[x86] fix assert with horizontal math + broadcast of vector (PR43402)
[llvm-core.git] / lib / Target / AVR / AVRRegisterInfo.h
blob8e6e63af3d579e4c4e3e590e2cff94b2b4d6250e
1 //===-- AVRRegisterInfo.h - AVR Register Information Impl -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_AVR_REGISTER_INFO_H
14 #define LLVM_AVR_REGISTER_INFO_H
16 #include "llvm/CodeGen/TargetRegisterInfo.h"
18 #define GET_REGINFO_HEADER
19 #include "AVRGenRegisterInfo.inc"
21 namespace llvm {
23 /// Utilities relating to AVR registers.
24 class AVRRegisterInfo : public AVRGenRegisterInfo {
25 public:
26 AVRRegisterInfo();
28 public:
29 const uint16_t *
30 getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
31 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
32 CallingConv::ID CC) const override;
33 BitVector getReservedRegs(const MachineFunction &MF) const override;
35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
37 const MachineFunction &MF) const override;
39 /// Stack Frame Processing Methods
40 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
41 unsigned FIOperandNum,
42 RegScavenger *RS = NULL) const override;
44 Register getFrameRegister(const MachineFunction &MF) const override;
46 const TargetRegisterClass *
47 getPointerRegClass(const MachineFunction &MF,
48 unsigned Kind = 0) const override;
50 /// Splits a 16-bit `DREGS` register into the lo/hi register pair.
51 /// \param Reg A 16-bit register to split.
52 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
54 bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
55 return true;
58 bool shouldCoalesce(MachineInstr *MI,
59 const TargetRegisterClass *SrcRC,
60 unsigned SubReg,
61 const TargetRegisterClass *DstRC,
62 unsigned DstSubReg,
63 const TargetRegisterClass *NewRC,
64 LiveIntervals &LIS) const override;
67 } // end namespace llvm
69 #endif // LLVM_AVR_REGISTER_INFO_H