1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "HexagonInstrInfo.h"
15 #include "HexagonFrameLowering.h"
16 #include "HexagonHazardRecognizer.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/CodeGen/DFAPacketizer.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetOpcodes.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/MC/MCInstrItineraries.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Support/BranchProbability.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MachineValueType.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
64 #define DEBUG_TYPE "hexagon-instrinfo"
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
68 #include "HexagonDepTimingClasses.h"
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
72 cl::opt
<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden
,
73 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74 "packetization boundary."));
76 static cl::opt
<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77 cl::Hidden
, cl::init(true), cl::desc("Enable branch prediction"));
79 static cl::opt
<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
80 cl::Hidden
, cl::ZeroOrMore
, cl::init(false),
81 cl::desc("Disable schedule adjustment for new value stores."));
83 static cl::opt
<bool> EnableTimingClassLatency(
84 "enable-timing-class-latency", cl::Hidden
, cl::init(false),
85 cl::desc("Enable timing class latency"));
87 static cl::opt
<bool> EnableALUForwarding(
88 "enable-alu-forwarding", cl::Hidden
, cl::init(true),
89 cl::desc("Enable vec alu forwarding"));
91 static cl::opt
<bool> EnableACCForwarding(
92 "enable-acc-forwarding", cl::Hidden
, cl::init(true),
93 cl::desc("Enable vec acc forwarding"));
95 static cl::opt
<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96 cl::init(true), cl::Hidden
, cl::ZeroOrMore
, cl::desc("branch relax asm"));
98 static cl::opt
<bool> UseDFAHazardRec("dfa-hazard-rec",
99 cl::init(true), cl::Hidden
, cl::ZeroOrMore
,
100 cl::desc("Use the DFA based hazard recognizer."));
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX
= 4095;
104 const int Hexagon_MEMW_OFFSET_MIN
= -4096;
105 const int Hexagon_MEMD_OFFSET_MAX
= 8191;
106 const int Hexagon_MEMD_OFFSET_MIN
= -8192;
107 const int Hexagon_MEMH_OFFSET_MAX
= 2047;
108 const int Hexagon_MEMH_OFFSET_MIN
= -2048;
109 const int Hexagon_MEMB_OFFSET_MAX
= 1023;
110 const int Hexagon_MEMB_OFFSET_MIN
= -1024;
111 const int Hexagon_ADDI_OFFSET_MAX
= 32767;
112 const int Hexagon_ADDI_OFFSET_MIN
= -32768;
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
117 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget
&ST
)
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN
, Hexagon::ADJCALLSTACKUP
),
121 static bool isIntRegForSubInst(unsigned Reg
) {
122 return (Reg
>= Hexagon::R0
&& Reg
<= Hexagon::R7
) ||
123 (Reg
>= Hexagon::R16
&& Reg
<= Hexagon::R23
);
126 static bool isDblRegForSubInst(unsigned Reg
, const HexagonRegisterInfo
&HRI
) {
127 return isIntRegForSubInst(HRI
.getSubReg(Reg
, Hexagon::isub_lo
)) &&
128 isIntRegForSubInst(HRI
.getSubReg(Reg
, Hexagon::isub_hi
));
131 /// Calculate number of instructions excluding the debug instructions.
132 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB
,
133 MachineBasicBlock::const_instr_iterator MIE
) {
135 for (; MIB
!= MIE
; ++MIB
) {
136 if (!MIB
->isDebugInstr())
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
146 MachineInstr
*HexagonInstrInfo::findLoopInstr(MachineBasicBlock
*BB
,
147 unsigned EndLoopOp
, MachineBasicBlock
*TargetBB
,
148 SmallPtrSet
<MachineBasicBlock
*, 8> &Visited
) const {
151 if (EndLoopOp
== Hexagon::ENDLOOP0
) {
152 LOOPi
= Hexagon::J2_loop0i
;
153 LOOPr
= Hexagon::J2_loop0r
;
154 } else { // EndLoopOp == Hexagon::EndLOOP1
155 LOOPi
= Hexagon::J2_loop1i
;
156 LOOPr
= Hexagon::J2_loop1r
;
159 // The loop set-up instruction will be in a predecessor block
160 for (MachineBasicBlock
*PB
: BB
->predecessors()) {
161 // If this has been visited, already skip it.
162 if (!Visited
.insert(PB
).second
)
166 for (auto I
= PB
->instr_rbegin(), E
= PB
->instr_rend(); I
!= E
; ++I
) {
167 unsigned Opc
= I
->getOpcode();
168 if (Opc
== LOOPi
|| Opc
== LOOPr
)
170 // We've reached a different loop, which means the loop01 has been
172 if (Opc
== EndLoopOp
&& I
->getOperand(0).getMBB() != TargetBB
)
175 // Check the predecessors for the LOOP instruction.
176 if (MachineInstr
*Loop
= findLoopInstr(PB
, EndLoopOp
, TargetBB
, Visited
))
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
185 static inline void parseOperands(const MachineInstr
&MI
,
186 SmallVector
<unsigned, 4> &Defs
, SmallVector
<unsigned, 8> &Uses
) {
190 for (unsigned i
= 0, e
= MI
.getNumOperands(); i
!= e
; ++i
) {
191 const MachineOperand
&MO
= MI
.getOperand(i
);
196 Register Reg
= MO
.getReg();
201 Uses
.push_back(MO
.getReg());
204 Defs
.push_back(MO
.getReg());
208 // Position dependent, so check twice for swap.
209 static bool isDuplexPairMatch(unsigned Ga
, unsigned Gb
) {
211 case HexagonII::HSIG_None
:
214 case HexagonII::HSIG_L1
:
215 return (Gb
== HexagonII::HSIG_L1
|| Gb
== HexagonII::HSIG_A
);
216 case HexagonII::HSIG_L2
:
217 return (Gb
== HexagonII::HSIG_L1
|| Gb
== HexagonII::HSIG_L2
||
218 Gb
== HexagonII::HSIG_A
);
219 case HexagonII::HSIG_S1
:
220 return (Gb
== HexagonII::HSIG_L1
|| Gb
== HexagonII::HSIG_L2
||
221 Gb
== HexagonII::HSIG_S1
|| Gb
== HexagonII::HSIG_A
);
222 case HexagonII::HSIG_S2
:
223 return (Gb
== HexagonII::HSIG_L1
|| Gb
== HexagonII::HSIG_L2
||
224 Gb
== HexagonII::HSIG_S1
|| Gb
== HexagonII::HSIG_S2
||
225 Gb
== HexagonII::HSIG_A
);
226 case HexagonII::HSIG_A
:
227 return (Gb
== HexagonII::HSIG_A
);
228 case HexagonII::HSIG_Compound
:
229 return (Gb
== HexagonII::HSIG_Compound
);
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
239 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr
&MI
,
240 int &FrameIndex
) const {
241 switch (MI
.getOpcode()) {
244 case Hexagon::L2_loadri_io
:
245 case Hexagon::L2_loadrd_io
:
246 case Hexagon::V6_vL32b_ai
:
247 case Hexagon::V6_vL32b_nt_ai
:
248 case Hexagon::V6_vL32Ub_ai
:
249 case Hexagon::LDriw_pred
:
250 case Hexagon::LDriw_ctr
:
251 case Hexagon::PS_vloadrq_ai
:
252 case Hexagon::PS_vloadrw_ai
:
253 case Hexagon::PS_vloadrw_nt_ai
: {
254 const MachineOperand OpFI
= MI
.getOperand(1);
257 const MachineOperand OpOff
= MI
.getOperand(2);
258 if (!OpOff
.isImm() || OpOff
.getImm() != 0)
260 FrameIndex
= OpFI
.getIndex();
261 return MI
.getOperand(0).getReg();
264 case Hexagon::L2_ploadrit_io
:
265 case Hexagon::L2_ploadrif_io
:
266 case Hexagon::L2_ploadrdt_io
:
267 case Hexagon::L2_ploadrdf_io
: {
268 const MachineOperand OpFI
= MI
.getOperand(2);
271 const MachineOperand OpOff
= MI
.getOperand(3);
272 if (!OpOff
.isImm() || OpOff
.getImm() != 0)
274 FrameIndex
= OpFI
.getIndex();
275 return MI
.getOperand(0).getReg();
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
287 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr
&MI
,
288 int &FrameIndex
) const {
289 switch (MI
.getOpcode()) {
292 case Hexagon::S2_storerb_io
:
293 case Hexagon::S2_storerh_io
:
294 case Hexagon::S2_storeri_io
:
295 case Hexagon::S2_storerd_io
:
296 case Hexagon::V6_vS32b_ai
:
297 case Hexagon::V6_vS32Ub_ai
:
298 case Hexagon::STriw_pred
:
299 case Hexagon::STriw_ctr
:
300 case Hexagon::PS_vstorerq_ai
:
301 case Hexagon::PS_vstorerw_ai
: {
302 const MachineOperand
&OpFI
= MI
.getOperand(0);
305 const MachineOperand
&OpOff
= MI
.getOperand(1);
306 if (!OpOff
.isImm() || OpOff
.getImm() != 0)
308 FrameIndex
= OpFI
.getIndex();
309 return MI
.getOperand(2).getReg();
312 case Hexagon::S2_pstorerbt_io
:
313 case Hexagon::S2_pstorerbf_io
:
314 case Hexagon::S2_pstorerht_io
:
315 case Hexagon::S2_pstorerhf_io
:
316 case Hexagon::S2_pstorerit_io
:
317 case Hexagon::S2_pstorerif_io
:
318 case Hexagon::S2_pstorerdt_io
:
319 case Hexagon::S2_pstorerdf_io
: {
320 const MachineOperand
&OpFI
= MI
.getOperand(1);
323 const MachineOperand
&OpOff
= MI
.getOperand(2);
324 if (!OpOff
.isImm() || OpOff
.getImm() != 0)
326 FrameIndex
= OpFI
.getIndex();
327 return MI
.getOperand(3).getReg();
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
337 bool HexagonInstrInfo::hasLoadFromStackSlot(
338 const MachineInstr
&MI
,
339 SmallVectorImpl
<const MachineMemOperand
*> &Accesses
) const {
341 const MachineBasicBlock
*MBB
= MI
.getParent();
342 MachineBasicBlock::const_instr_iterator MII
= MI
.getIterator();
343 for (++MII
; MII
!= MBB
->instr_end() && MII
->isInsideBundle(); ++MII
)
344 if (TargetInstrInfo::hasLoadFromStackSlot(*MII
, Accesses
))
349 return TargetInstrInfo::hasLoadFromStackSlot(MI
, Accesses
);
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
355 bool HexagonInstrInfo::hasStoreToStackSlot(
356 const MachineInstr
&MI
,
357 SmallVectorImpl
<const MachineMemOperand
*> &Accesses
) const {
359 const MachineBasicBlock
*MBB
= MI
.getParent();
360 MachineBasicBlock::const_instr_iterator MII
= MI
.getIterator();
361 for (++MII
; MII
!= MBB
->instr_end() && MII
->isInsideBundle(); ++MII
)
362 if (TargetInstrInfo::hasStoreToStackSlot(*MII
, Accesses
))
367 return TargetInstrInfo::hasStoreToStackSlot(MI
, Accesses
);
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
379 /// Cond[0] = ENDLOOP
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
385 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock
&MBB
,
386 MachineBasicBlock
*&TBB
,
387 MachineBasicBlock
*&FBB
,
388 SmallVectorImpl
<MachineOperand
> &Cond
,
389 bool AllowModify
) const {
394 // If the block has no terminators, it just falls into the block after it.
395 MachineBasicBlock::instr_iterator I
= MBB
.instr_end();
396 if (I
== MBB
.instr_begin())
399 // A basic block may looks like this:
409 // It has two succs but does not have a terminator
410 // Don't know how to handle it.
414 // Don't analyze EH branches.
416 } while (I
!= MBB
.instr_begin());
421 while (I
->isDebugInstr()) {
422 if (I
== MBB
.instr_begin())
427 bool JumpToBlock
= I
->getOpcode() == Hexagon::J2_jump
&&
428 I
->getOperand(0).isMBB();
429 // Delete the J2_jump if it's equivalent to a fall-through.
430 if (AllowModify
&& JumpToBlock
&&
431 MBB
.isLayoutSuccessor(I
->getOperand(0).getMBB())) {
432 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433 I
->eraseFromParent();
435 if (I
== MBB
.instr_begin())
439 if (!isUnpredicatedTerminator(*I
))
442 // Get the last instruction in the block.
443 MachineInstr
*LastInst
= &*I
;
444 MachineInstr
*SecondLastInst
= nullptr;
445 // Find one more terminator if present.
447 if (&*I
!= LastInst
&& !I
->isBundle() && isUnpredicatedTerminator(*I
)) {
449 SecondLastInst
= &*I
;
451 // This is a third branch.
454 if (I
== MBB
.instr_begin())
459 int LastOpcode
= LastInst
->getOpcode();
460 int SecLastOpcode
= SecondLastInst
? SecondLastInst
->getOpcode() : 0;
461 // If the branch target is not a basic block, it could be a tail call.
462 // (It is, if the target is a function.)
463 if (LastOpcode
== Hexagon::J2_jump
&& !LastInst
->getOperand(0).isMBB())
465 if (SecLastOpcode
== Hexagon::J2_jump
&&
466 !SecondLastInst
->getOperand(0).isMBB())
469 bool LastOpcodeHasJMP_c
= PredOpcodeHasJMP_c(LastOpcode
);
470 bool LastOpcodeHasNVJump
= isNewValueJump(*LastInst
);
472 if (LastOpcodeHasJMP_c
&& !LastInst
->getOperand(1).isMBB())
475 // If there is only one terminator instruction, process it.
476 if (LastInst
&& !SecondLastInst
) {
477 if (LastOpcode
== Hexagon::J2_jump
) {
478 TBB
= LastInst
->getOperand(0).getMBB();
481 if (isEndLoopN(LastOpcode
)) {
482 TBB
= LastInst
->getOperand(0).getMBB();
483 Cond
.push_back(MachineOperand::CreateImm(LastInst
->getOpcode()));
484 Cond
.push_back(LastInst
->getOperand(0));
487 if (LastOpcodeHasJMP_c
) {
488 TBB
= LastInst
->getOperand(1).getMBB();
489 Cond
.push_back(MachineOperand::CreateImm(LastInst
->getOpcode()));
490 Cond
.push_back(LastInst
->getOperand(0));
493 // Only supporting rr/ri versions of new-value jumps.
494 if (LastOpcodeHasNVJump
&& (LastInst
->getNumExplicitOperands() == 3)) {
495 TBB
= LastInst
->getOperand(2).getMBB();
496 Cond
.push_back(MachineOperand::CreateImm(LastInst
->getOpcode()));
497 Cond
.push_back(LastInst
->getOperand(0));
498 Cond
.push_back(LastInst
->getOperand(1));
501 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB
)
502 << " with one jump\n";);
503 // Otherwise, don't know what this is.
507 bool SecLastOpcodeHasJMP_c
= PredOpcodeHasJMP_c(SecLastOpcode
);
508 bool SecLastOpcodeHasNVJump
= isNewValueJump(*SecondLastInst
);
509 if (SecLastOpcodeHasJMP_c
&& (LastOpcode
== Hexagon::J2_jump
)) {
510 if (!SecondLastInst
->getOperand(1).isMBB())
512 TBB
= SecondLastInst
->getOperand(1).getMBB();
513 Cond
.push_back(MachineOperand::CreateImm(SecondLastInst
->getOpcode()));
514 Cond
.push_back(SecondLastInst
->getOperand(0));
515 FBB
= LastInst
->getOperand(0).getMBB();
519 // Only supporting rr/ri versions of new-value jumps.
520 if (SecLastOpcodeHasNVJump
&&
521 (SecondLastInst
->getNumExplicitOperands() == 3) &&
522 (LastOpcode
== Hexagon::J2_jump
)) {
523 TBB
= SecondLastInst
->getOperand(2).getMBB();
524 Cond
.push_back(MachineOperand::CreateImm(SecondLastInst
->getOpcode()));
525 Cond
.push_back(SecondLastInst
->getOperand(0));
526 Cond
.push_back(SecondLastInst
->getOperand(1));
527 FBB
= LastInst
->getOperand(0).getMBB();
531 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532 // executed, so remove it.
533 if (SecLastOpcode
== Hexagon::J2_jump
&& LastOpcode
== Hexagon::J2_jump
) {
534 TBB
= SecondLastInst
->getOperand(0).getMBB();
535 I
= LastInst
->getIterator();
537 I
->eraseFromParent();
541 // If the block ends with an ENDLOOP, and J2_jump, handle it.
542 if (isEndLoopN(SecLastOpcode
) && LastOpcode
== Hexagon::J2_jump
) {
543 TBB
= SecondLastInst
->getOperand(0).getMBB();
544 Cond
.push_back(MachineOperand::CreateImm(SecondLastInst
->getOpcode()));
545 Cond
.push_back(SecondLastInst
->getOperand(0));
546 FBB
= LastInst
->getOperand(0).getMBB();
549 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB
)
550 << " with two jumps";);
551 // Otherwise, can't handle this.
555 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock
&MBB
,
556 int *BytesRemoved
) const {
557 assert(!BytesRemoved
&& "code size not handled");
559 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB
));
560 MachineBasicBlock::iterator I
= MBB
.end();
562 while (I
!= MBB
.begin()) {
564 if (I
->isDebugInstr())
566 // Only removing branches from end of MBB.
569 if (Count
&& (I
->getOpcode() == Hexagon::J2_jump
))
570 llvm_unreachable("Malformed basic block: unconditional branch not last");
571 MBB
.erase(&MBB
.back());
578 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock
&MBB
,
579 MachineBasicBlock
*TBB
,
580 MachineBasicBlock
*FBB
,
581 ArrayRef
<MachineOperand
> Cond
,
583 int *BytesAdded
) const {
584 unsigned BOpc
= Hexagon::J2_jump
;
585 unsigned BccOpc
= Hexagon::J2_jumpt
;
586 assert(validateBranchCond(Cond
) && "Invalid branching condition");
587 assert(TBB
&& "insertBranch must not be told to insert a fallthrough");
588 assert(!BytesAdded
&& "code size not handled");
590 // Check if reverseBranchCondition has asked to reverse this branch
591 // If we want to reverse the branch an odd number of times, we want
593 if (!Cond
.empty() && Cond
[0].isImm())
594 BccOpc
= Cond
[0].getImm();
598 // Due to a bug in TailMerging/CFG Optimization, we need to add a
599 // special case handling of a predicated jump followed by an
600 // unconditional jump. If not, Tail Merging and CFG Optimization go
601 // into an infinite loop.
602 MachineBasicBlock
*NewTBB
, *NewFBB
;
603 SmallVector
<MachineOperand
, 4> Cond
;
604 auto Term
= MBB
.getFirstTerminator();
605 if (Term
!= MBB
.end() && isPredicated(*Term
) &&
606 !analyzeBranch(MBB
, NewTBB
, NewFBB
, Cond
, false) &&
607 MachineFunction::iterator(NewTBB
) == ++MBB
.getIterator()) {
608 reverseBranchCondition(Cond
);
610 return insertBranch(MBB
, TBB
, nullptr, Cond
, DL
);
612 BuildMI(&MBB
, DL
, get(BOpc
)).addMBB(TBB
);
613 } else if (isEndLoopN(Cond
[0].getImm())) {
614 int EndLoopOp
= Cond
[0].getImm();
615 assert(Cond
[1].isMBB());
616 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617 // Check for it, and change the BB target if needed.
618 SmallPtrSet
<MachineBasicBlock
*, 8> VisitedBBs
;
619 MachineInstr
*Loop
= findLoopInstr(TBB
, EndLoopOp
, Cond
[1].getMBB(),
621 assert(Loop
!= nullptr && "Inserting an ENDLOOP without a LOOP");
622 Loop
->getOperand(0).setMBB(TBB
);
623 // Add the ENDLOOP after the finding the LOOP0.
624 BuildMI(&MBB
, DL
, get(EndLoopOp
)).addMBB(TBB
);
625 } else if (isNewValueJump(Cond
[0].getImm())) {
626 assert((Cond
.size() == 3) && "Only supporting rr/ri version of nvjump");
628 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630 unsigned Flags1
= getUndefRegState(Cond
[1].isUndef());
631 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632 << printMBBReference(MBB
););
633 if (Cond
[2].isReg()) {
634 unsigned Flags2
= getUndefRegState(Cond
[2].isUndef());
635 BuildMI(&MBB
, DL
, get(BccOpc
)).addReg(Cond
[1].getReg(), Flags1
).
636 addReg(Cond
[2].getReg(), Flags2
).addMBB(TBB
);
637 } else if(Cond
[2].isImm()) {
638 BuildMI(&MBB
, DL
, get(BccOpc
)).addReg(Cond
[1].getReg(), Flags1
).
639 addImm(Cond
[2].getImm()).addMBB(TBB
);
641 llvm_unreachable("Invalid condition for branching");
643 assert((Cond
.size() == 2) && "Malformed cond vector");
644 const MachineOperand
&RO
= Cond
[1];
645 unsigned Flags
= getUndefRegState(RO
.isUndef());
646 BuildMI(&MBB
, DL
, get(BccOpc
)).addReg(RO
.getReg(), Flags
).addMBB(TBB
);
650 assert((!Cond
.empty()) &&
651 "Cond. cannot be empty when multiple branchings are required");
652 assert((!isNewValueJump(Cond
[0].getImm())) &&
653 "NV-jump cannot be inserted with another branch");
654 // Special case for hardware loops. The condition is a basic block.
655 if (isEndLoopN(Cond
[0].getImm())) {
656 int EndLoopOp
= Cond
[0].getImm();
657 assert(Cond
[1].isMBB());
658 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659 // Check for it, and change the BB target if needed.
660 SmallPtrSet
<MachineBasicBlock
*, 8> VisitedBBs
;
661 MachineInstr
*Loop
= findLoopInstr(TBB
, EndLoopOp
, Cond
[1].getMBB(),
663 assert(Loop
!= nullptr && "Inserting an ENDLOOP without a LOOP");
664 Loop
->getOperand(0).setMBB(TBB
);
665 // Add the ENDLOOP after the finding the LOOP0.
666 BuildMI(&MBB
, DL
, get(EndLoopOp
)).addMBB(TBB
);
668 const MachineOperand
&RO
= Cond
[1];
669 unsigned Flags
= getUndefRegState(RO
.isUndef());
670 BuildMI(&MBB
, DL
, get(BccOpc
)).addReg(RO
.getReg(), Flags
).addMBB(TBB
);
672 BuildMI(&MBB
, DL
, get(BOpc
)).addMBB(FBB
);
678 class HexagonPipelinerLoopInfo
: public TargetInstrInfo::PipelinerLoopInfo
{
679 MachineInstr
*Loop
, *EndLoop
;
681 const HexagonInstrInfo
*TII
;
687 HexagonPipelinerLoopInfo(MachineInstr
*Loop
, MachineInstr
*EndLoop
)
688 : Loop(Loop
), EndLoop(EndLoop
), MF(Loop
->getParent()->getParent()),
689 TII(MF
->getSubtarget
<HexagonSubtarget
>().getInstrInfo()),
690 DL(Loop
->getDebugLoc()) {
691 // Inspect the Loop instruction up-front, as it may be deleted when we call
692 // createTripCountGreaterCondition.
693 TripCount
= Loop
->getOpcode() == Hexagon::J2_loop0r
695 : Loop
->getOperand(1).getImm();
697 LoopCount
= Loop
->getOperand(1).getReg();
700 bool shouldIgnoreForPipelining(const MachineInstr
*MI
) const override
{
701 // Only ignore the terminator.
702 return MI
== EndLoop
;
706 createTripCountGreaterCondition(int TC
, MachineBasicBlock
&MBB
,
707 SmallVectorImpl
<MachineOperand
> &Cond
) override
{
708 if (TripCount
== -1) {
709 // Check if we're done with the loop.
710 unsigned Done
= TII
->createVR(MF
, MVT::i1
);
711 MachineInstr
*NewCmp
= BuildMI(&MBB
, DL
,
712 TII
->get(Hexagon::C2_cmpgtui
), Done
)
715 Cond
.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf
));
716 Cond
.push_back(NewCmp
->getOperand(0));
720 return TripCount
> TC
;
723 void setPreheader(MachineBasicBlock
*NewPreheader
) override
{
724 NewPreheader
->splice(NewPreheader
->getFirstTerminator(), Loop
->getParent(),
728 void adjustTripCount(int TripCountAdjust
) override
{
729 // If the loop trip count is a compile-time value, then just change the
731 if (Loop
->getOpcode() == Hexagon::J2_loop0i
||
732 Loop
->getOpcode() == Hexagon::J2_loop1i
) {
733 int64_t TripCount
= Loop
->getOperand(1).getImm() + TripCountAdjust
;
734 assert(TripCount
> 0 && "Can't create an empty or negative loop!");
735 Loop
->getOperand(1).setImm(TripCount
);
739 // The loop trip count is a run-time value. We generate code to subtract
740 // one from the trip count, and update the loop instruction.
741 Register LoopCount
= Loop
->getOperand(1).getReg();
742 Register NewLoopCount
= TII
->createVR(MF
, MVT::i32
);
743 BuildMI(*Loop
->getParent(), Loop
, Loop
->getDebugLoc(),
744 TII
->get(Hexagon::A2_addi
), NewLoopCount
)
746 .addImm(TripCountAdjust
);
747 Loop
->getOperand(1).setReg(NewLoopCount
);
750 void disposed() override
{ Loop
->eraseFromParent(); }
754 std::unique_ptr
<TargetInstrInfo::PipelinerLoopInfo
>
755 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock
*LoopBB
) const {
756 // We really "analyze" only hardware loops right now.
757 MachineBasicBlock::iterator I
= LoopBB
->getFirstTerminator();
759 if (I
!= LoopBB
->end() && isEndLoopN(I
->getOpcode())) {
760 SmallPtrSet
<MachineBasicBlock
*, 8> VisitedBBs
;
761 MachineInstr
*LoopInst
= findLoopInstr(
762 LoopBB
, I
->getOpcode(), I
->getOperand(0).getMBB(), VisitedBBs
);
764 return std::make_unique
<HexagonPipelinerLoopInfo
>(LoopInst
, &*I
);
769 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock
&MBB
,
770 unsigned NumCycles
, unsigned ExtraPredCycles
,
771 BranchProbability Probability
) const {
772 return nonDbgBBSize(&MBB
) <= 3;
775 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock
&TMBB
,
776 unsigned NumTCycles
, unsigned ExtraTCycles
, MachineBasicBlock
&FMBB
,
777 unsigned NumFCycles
, unsigned ExtraFCycles
, BranchProbability Probability
)
779 return nonDbgBBSize(&TMBB
) <= 3 && nonDbgBBSize(&FMBB
) <= 3;
782 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock
&MBB
,
783 unsigned NumInstrs
, BranchProbability Probability
) const {
784 return NumInstrs
<= 4;
787 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock
&MBB
,
788 MachineBasicBlock::iterator I
,
789 const DebugLoc
&DL
, unsigned DestReg
,
790 unsigned SrcReg
, bool KillSrc
) const {
791 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
792 unsigned KillFlag
= getKillRegState(KillSrc
);
794 if (Hexagon::IntRegsRegClass
.contains(SrcReg
, DestReg
)) {
795 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfr
), DestReg
)
796 .addReg(SrcReg
, KillFlag
);
799 if (Hexagon::DoubleRegsRegClass
.contains(SrcReg
, DestReg
)) {
800 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrp
), DestReg
)
801 .addReg(SrcReg
, KillFlag
);
804 if (Hexagon::PredRegsRegClass
.contains(SrcReg
, DestReg
)) {
805 // Map Pd = Ps to Pd = or(Ps, Ps).
806 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_or
), DestReg
)
807 .addReg(SrcReg
).addReg(SrcReg
, KillFlag
);
810 if (Hexagon::CtrRegsRegClass
.contains(DestReg
) &&
811 Hexagon::IntRegsRegClass
.contains(SrcReg
)) {
812 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrrcr
), DestReg
)
813 .addReg(SrcReg
, KillFlag
);
816 if (Hexagon::IntRegsRegClass
.contains(DestReg
) &&
817 Hexagon::CtrRegsRegClass
.contains(SrcReg
)) {
818 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrcrr
), DestReg
)
819 .addReg(SrcReg
, KillFlag
);
822 if (Hexagon::ModRegsRegClass
.contains(DestReg
) &&
823 Hexagon::IntRegsRegClass
.contains(SrcReg
)) {
824 BuildMI(MBB
, I
, DL
, get(Hexagon::A2_tfrrcr
), DestReg
)
825 .addReg(SrcReg
, KillFlag
);
828 if (Hexagon::PredRegsRegClass
.contains(SrcReg
) &&
829 Hexagon::IntRegsRegClass
.contains(DestReg
)) {
830 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_tfrpr
), DestReg
)
831 .addReg(SrcReg
, KillFlag
);
834 if (Hexagon::IntRegsRegClass
.contains(SrcReg
) &&
835 Hexagon::PredRegsRegClass
.contains(DestReg
)) {
836 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_tfrrp
), DestReg
)
837 .addReg(SrcReg
, KillFlag
);
840 if (Hexagon::PredRegsRegClass
.contains(SrcReg
) &&
841 Hexagon::IntRegsRegClass
.contains(DestReg
)) {
842 BuildMI(MBB
, I
, DL
, get(Hexagon::C2_tfrpr
), DestReg
)
843 .addReg(SrcReg
, KillFlag
);
846 if (Hexagon::HvxVRRegClass
.contains(SrcReg
, DestReg
)) {
847 BuildMI(MBB
, I
, DL
, get(Hexagon::V6_vassign
), DestReg
).
848 addReg(SrcReg
, KillFlag
);
851 if (Hexagon::HvxWRRegClass
.contains(SrcReg
, DestReg
)) {
852 Register LoSrc
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_lo
);
853 Register HiSrc
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_hi
);
854 BuildMI(MBB
, I
, DL
, get(Hexagon::V6_vcombine
), DestReg
)
855 .addReg(HiSrc
, KillFlag
)
856 .addReg(LoSrc
, KillFlag
);
859 if (Hexagon::HvxQRRegClass
.contains(SrcReg
, DestReg
)) {
860 BuildMI(MBB
, I
, DL
, get(Hexagon::V6_pred_and
), DestReg
)
862 .addReg(SrcReg
, KillFlag
);
865 if (Hexagon::HvxQRRegClass
.contains(SrcReg
) &&
866 Hexagon::HvxVRRegClass
.contains(DestReg
)) {
867 llvm_unreachable("Unimplemented pred to vec");
870 if (Hexagon::HvxQRRegClass
.contains(DestReg
) &&
871 Hexagon::HvxVRRegClass
.contains(SrcReg
)) {
872 llvm_unreachable("Unimplemented vec to pred");
877 // Show the invalid registers to ease debugging.
878 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB
) << ": "
879 << printReg(DestReg
, &HRI
) << " = " << printReg(SrcReg
, &HRI
) << '\n';
881 llvm_unreachable("Unimplemented");
884 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock
&MBB
,
885 MachineBasicBlock::iterator I
, unsigned SrcReg
, bool isKill
, int FI
,
886 const TargetRegisterClass
*RC
, const TargetRegisterInfo
*TRI
) const {
887 DebugLoc DL
= MBB
.findDebugLoc(I
);
888 MachineFunction
&MF
= *MBB
.getParent();
889 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
890 unsigned SlotAlign
= MFI
.getObjectAlignment(FI
);
891 unsigned RegAlign
= TRI
->getSpillAlignment(*RC
);
892 unsigned KillFlag
= getKillRegState(isKill
);
893 bool HasAlloca
= MFI
.hasVarSizedObjects();
894 const HexagonFrameLowering
&HFI
= *Subtarget
.getFrameLowering();
896 MachineMemOperand
*MMO
= MF
.getMachineMemOperand(
897 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOStore
,
898 MFI
.getObjectSize(FI
), SlotAlign
);
900 if (Hexagon::IntRegsRegClass
.hasSubClassEq(RC
)) {
901 BuildMI(MBB
, I
, DL
, get(Hexagon::S2_storeri_io
))
902 .addFrameIndex(FI
).addImm(0)
903 .addReg(SrcReg
, KillFlag
).addMemOperand(MMO
);
904 } else if (Hexagon::DoubleRegsRegClass
.hasSubClassEq(RC
)) {
905 BuildMI(MBB
, I
, DL
, get(Hexagon::S2_storerd_io
))
906 .addFrameIndex(FI
).addImm(0)
907 .addReg(SrcReg
, KillFlag
).addMemOperand(MMO
);
908 } else if (Hexagon::PredRegsRegClass
.hasSubClassEq(RC
)) {
909 BuildMI(MBB
, I
, DL
, get(Hexagon::STriw_pred
))
910 .addFrameIndex(FI
).addImm(0)
911 .addReg(SrcReg
, KillFlag
).addMemOperand(MMO
);
912 } else if (Hexagon::ModRegsRegClass
.hasSubClassEq(RC
)) {
913 BuildMI(MBB
, I
, DL
, get(Hexagon::STriw_ctr
))
914 .addFrameIndex(FI
).addImm(0)
915 .addReg(SrcReg
, KillFlag
).addMemOperand(MMO
);
916 } else if (Hexagon::HvxQRRegClass
.hasSubClassEq(RC
)) {
917 BuildMI(MBB
, I
, DL
, get(Hexagon::PS_vstorerq_ai
))
918 .addFrameIndex(FI
).addImm(0)
919 .addReg(SrcReg
, KillFlag
).addMemOperand(MMO
);
920 } else if (Hexagon::HvxVRRegClass
.hasSubClassEq(RC
)) {
921 // If there are variable-sized objects, spills will not be aligned.
923 SlotAlign
= HFI
.getStackAlignment();
924 unsigned Opc
= SlotAlign
< RegAlign
? Hexagon::V6_vS32Ub_ai
925 : Hexagon::V6_vS32b_ai
;
926 MachineMemOperand
*MMOA
= MF
.getMachineMemOperand(
927 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOStore
,
928 MFI
.getObjectSize(FI
), SlotAlign
);
929 BuildMI(MBB
, I
, DL
, get(Opc
))
930 .addFrameIndex(FI
).addImm(0)
931 .addReg(SrcReg
, KillFlag
).addMemOperand(MMOA
);
932 } else if (Hexagon::HvxWRRegClass
.hasSubClassEq(RC
)) {
933 // If there are variable-sized objects, spills will not be aligned.
935 SlotAlign
= HFI
.getStackAlignment();
936 unsigned Opc
= SlotAlign
< RegAlign
? Hexagon::PS_vstorerwu_ai
937 : Hexagon::PS_vstorerw_ai
;
938 MachineMemOperand
*MMOA
= MF
.getMachineMemOperand(
939 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOStore
,
940 MFI
.getObjectSize(FI
), SlotAlign
);
941 BuildMI(MBB
, I
, DL
, get(Opc
))
942 .addFrameIndex(FI
).addImm(0)
943 .addReg(SrcReg
, KillFlag
).addMemOperand(MMOA
);
945 llvm_unreachable("Unimplemented");
949 void HexagonInstrInfo::loadRegFromStackSlot(
950 MachineBasicBlock
&MBB
, MachineBasicBlock::iterator I
, unsigned DestReg
,
951 int FI
, const TargetRegisterClass
*RC
,
952 const TargetRegisterInfo
*TRI
) const {
953 DebugLoc DL
= MBB
.findDebugLoc(I
);
954 MachineFunction
&MF
= *MBB
.getParent();
955 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
956 unsigned SlotAlign
= MFI
.getObjectAlignment(FI
);
957 unsigned RegAlign
= TRI
->getSpillAlignment(*RC
);
958 bool HasAlloca
= MFI
.hasVarSizedObjects();
959 const HexagonFrameLowering
&HFI
= *Subtarget
.getFrameLowering();
961 MachineMemOperand
*MMO
= MF
.getMachineMemOperand(
962 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOLoad
,
963 MFI
.getObjectSize(FI
), SlotAlign
);
965 if (Hexagon::IntRegsRegClass
.hasSubClassEq(RC
)) {
966 BuildMI(MBB
, I
, DL
, get(Hexagon::L2_loadri_io
), DestReg
)
967 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
968 } else if (Hexagon::DoubleRegsRegClass
.hasSubClassEq(RC
)) {
969 BuildMI(MBB
, I
, DL
, get(Hexagon::L2_loadrd_io
), DestReg
)
970 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
971 } else if (Hexagon::PredRegsRegClass
.hasSubClassEq(RC
)) {
972 BuildMI(MBB
, I
, DL
, get(Hexagon::LDriw_pred
), DestReg
)
973 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
974 } else if (Hexagon::ModRegsRegClass
.hasSubClassEq(RC
)) {
975 BuildMI(MBB
, I
, DL
, get(Hexagon::LDriw_ctr
), DestReg
)
976 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
977 } else if (Hexagon::HvxQRRegClass
.hasSubClassEq(RC
)) {
978 BuildMI(MBB
, I
, DL
, get(Hexagon::PS_vloadrq_ai
), DestReg
)
979 .addFrameIndex(FI
).addImm(0).addMemOperand(MMO
);
980 } else if (Hexagon::HvxVRRegClass
.hasSubClassEq(RC
)) {
981 // If there are variable-sized objects, spills will not be aligned.
983 SlotAlign
= HFI
.getStackAlignment();
984 unsigned Opc
= SlotAlign
< RegAlign
? Hexagon::V6_vL32Ub_ai
985 : Hexagon::V6_vL32b_ai
;
986 MachineMemOperand
*MMOA
= MF
.getMachineMemOperand(
987 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOLoad
,
988 MFI
.getObjectSize(FI
), SlotAlign
);
989 BuildMI(MBB
, I
, DL
, get(Opc
), DestReg
)
990 .addFrameIndex(FI
).addImm(0).addMemOperand(MMOA
);
991 } else if (Hexagon::HvxWRRegClass
.hasSubClassEq(RC
)) {
992 // If there are variable-sized objects, spills will not be aligned.
994 SlotAlign
= HFI
.getStackAlignment();
995 unsigned Opc
= SlotAlign
< RegAlign
? Hexagon::PS_vloadrwu_ai
996 : Hexagon::PS_vloadrw_ai
;
997 MachineMemOperand
*MMOA
= MF
.getMachineMemOperand(
998 MachinePointerInfo::getFixedStack(MF
, FI
), MachineMemOperand::MOLoad
,
999 MFI
.getObjectSize(FI
), SlotAlign
);
1000 BuildMI(MBB
, I
, DL
, get(Opc
), DestReg
)
1001 .addFrameIndex(FI
).addImm(0).addMemOperand(MMOA
);
1003 llvm_unreachable("Can't store this register to stack slot");
1007 static void getLiveRegsAt(LivePhysRegs
&Regs
, const MachineInstr
&MI
) {
1008 const MachineBasicBlock
&B
= *MI
.getParent();
1009 Regs
.addLiveOuts(B
);
1010 auto E
= ++MachineBasicBlock::const_iterator(MI
.getIterator()).getReverse();
1011 for (auto I
= B
.rbegin(); I
!= E
; ++I
)
1012 Regs
.stepBackward(*I
);
1015 /// expandPostRAPseudo - This function is called for all pseudo instructions
1016 /// that remain after register allocation. Many pseudo instructions are
1017 /// created to help register allocation. This is the place to convert them
1018 /// into real instructions. The target can edit MI in place, or it can insert
1019 /// new instructions and erase MI. The function should return true if
1020 /// anything was changed.
1021 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr
&MI
) const {
1022 MachineBasicBlock
&MBB
= *MI
.getParent();
1023 MachineFunction
&MF
= *MBB
.getParent();
1024 MachineRegisterInfo
&MRI
= MF
.getRegInfo();
1025 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
1026 DebugLoc DL
= MI
.getDebugLoc();
1027 unsigned Opc
= MI
.getOpcode();
1029 auto RealCirc
= [&](unsigned Opc
, bool HasImm
, unsigned MxOp
) {
1030 Register Mx
= MI
.getOperand(MxOp
).getReg();
1031 unsigned CSx
= (Mx
== Hexagon::M0
? Hexagon::CS0
: Hexagon::CS1
);
1032 BuildMI(MBB
, MI
, DL
, get(Hexagon::A2_tfrrcr
), CSx
)
1033 .add(MI
.getOperand((HasImm
? 5 : 4)));
1034 auto MIB
= BuildMI(MBB
, MI
, DL
, get(Opc
)).add(MI
.getOperand(0))
1035 .add(MI
.getOperand(1)).add(MI
.getOperand(2)).add(MI
.getOperand(3));
1037 MIB
.add(MI
.getOperand(4));
1038 MIB
.addReg(CSx
, RegState::Implicit
);
1044 case TargetOpcode::COPY
: {
1045 MachineOperand
&MD
= MI
.getOperand(0);
1046 MachineOperand
&MS
= MI
.getOperand(1);
1047 MachineBasicBlock::iterator MBBI
= MI
.getIterator();
1048 if (MD
.getReg() != MS
.getReg() && !MS
.isUndef()) {
1049 copyPhysReg(MBB
, MI
, DL
, MD
.getReg(), MS
.getReg(), MS
.isKill());
1050 std::prev(MBBI
)->copyImplicitOps(*MBB
.getParent(), MI
);
1055 case Hexagon::PS_aligna
:
1056 BuildMI(MBB
, MI
, DL
, get(Hexagon::A2_andir
), MI
.getOperand(0).getReg())
1057 .addReg(HRI
.getFrameRegister())
1058 .addImm(-MI
.getOperand(1).getImm());
1061 case Hexagon::V6_vassignp
: {
1062 Register SrcReg
= MI
.getOperand(1).getReg();
1063 Register DstReg
= MI
.getOperand(0).getReg();
1064 unsigned Kill
= getKillRegState(MI
.getOperand(1).isKill());
1065 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vcombine
), DstReg
)
1066 .addReg(HRI
.getSubReg(SrcReg
, Hexagon::vsub_hi
), Kill
)
1067 .addReg(HRI
.getSubReg(SrcReg
, Hexagon::vsub_lo
), Kill
);
1071 case Hexagon::V6_lo
: {
1072 Register SrcReg
= MI
.getOperand(1).getReg();
1073 Register DstReg
= MI
.getOperand(0).getReg();
1074 Register SrcSubLo
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_lo
);
1075 copyPhysReg(MBB
, MI
, DL
, DstReg
, SrcSubLo
, MI
.getOperand(1).isKill());
1077 MRI
.clearKillFlags(SrcSubLo
);
1080 case Hexagon::V6_hi
: {
1081 Register SrcReg
= MI
.getOperand(1).getReg();
1082 Register DstReg
= MI
.getOperand(0).getReg();
1083 Register SrcSubHi
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_hi
);
1084 copyPhysReg(MBB
, MI
, DL
, DstReg
, SrcSubHi
, MI
.getOperand(1).isKill());
1086 MRI
.clearKillFlags(SrcSubHi
);
1089 case Hexagon::PS_vstorerw_ai
:
1090 case Hexagon::PS_vstorerwu_ai
: {
1091 bool Aligned
= Opc
== Hexagon::PS_vstorerw_ai
;
1092 Register SrcReg
= MI
.getOperand(2).getReg();
1093 Register SrcSubHi
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_hi
);
1094 Register SrcSubLo
= HRI
.getSubReg(SrcReg
, Hexagon::vsub_lo
);
1095 unsigned NewOpc
= Aligned
? Hexagon::V6_vS32b_ai
: Hexagon::V6_vS32Ub_ai
;
1096 unsigned Offset
= HRI
.getSpillSize(Hexagon::HvxVRRegClass
);
1098 MachineInstr
*MI1New
= BuildMI(MBB
, MI
, DL
, get(NewOpc
))
1099 .add(MI
.getOperand(0))
1100 .addImm(MI
.getOperand(1).getImm())
1103 MI1New
->getOperand(0).setIsKill(false);
1104 BuildMI(MBB
, MI
, DL
, get(NewOpc
))
1105 .add(MI
.getOperand(0))
1106 // The Vectors are indexed in multiples of vector size.
1107 .addImm(MI
.getOperand(1).getImm() + Offset
)
1113 case Hexagon::PS_vloadrw_ai
:
1114 case Hexagon::PS_vloadrwu_ai
: {
1115 bool Aligned
= Opc
== Hexagon::PS_vloadrw_ai
;
1116 Register DstReg
= MI
.getOperand(0).getReg();
1117 unsigned NewOpc
= Aligned
? Hexagon::V6_vL32b_ai
: Hexagon::V6_vL32Ub_ai
;
1118 unsigned Offset
= HRI
.getSpillSize(Hexagon::HvxVRRegClass
);
1120 MachineInstr
*MI1New
= BuildMI(MBB
, MI
, DL
, get(NewOpc
),
1121 HRI
.getSubReg(DstReg
, Hexagon::vsub_lo
))
1122 .add(MI
.getOperand(1))
1123 .addImm(MI
.getOperand(2).getImm())
1125 MI1New
->getOperand(1).setIsKill(false);
1126 BuildMI(MBB
, MI
, DL
, get(NewOpc
), HRI
.getSubReg(DstReg
, Hexagon::vsub_hi
))
1127 .add(MI
.getOperand(1))
1128 // The Vectors are indexed in multiples of vector size.
1129 .addImm(MI
.getOperand(2).getImm() + Offset
)
1134 case Hexagon::PS_true
: {
1135 Register Reg
= MI
.getOperand(0).getReg();
1136 BuildMI(MBB
, MI
, DL
, get(Hexagon::C2_orn
), Reg
)
1137 .addReg(Reg
, RegState::Undef
)
1138 .addReg(Reg
, RegState::Undef
);
1142 case Hexagon::PS_false
: {
1143 Register Reg
= MI
.getOperand(0).getReg();
1144 BuildMI(MBB
, MI
, DL
, get(Hexagon::C2_andn
), Reg
)
1145 .addReg(Reg
, RegState::Undef
)
1146 .addReg(Reg
, RegState::Undef
);
1150 case Hexagon::PS_qtrue
: {
1151 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_veqw
), MI
.getOperand(0).getReg())
1152 .addReg(Hexagon::V0
, RegState::Undef
)
1153 .addReg(Hexagon::V0
, RegState::Undef
);
1157 case Hexagon::PS_qfalse
: {
1158 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgtw
), MI
.getOperand(0).getReg())
1159 .addReg(Hexagon::V0
, RegState::Undef
)
1160 .addReg(Hexagon::V0
, RegState::Undef
);
1164 case Hexagon::PS_vdd0
: {
1165 Register Vd
= MI
.getOperand(0).getReg();
1166 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vsubw_dv
), Vd
)
1167 .addReg(Vd
, RegState::Undef
)
1168 .addReg(Vd
, RegState::Undef
);
1172 case Hexagon::PS_vmulw
: {
1173 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1174 Register DstReg
= MI
.getOperand(0).getReg();
1175 Register Src1Reg
= MI
.getOperand(1).getReg();
1176 Register Src2Reg
= MI
.getOperand(2).getReg();
1177 Register Src1SubHi
= HRI
.getSubReg(Src1Reg
, Hexagon::isub_hi
);
1178 Register Src1SubLo
= HRI
.getSubReg(Src1Reg
, Hexagon::isub_lo
);
1179 Register Src2SubHi
= HRI
.getSubReg(Src2Reg
, Hexagon::isub_hi
);
1180 Register Src2SubLo
= HRI
.getSubReg(Src2Reg
, Hexagon::isub_lo
);
1181 BuildMI(MBB
, MI
, MI
.getDebugLoc(), get(Hexagon::M2_mpyi
),
1182 HRI
.getSubReg(DstReg
, Hexagon::isub_hi
))
1185 BuildMI(MBB
, MI
, MI
.getDebugLoc(), get(Hexagon::M2_mpyi
),
1186 HRI
.getSubReg(DstReg
, Hexagon::isub_lo
))
1190 MRI
.clearKillFlags(Src1SubHi
);
1191 MRI
.clearKillFlags(Src1SubLo
);
1192 MRI
.clearKillFlags(Src2SubHi
);
1193 MRI
.clearKillFlags(Src2SubLo
);
1196 case Hexagon::PS_vmulw_acc
: {
1197 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1198 Register DstReg
= MI
.getOperand(0).getReg();
1199 Register Src1Reg
= MI
.getOperand(1).getReg();
1200 Register Src2Reg
= MI
.getOperand(2).getReg();
1201 Register Src3Reg
= MI
.getOperand(3).getReg();
1202 Register Src1SubHi
= HRI
.getSubReg(Src1Reg
, Hexagon::isub_hi
);
1203 Register Src1SubLo
= HRI
.getSubReg(Src1Reg
, Hexagon::isub_lo
);
1204 Register Src2SubHi
= HRI
.getSubReg(Src2Reg
, Hexagon::isub_hi
);
1205 Register Src2SubLo
= HRI
.getSubReg(Src2Reg
, Hexagon::isub_lo
);
1206 Register Src3SubHi
= HRI
.getSubReg(Src3Reg
, Hexagon::isub_hi
);
1207 Register Src3SubLo
= HRI
.getSubReg(Src3Reg
, Hexagon::isub_lo
);
1208 BuildMI(MBB
, MI
, MI
.getDebugLoc(), get(Hexagon::M2_maci
),
1209 HRI
.getSubReg(DstReg
, Hexagon::isub_hi
))
1213 BuildMI(MBB
, MI
, MI
.getDebugLoc(), get(Hexagon::M2_maci
),
1214 HRI
.getSubReg(DstReg
, Hexagon::isub_lo
))
1219 MRI
.clearKillFlags(Src1SubHi
);
1220 MRI
.clearKillFlags(Src1SubLo
);
1221 MRI
.clearKillFlags(Src2SubHi
);
1222 MRI
.clearKillFlags(Src2SubLo
);
1223 MRI
.clearKillFlags(Src3SubHi
);
1224 MRI
.clearKillFlags(Src3SubLo
);
1227 case Hexagon::PS_pselect
: {
1228 const MachineOperand
&Op0
= MI
.getOperand(0);
1229 const MachineOperand
&Op1
= MI
.getOperand(1);
1230 const MachineOperand
&Op2
= MI
.getOperand(2);
1231 const MachineOperand
&Op3
= MI
.getOperand(3);
1232 Register Rd
= Op0
.getReg();
1233 Register Pu
= Op1
.getReg();
1234 Register Rs
= Op2
.getReg();
1235 Register Rt
= Op3
.getReg();
1236 DebugLoc DL
= MI
.getDebugLoc();
1237 unsigned K1
= getKillRegState(Op1
.isKill());
1238 unsigned K2
= getKillRegState(Op2
.isKill());
1239 unsigned K3
= getKillRegState(Op3
.isKill());
1241 BuildMI(MBB
, MI
, DL
, get(Hexagon::A2_tfrpt
), Rd
)
1242 .addReg(Pu
, (Rd
== Rt
) ? K1
: 0)
1245 BuildMI(MBB
, MI
, DL
, get(Hexagon::A2_tfrpf
), Rd
)
1251 case Hexagon::PS_vselect
: {
1252 const MachineOperand
&Op0
= MI
.getOperand(0);
1253 const MachineOperand
&Op1
= MI
.getOperand(1);
1254 const MachineOperand
&Op2
= MI
.getOperand(2);
1255 const MachineOperand
&Op3
= MI
.getOperand(3);
1256 LivePhysRegs
LiveAtMI(HRI
);
1257 getLiveRegsAt(LiveAtMI
, MI
);
1258 bool IsDestLive
= !LiveAtMI
.available(MRI
, Op0
.getReg());
1259 Register PReg
= Op1
.getReg();
1260 assert(Op1
.getSubReg() == 0);
1261 unsigned PState
= getRegState(Op1
);
1263 if (Op0
.getReg() != Op2
.getReg()) {
1264 unsigned S
= Op0
.getReg() != Op3
.getReg() ? PState
& ~RegState::Kill
1266 auto T
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vcmov
))
1271 T
.addReg(Op0
.getReg(), RegState::Implicit
);
1274 if (Op0
.getReg() != Op3
.getReg()) {
1275 auto T
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vncmov
))
1277 .addReg(PReg
, PState
)
1280 T
.addReg(Op0
.getReg(), RegState::Implicit
);
1285 case Hexagon::PS_wselect
: {
1286 MachineOperand
&Op0
= MI
.getOperand(0);
1287 MachineOperand
&Op1
= MI
.getOperand(1);
1288 MachineOperand
&Op2
= MI
.getOperand(2);
1289 MachineOperand
&Op3
= MI
.getOperand(3);
1290 LivePhysRegs
LiveAtMI(HRI
);
1291 getLiveRegsAt(LiveAtMI
, MI
);
1292 bool IsDestLive
= !LiveAtMI
.available(MRI
, Op0
.getReg());
1293 Register PReg
= Op1
.getReg();
1294 assert(Op1
.getSubReg() == 0);
1295 unsigned PState
= getRegState(Op1
);
1297 if (Op0
.getReg() != Op2
.getReg()) {
1298 unsigned S
= Op0
.getReg() != Op3
.getReg() ? PState
& ~RegState::Kill
1300 Register SrcLo
= HRI
.getSubReg(Op2
.getReg(), Hexagon::vsub_lo
);
1301 Register SrcHi
= HRI
.getSubReg(Op2
.getReg(), Hexagon::vsub_hi
);
1302 auto T
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vccombine
))
1308 T
.addReg(Op0
.getReg(), RegState::Implicit
);
1311 if (Op0
.getReg() != Op3
.getReg()) {
1312 Register SrcLo
= HRI
.getSubReg(Op3
.getReg(), Hexagon::vsub_lo
);
1313 Register SrcHi
= HRI
.getSubReg(Op3
.getReg(), Hexagon::vsub_hi
);
1314 auto T
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vnccombine
))
1316 .addReg(PReg
, PState
)
1320 T
.addReg(Op0
.getReg(), RegState::Implicit
);
1326 case Hexagon::PS_crash
: {
1327 // Generate a misaligned load that is guaranteed to cause a crash.
1328 class CrashPseudoSourceValue
: public PseudoSourceValue
{
1330 CrashPseudoSourceValue(const TargetInstrInfo
&TII
)
1331 : PseudoSourceValue(TargetCustom
, TII
) {}
1333 bool isConstant(const MachineFrameInfo
*) const override
{
1336 bool isAliased(const MachineFrameInfo
*) const override
{
1339 bool mayAlias(const MachineFrameInfo
*) const override
{
1342 void printCustom(raw_ostream
&OS
) const override
{
1343 OS
<< "MisalignedCrash";
1347 static const CrashPseudoSourceValue
CrashPSV(*this);
1348 MachineMemOperand
*MMO
= MF
.getMachineMemOperand(
1349 MachinePointerInfo(&CrashPSV
),
1350 MachineMemOperand::MOLoad
| MachineMemOperand::MOVolatile
, 8, 1);
1351 BuildMI(MBB
, MI
, DL
, get(Hexagon::PS_loadrdabs
), Hexagon::D13
)
1352 .addImm(0xBADC0FEE) // Misaligned load.
1353 .addMemOperand(MMO
);
1358 case Hexagon::PS_tailcall_i
:
1359 MI
.setDesc(get(Hexagon::J2_jump
));
1361 case Hexagon::PS_tailcall_r
:
1362 case Hexagon::PS_jmpret
:
1363 MI
.setDesc(get(Hexagon::J2_jumpr
));
1365 case Hexagon::PS_jmprett
:
1366 MI
.setDesc(get(Hexagon::J2_jumprt
));
1368 case Hexagon::PS_jmpretf
:
1369 MI
.setDesc(get(Hexagon::J2_jumprf
));
1371 case Hexagon::PS_jmprettnewpt
:
1372 MI
.setDesc(get(Hexagon::J2_jumprtnewpt
));
1374 case Hexagon::PS_jmpretfnewpt
:
1375 MI
.setDesc(get(Hexagon::J2_jumprfnewpt
));
1377 case Hexagon::PS_jmprettnew
:
1378 MI
.setDesc(get(Hexagon::J2_jumprtnew
));
1380 case Hexagon::PS_jmpretfnew
:
1381 MI
.setDesc(get(Hexagon::J2_jumprfnew
));
1384 case Hexagon::PS_loadrub_pci
:
1385 return RealCirc(Hexagon::L2_loadrub_pci
, /*HasImm*/true, /*MxOp*/4);
1386 case Hexagon::PS_loadrb_pci
:
1387 return RealCirc(Hexagon::L2_loadrb_pci
, /*HasImm*/true, /*MxOp*/4);
1388 case Hexagon::PS_loadruh_pci
:
1389 return RealCirc(Hexagon::L2_loadruh_pci
, /*HasImm*/true, /*MxOp*/4);
1390 case Hexagon::PS_loadrh_pci
:
1391 return RealCirc(Hexagon::L2_loadrh_pci
, /*HasImm*/true, /*MxOp*/4);
1392 case Hexagon::PS_loadri_pci
:
1393 return RealCirc(Hexagon::L2_loadri_pci
, /*HasImm*/true, /*MxOp*/4);
1394 case Hexagon::PS_loadrd_pci
:
1395 return RealCirc(Hexagon::L2_loadrd_pci
, /*HasImm*/true, /*MxOp*/4);
1396 case Hexagon::PS_loadrub_pcr
:
1397 return RealCirc(Hexagon::L2_loadrub_pcr
, /*HasImm*/false, /*MxOp*/3);
1398 case Hexagon::PS_loadrb_pcr
:
1399 return RealCirc(Hexagon::L2_loadrb_pcr
, /*HasImm*/false, /*MxOp*/3);
1400 case Hexagon::PS_loadruh_pcr
:
1401 return RealCirc(Hexagon::L2_loadruh_pcr
, /*HasImm*/false, /*MxOp*/3);
1402 case Hexagon::PS_loadrh_pcr
:
1403 return RealCirc(Hexagon::L2_loadrh_pcr
, /*HasImm*/false, /*MxOp*/3);
1404 case Hexagon::PS_loadri_pcr
:
1405 return RealCirc(Hexagon::L2_loadri_pcr
, /*HasImm*/false, /*MxOp*/3);
1406 case Hexagon::PS_loadrd_pcr
:
1407 return RealCirc(Hexagon::L2_loadrd_pcr
, /*HasImm*/false, /*MxOp*/3);
1408 case Hexagon::PS_storerb_pci
:
1409 return RealCirc(Hexagon::S2_storerb_pci
, /*HasImm*/true, /*MxOp*/3);
1410 case Hexagon::PS_storerh_pci
:
1411 return RealCirc(Hexagon::S2_storerh_pci
, /*HasImm*/true, /*MxOp*/3);
1412 case Hexagon::PS_storerf_pci
:
1413 return RealCirc(Hexagon::S2_storerf_pci
, /*HasImm*/true, /*MxOp*/3);
1414 case Hexagon::PS_storeri_pci
:
1415 return RealCirc(Hexagon::S2_storeri_pci
, /*HasImm*/true, /*MxOp*/3);
1416 case Hexagon::PS_storerd_pci
:
1417 return RealCirc(Hexagon::S2_storerd_pci
, /*HasImm*/true, /*MxOp*/3);
1418 case Hexagon::PS_storerb_pcr
:
1419 return RealCirc(Hexagon::S2_storerb_pcr
, /*HasImm*/false, /*MxOp*/2);
1420 case Hexagon::PS_storerh_pcr
:
1421 return RealCirc(Hexagon::S2_storerh_pcr
, /*HasImm*/false, /*MxOp*/2);
1422 case Hexagon::PS_storerf_pcr
:
1423 return RealCirc(Hexagon::S2_storerf_pcr
, /*HasImm*/false, /*MxOp*/2);
1424 case Hexagon::PS_storeri_pcr
:
1425 return RealCirc(Hexagon::S2_storeri_pcr
, /*HasImm*/false, /*MxOp*/2);
1426 case Hexagon::PS_storerd_pcr
:
1427 return RealCirc(Hexagon::S2_storerd_pcr
, /*HasImm*/false, /*MxOp*/2);
1433 MachineBasicBlock::instr_iterator
1434 HexagonInstrInfo::expandVGatherPseudo(MachineInstr
&MI
) const {
1435 MachineBasicBlock
&MBB
= *MI
.getParent();
1436 const DebugLoc
&DL
= MI
.getDebugLoc();
1437 unsigned Opc
= MI
.getOpcode();
1438 MachineBasicBlock::iterator First
;
1441 case Hexagon::V6_vgathermh_pseudo
:
1442 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermh
))
1443 .add(MI
.getOperand(1))
1444 .add(MI
.getOperand(2))
1445 .add(MI
.getOperand(3));
1446 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1447 .add(MI
.getOperand(0))
1449 .addReg(Hexagon::VTMP
);
1451 return First
.getInstrIterator();
1453 case Hexagon::V6_vgathermw_pseudo
:
1454 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermw
))
1455 .add(MI
.getOperand(1))
1456 .add(MI
.getOperand(2))
1457 .add(MI
.getOperand(3));
1458 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1459 .add(MI
.getOperand(0))
1461 .addReg(Hexagon::VTMP
);
1463 return First
.getInstrIterator();
1465 case Hexagon::V6_vgathermhw_pseudo
:
1466 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermhw
))
1467 .add(MI
.getOperand(1))
1468 .add(MI
.getOperand(2))
1469 .add(MI
.getOperand(3));
1470 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1471 .add(MI
.getOperand(0))
1473 .addReg(Hexagon::VTMP
);
1475 return First
.getInstrIterator();
1477 case Hexagon::V6_vgathermhq_pseudo
:
1478 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermhq
))
1479 .add(MI
.getOperand(1))
1480 .add(MI
.getOperand(2))
1481 .add(MI
.getOperand(3))
1482 .add(MI
.getOperand(4));
1483 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1484 .add(MI
.getOperand(0))
1486 .addReg(Hexagon::VTMP
);
1488 return First
.getInstrIterator();
1490 case Hexagon::V6_vgathermwq_pseudo
:
1491 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermwq
))
1492 .add(MI
.getOperand(1))
1493 .add(MI
.getOperand(2))
1494 .add(MI
.getOperand(3))
1495 .add(MI
.getOperand(4));
1496 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1497 .add(MI
.getOperand(0))
1499 .addReg(Hexagon::VTMP
);
1501 return First
.getInstrIterator();
1503 case Hexagon::V6_vgathermhwq_pseudo
:
1504 First
= BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vgathermhwq
))
1505 .add(MI
.getOperand(1))
1506 .add(MI
.getOperand(2))
1507 .add(MI
.getOperand(3))
1508 .add(MI
.getOperand(4));
1509 BuildMI(MBB
, MI
, DL
, get(Hexagon::V6_vS32b_new_ai
))
1510 .add(MI
.getOperand(0))
1512 .addReg(Hexagon::VTMP
);
1514 return First
.getInstrIterator();
1517 return MI
.getIterator();
1520 // We indicate that we want to reverse the branch by
1521 // inserting the reversed branching opcode.
1522 bool HexagonInstrInfo::reverseBranchCondition(
1523 SmallVectorImpl
<MachineOperand
> &Cond
) const {
1526 assert(Cond
[0].isImm() && "First entry in the cond vector not imm-val");
1527 unsigned opcode
= Cond
[0].getImm();
1529 assert(get(opcode
).isBranch() && "Should be a branching condition.");
1530 if (isEndLoopN(opcode
))
1532 unsigned NewOpcode
= getInvertedPredicatedOpcode(opcode
);
1533 Cond
[0].setImm(NewOpcode
);
1537 void HexagonInstrInfo::insertNoop(MachineBasicBlock
&MBB
,
1538 MachineBasicBlock::iterator MI
) const {
1540 BuildMI(MBB
, MI
, DL
, get(Hexagon::A2_nop
));
1543 bool HexagonInstrInfo::isPostIncrement(const MachineInstr
&MI
) const {
1544 return getAddrMode(MI
) == HexagonII::PostInc
;
1547 // Returns true if an instruction is predicated irrespective of the predicate
1548 // sense. For example, all of the following will return true.
1549 // if (p0) R1 = add(R2, R3)
1550 // if (!p0) R1 = add(R2, R3)
1551 // if (p0.new) R1 = add(R2, R3)
1552 // if (!p0.new) R1 = add(R2, R3)
1553 // Note: New-value stores are not included here as in the current
1554 // implementation, we don't need to check their predicate sense.
1555 bool HexagonInstrInfo::isPredicated(const MachineInstr
&MI
) const {
1556 const uint64_t F
= MI
.getDesc().TSFlags
;
1557 return (F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
;
1560 bool HexagonInstrInfo::PredicateInstruction(
1561 MachineInstr
&MI
, ArrayRef
<MachineOperand
> Cond
) const {
1562 if (Cond
.empty() || isNewValueJump(Cond
[0].getImm()) ||
1563 isEndLoopN(Cond
[0].getImm())) {
1564 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI
.dump(););
1567 int Opc
= MI
.getOpcode();
1568 assert (isPredicable(MI
) && "Expected predicable instruction");
1569 bool invertJump
= predOpcodeHasNot(Cond
);
1571 // We have to predicate MI "in place", i.e. after this function returns,
1572 // MI will need to be transformed into a predicated form. To avoid com-
1573 // plicated manipulations with the operands (handling tied operands,
1574 // etc.), build a new temporary instruction, then overwrite MI with it.
1576 MachineBasicBlock
&B
= *MI
.getParent();
1577 DebugLoc DL
= MI
.getDebugLoc();
1578 unsigned PredOpc
= getCondOpcode(Opc
, invertJump
);
1579 MachineInstrBuilder T
= BuildMI(B
, MI
, DL
, get(PredOpc
));
1580 unsigned NOp
= 0, NumOps
= MI
.getNumOperands();
1581 while (NOp
< NumOps
) {
1582 MachineOperand
&Op
= MI
.getOperand(NOp
);
1583 if (!Op
.isReg() || !Op
.isDef() || Op
.isImplicit())
1589 unsigned PredReg
, PredRegPos
, PredRegFlags
;
1590 bool GotPredReg
= getPredReg(Cond
, PredReg
, PredRegPos
, PredRegFlags
);
1593 T
.addReg(PredReg
, PredRegFlags
);
1594 while (NOp
< NumOps
)
1595 T
.add(MI
.getOperand(NOp
++));
1597 MI
.setDesc(get(PredOpc
));
1598 while (unsigned n
= MI
.getNumOperands())
1599 MI
.RemoveOperand(n
-1);
1600 for (unsigned i
= 0, n
= T
->getNumOperands(); i
< n
; ++i
)
1601 MI
.addOperand(T
->getOperand(i
));
1603 MachineBasicBlock::instr_iterator TI
= T
->getIterator();
1606 MachineRegisterInfo
&MRI
= B
.getParent()->getRegInfo();
1607 MRI
.clearKillFlags(PredReg
);
1611 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef
<MachineOperand
> Pred1
,
1612 ArrayRef
<MachineOperand
> Pred2
) const {
1617 bool HexagonInstrInfo::DefinesPredicate(MachineInstr
&MI
,
1618 std::vector
<MachineOperand
> &Pred
) const {
1619 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
1621 for (unsigned oper
= 0; oper
< MI
.getNumOperands(); ++oper
) {
1622 MachineOperand MO
= MI
.getOperand(oper
);
1626 const TargetRegisterClass
* RC
= HRI
.getMinimalPhysRegClass(MO
.getReg());
1627 if (RC
== &Hexagon::PredRegsRegClass
) {
1632 } else if (MO
.isRegMask()) {
1633 for (unsigned PR
: Hexagon::PredRegsRegClass
) {
1634 if (!MI
.modifiesRegister(PR
, &HRI
))
1644 bool HexagonInstrInfo::isPredicable(const MachineInstr
&MI
) const {
1645 if (!MI
.getDesc().isPredicable())
1648 if (MI
.isCall() || isTailCall(MI
)) {
1649 if (!Subtarget
.usePredicatedCalls())
1653 // HVX loads are not predicable on v60, but are on v62.
1654 if (!Subtarget
.hasV62Ops()) {
1655 switch (MI
.getOpcode()) {
1656 case Hexagon::V6_vL32b_ai
:
1657 case Hexagon::V6_vL32b_pi
:
1658 case Hexagon::V6_vL32b_ppu
:
1659 case Hexagon::V6_vL32b_cur_ai
:
1660 case Hexagon::V6_vL32b_cur_pi
:
1661 case Hexagon::V6_vL32b_cur_ppu
:
1662 case Hexagon::V6_vL32b_nt_ai
:
1663 case Hexagon::V6_vL32b_nt_pi
:
1664 case Hexagon::V6_vL32b_nt_ppu
:
1665 case Hexagon::V6_vL32b_tmp_ai
:
1666 case Hexagon::V6_vL32b_tmp_pi
:
1667 case Hexagon::V6_vL32b_tmp_ppu
:
1668 case Hexagon::V6_vL32b_nt_cur_ai
:
1669 case Hexagon::V6_vL32b_nt_cur_pi
:
1670 case Hexagon::V6_vL32b_nt_cur_ppu
:
1671 case Hexagon::V6_vL32b_nt_tmp_ai
:
1672 case Hexagon::V6_vL32b_nt_tmp_pi
:
1673 case Hexagon::V6_vL32b_nt_tmp_ppu
:
1680 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr
&MI
,
1681 const MachineBasicBlock
*MBB
,
1682 const MachineFunction
&MF
) const {
1683 // Debug info is never a scheduling boundary. It's necessary to be explicit
1684 // due to the special treatment of IT instructions below, otherwise a
1685 // dbg_value followed by an IT will result in the IT instruction being
1686 // considered a scheduling hazard, which is wrong. It should be the actual
1687 // instruction preceding the dbg_value instruction(s), just like it is
1688 // when debug info is not present.
1689 if (MI
.isDebugInstr())
1692 // Throwing call is a boundary.
1694 // Don't mess around with no return calls.
1695 if (doesNotReturn(MI
))
1697 // If any of the block's successors is a landing pad, this could be a
1699 for (auto I
: MBB
->successors())
1704 // Terminators and labels can't be scheduled around.
1705 if (MI
.getDesc().isTerminator() || MI
.isPosition())
1708 if (MI
.isInlineAsm() && !ScheduleInlineAsm
)
1714 /// Measure the specified inline asm to determine an approximation of its
1716 /// Comments (which run till the next SeparatorString or newline) do not
1717 /// count as an instruction.
1718 /// Any other non-whitespace text is considered an instruction, with
1719 /// multiple instructions separated by SeparatorString or newlines.
1720 /// Variable-length instructions are not handled here; this function
1721 /// may be overloaded in the target code to do that.
1722 /// Hexagon counts the number of ##'s and adjust for that many
1723 /// constant exenders.
1724 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str
,
1725 const MCAsmInfo
&MAI
,
1726 const TargetSubtargetInfo
*STI
) const {
1727 StringRef
AStr(Str
);
1728 // Count the number of instructions in the asm.
1729 bool atInsnStart
= true;
1730 unsigned Length
= 0;
1731 const unsigned MaxInstLength
= MAI
.getMaxInstLength(STI
);
1732 for (; *Str
; ++Str
) {
1733 if (*Str
== '\n' || strncmp(Str
, MAI
.getSeparatorString(),
1734 strlen(MAI
.getSeparatorString())) == 0)
1736 if (atInsnStart
&& !std::isspace(static_cast<unsigned char>(*Str
))) {
1737 Length
+= MaxInstLength
;
1738 atInsnStart
= false;
1740 if (atInsnStart
&& strncmp(Str
, MAI
.getCommentString().data(),
1741 MAI
.getCommentString().size()) == 0)
1742 atInsnStart
= false;
1745 // Add to size number of constant extenders seen * 4.
1746 StringRef
Occ("##");
1747 Length
+= AStr
.count(Occ
)*4;
1751 ScheduleHazardRecognizer
*
1752 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1753 const InstrItineraryData
*II
, const ScheduleDAG
*DAG
) const {
1754 if (UseDFAHazardRec
)
1755 return new HexagonHazardRecognizer(II
, this, Subtarget
);
1756 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II
, DAG
);
1759 /// For a comparison instruction, return the source registers in
1760 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1761 /// compares against in CmpValue. Return true if the comparison instruction
1762 /// can be analyzed.
1763 bool HexagonInstrInfo::analyzeCompare(const MachineInstr
&MI
, unsigned &SrcReg
,
1764 unsigned &SrcReg2
, int &Mask
,
1766 unsigned Opc
= MI
.getOpcode();
1768 // Set mask and the first source register.
1770 case Hexagon::C2_cmpeq
:
1771 case Hexagon::C2_cmpeqp
:
1772 case Hexagon::C2_cmpgt
:
1773 case Hexagon::C2_cmpgtp
:
1774 case Hexagon::C2_cmpgtu
:
1775 case Hexagon::C2_cmpgtup
:
1776 case Hexagon::C4_cmpneq
:
1777 case Hexagon::C4_cmplte
:
1778 case Hexagon::C4_cmplteu
:
1779 case Hexagon::C2_cmpeqi
:
1780 case Hexagon::C2_cmpgti
:
1781 case Hexagon::C2_cmpgtui
:
1782 case Hexagon::C4_cmpneqi
:
1783 case Hexagon::C4_cmplteui
:
1784 case Hexagon::C4_cmpltei
:
1785 SrcReg
= MI
.getOperand(1).getReg();
1788 case Hexagon::A4_cmpbeq
:
1789 case Hexagon::A4_cmpbgt
:
1790 case Hexagon::A4_cmpbgtu
:
1791 case Hexagon::A4_cmpbeqi
:
1792 case Hexagon::A4_cmpbgti
:
1793 case Hexagon::A4_cmpbgtui
:
1794 SrcReg
= MI
.getOperand(1).getReg();
1797 case Hexagon::A4_cmpheq
:
1798 case Hexagon::A4_cmphgt
:
1799 case Hexagon::A4_cmphgtu
:
1800 case Hexagon::A4_cmpheqi
:
1801 case Hexagon::A4_cmphgti
:
1802 case Hexagon::A4_cmphgtui
:
1803 SrcReg
= MI
.getOperand(1).getReg();
1808 // Set the value/second source register.
1810 case Hexagon::C2_cmpeq
:
1811 case Hexagon::C2_cmpeqp
:
1812 case Hexagon::C2_cmpgt
:
1813 case Hexagon::C2_cmpgtp
:
1814 case Hexagon::C2_cmpgtu
:
1815 case Hexagon::C2_cmpgtup
:
1816 case Hexagon::A4_cmpbeq
:
1817 case Hexagon::A4_cmpbgt
:
1818 case Hexagon::A4_cmpbgtu
:
1819 case Hexagon::A4_cmpheq
:
1820 case Hexagon::A4_cmphgt
:
1821 case Hexagon::A4_cmphgtu
:
1822 case Hexagon::C4_cmpneq
:
1823 case Hexagon::C4_cmplte
:
1824 case Hexagon::C4_cmplteu
:
1825 SrcReg2
= MI
.getOperand(2).getReg();
1828 case Hexagon::C2_cmpeqi
:
1829 case Hexagon::C2_cmpgtui
:
1830 case Hexagon::C2_cmpgti
:
1831 case Hexagon::C4_cmpneqi
:
1832 case Hexagon::C4_cmplteui
:
1833 case Hexagon::C4_cmpltei
:
1834 case Hexagon::A4_cmpbeqi
:
1835 case Hexagon::A4_cmpbgti
:
1836 case Hexagon::A4_cmpbgtui
:
1837 case Hexagon::A4_cmpheqi
:
1838 case Hexagon::A4_cmphgti
:
1839 case Hexagon::A4_cmphgtui
: {
1841 const MachineOperand
&Op2
= MI
.getOperand(2);
1844 Value
= MI
.getOperand(2).getImm();
1852 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData
*ItinData
,
1853 const MachineInstr
&MI
,
1854 unsigned *PredCost
) const {
1855 return getInstrTimingClassLatency(ItinData
, MI
);
1858 DFAPacketizer
*HexagonInstrInfo::CreateTargetScheduleState(
1859 const TargetSubtargetInfo
&STI
) const {
1860 const InstrItineraryData
*II
= STI
.getInstrItineraryData();
1861 return static_cast<const HexagonSubtarget
&>(STI
).createDFAPacketizer(II
);
1864 // Inspired by this pair:
1865 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1866 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1867 // Currently AA considers the addresses in these instructions to be aliasing.
1868 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1869 const MachineInstr
&MIa
, const MachineInstr
&MIb
,
1870 AliasAnalysis
*AA
) const {
1871 if (MIa
.hasUnmodeledSideEffects() || MIb
.hasUnmodeledSideEffects() ||
1872 MIa
.hasOrderedMemoryRef() || MIb
.hasOrderedMemoryRef())
1875 // Instructions that are pure loads, not loads and stores like memops are not
1877 if (MIa
.mayLoad() && !isMemOp(MIa
) && MIb
.mayLoad() && !isMemOp(MIb
))
1880 // Get the base register in MIa.
1881 unsigned BasePosA
, OffsetPosA
;
1882 if (!getBaseAndOffsetPosition(MIa
, BasePosA
, OffsetPosA
))
1884 const MachineOperand
&BaseA
= MIa
.getOperand(BasePosA
);
1885 Register BaseRegA
= BaseA
.getReg();
1886 unsigned BaseSubA
= BaseA
.getSubReg();
1888 // Get the base register in MIb.
1889 unsigned BasePosB
, OffsetPosB
;
1890 if (!getBaseAndOffsetPosition(MIb
, BasePosB
, OffsetPosB
))
1892 const MachineOperand
&BaseB
= MIb
.getOperand(BasePosB
);
1893 Register BaseRegB
= BaseB
.getReg();
1894 unsigned BaseSubB
= BaseB
.getSubReg();
1896 if (BaseRegA
!= BaseRegB
|| BaseSubA
!= BaseSubB
)
1899 // Get the access sizes.
1900 unsigned SizeA
= getMemAccessSize(MIa
);
1901 unsigned SizeB
= getMemAccessSize(MIb
);
1903 // Get the offsets. Handle immediates only for now.
1904 const MachineOperand
&OffA
= MIa
.getOperand(OffsetPosA
);
1905 const MachineOperand
&OffB
= MIb
.getOperand(OffsetPosB
);
1906 if (!MIa
.getOperand(OffsetPosA
).isImm() ||
1907 !MIb
.getOperand(OffsetPosB
).isImm())
1909 int OffsetA
= isPostIncrement(MIa
) ? 0 : OffA
.getImm();
1910 int OffsetB
= isPostIncrement(MIb
) ? 0 : OffB
.getImm();
1912 // This is a mem access with the same base register and known offsets from it.
1914 if (OffsetA
> OffsetB
) {
1915 uint64_t OffDiff
= (uint64_t)((int64_t)OffsetA
- (int64_t)OffsetB
);
1916 return SizeB
<= OffDiff
;
1918 if (OffsetA
< OffsetB
) {
1919 uint64_t OffDiff
= (uint64_t)((int64_t)OffsetB
- (int64_t)OffsetA
);
1920 return SizeA
<= OffDiff
;
1926 /// If the instruction is an increment of a constant value, return the amount.
1927 bool HexagonInstrInfo::getIncrementValue(const MachineInstr
&MI
,
1929 if (isPostIncrement(MI
)) {
1930 unsigned BasePos
= 0, OffsetPos
= 0;
1931 if (!getBaseAndOffsetPosition(MI
, BasePos
, OffsetPos
))
1933 const MachineOperand
&OffsetOp
= MI
.getOperand(OffsetPos
);
1934 if (OffsetOp
.isImm()) {
1935 Value
= OffsetOp
.getImm();
1938 } else if (MI
.getOpcode() == Hexagon::A2_addi
) {
1939 const MachineOperand
&AddOp
= MI
.getOperand(2);
1940 if (AddOp
.isImm()) {
1941 Value
= AddOp
.getImm();
1949 std::pair
<unsigned, unsigned>
1950 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF
) const {
1951 return std::make_pair(TF
& ~HexagonII::MO_Bitmasks
,
1952 TF
& HexagonII::MO_Bitmasks
);
1955 ArrayRef
<std::pair
<unsigned, const char*>>
1956 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1957 using namespace HexagonII
;
1959 static const std::pair
<unsigned, const char*> Flags
[] = {
1960 {MO_PCREL
, "hexagon-pcrel"},
1961 {MO_GOT
, "hexagon-got"},
1962 {MO_LO16
, "hexagon-lo16"},
1963 {MO_HI16
, "hexagon-hi16"},
1964 {MO_GPREL
, "hexagon-gprel"},
1965 {MO_GDGOT
, "hexagon-gdgot"},
1966 {MO_GDPLT
, "hexagon-gdplt"},
1967 {MO_IE
, "hexagon-ie"},
1968 {MO_IEGOT
, "hexagon-iegot"},
1969 {MO_TPREL
, "hexagon-tprel"}
1971 return makeArrayRef(Flags
);
1974 ArrayRef
<std::pair
<unsigned, const char*>>
1975 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1976 using namespace HexagonII
;
1978 static const std::pair
<unsigned, const char*> Flags
[] = {
1979 {HMOTF_ConstExtended
, "hexagon-ext"}
1981 return makeArrayRef(Flags
);
1984 unsigned HexagonInstrInfo::createVR(MachineFunction
*MF
, MVT VT
) const {
1985 MachineRegisterInfo
&MRI
= MF
->getRegInfo();
1986 const TargetRegisterClass
*TRC
;
1987 if (VT
== MVT::i1
) {
1988 TRC
= &Hexagon::PredRegsRegClass
;
1989 } else if (VT
== MVT::i32
|| VT
== MVT::f32
) {
1990 TRC
= &Hexagon::IntRegsRegClass
;
1991 } else if (VT
== MVT::i64
|| VT
== MVT::f64
) {
1992 TRC
= &Hexagon::DoubleRegsRegClass
;
1994 llvm_unreachable("Cannot handle this register class");
1997 Register NewReg
= MRI
.createVirtualRegister(TRC
);
2001 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr
&MI
) const {
2002 return (getAddrMode(MI
) == HexagonII::AbsoluteSet
);
2005 bool HexagonInstrInfo::isAccumulator(const MachineInstr
&MI
) const {
2006 const uint64_t F
= MI
.getDesc().TSFlags
;
2007 return((F
>> HexagonII::AccumulatorPos
) & HexagonII::AccumulatorMask
);
2010 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr
&MI
) const {
2011 return getAddrMode(MI
) == HexagonII::BaseImmOffset
;
2014 bool HexagonInstrInfo::isComplex(const MachineInstr
&MI
) const {
2015 return !isTC1(MI
) && !isTC2Early(MI
) && !MI
.getDesc().mayLoad() &&
2016 !MI
.getDesc().mayStore() &&
2017 MI
.getDesc().getOpcode() != Hexagon::S2_allocframe
&&
2018 MI
.getDesc().getOpcode() != Hexagon::L2_deallocframe
&&
2019 !isMemOp(MI
) && !MI
.isBranch() && !MI
.isReturn() && !MI
.isCall();
2022 // Return true if the instruction is a compund branch instruction.
2023 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr
&MI
) const {
2024 return getType(MI
) == HexagonII::TypeCJ
&& MI
.isBranch();
2027 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2028 // isFPImm and later getFPImm as well.
2029 bool HexagonInstrInfo::isConstExtended(const MachineInstr
&MI
) const {
2030 const uint64_t F
= MI
.getDesc().TSFlags
;
2031 unsigned isExtended
= (F
>> HexagonII::ExtendedPos
) & HexagonII::ExtendedMask
;
2032 if (isExtended
) // Instruction must be extended.
2035 unsigned isExtendable
=
2036 (F
>> HexagonII::ExtendablePos
) & HexagonII::ExtendableMask
;
2043 short ExtOpNum
= getCExtOpNum(MI
);
2044 const MachineOperand
&MO
= MI
.getOperand(ExtOpNum
);
2045 // Use MO operand flags to determine if MO
2046 // has the HMOTF_ConstExtended flag set.
2047 if (MO
.getTargetFlags() & HexagonII::HMOTF_ConstExtended
)
2049 // If this is a Machine BB address we are talking about, and it is
2050 // not marked as extended, say so.
2054 // We could be using an instruction with an extendable immediate and shoehorn
2055 // a global address into it. If it is a global address it will be constant
2056 // extended. We do this for COMBINE.
2057 if (MO
.isGlobal() || MO
.isSymbol() || MO
.isBlockAddress() ||
2058 MO
.isJTI() || MO
.isCPI() || MO
.isFPImm())
2061 // If the extendable operand is not 'Immediate' type, the instruction should
2062 // have 'isExtended' flag set.
2063 assert(MO
.isImm() && "Extendable operand must be Immediate type");
2065 int MinValue
= getMinValue(MI
);
2066 int MaxValue
= getMaxValue(MI
);
2067 int ImmValue
= MO
.getImm();
2069 return (ImmValue
< MinValue
|| ImmValue
> MaxValue
);
2072 bool HexagonInstrInfo::isDeallocRet(const MachineInstr
&MI
) const {
2073 switch (MI
.getOpcode()) {
2074 case Hexagon::L4_return
:
2075 case Hexagon::L4_return_t
:
2076 case Hexagon::L4_return_f
:
2077 case Hexagon::L4_return_tnew_pnt
:
2078 case Hexagon::L4_return_fnew_pnt
:
2079 case Hexagon::L4_return_tnew_pt
:
2080 case Hexagon::L4_return_fnew_pt
:
2086 // Return true when ConsMI uses a register defined by ProdMI.
2087 bool HexagonInstrInfo::isDependent(const MachineInstr
&ProdMI
,
2088 const MachineInstr
&ConsMI
) const {
2089 if (!ProdMI
.getDesc().getNumDefs())
2091 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
2093 SmallVector
<unsigned, 4> DefsA
;
2094 SmallVector
<unsigned, 4> DefsB
;
2095 SmallVector
<unsigned, 8> UsesA
;
2096 SmallVector
<unsigned, 8> UsesB
;
2098 parseOperands(ProdMI
, DefsA
, UsesA
);
2099 parseOperands(ConsMI
, DefsB
, UsesB
);
2101 for (auto &RegA
: DefsA
)
2102 for (auto &RegB
: UsesB
) {
2103 // True data dependency.
2107 if (Register::isPhysicalRegister(RegA
))
2108 for (MCSubRegIterator
SubRegs(RegA
, &HRI
); SubRegs
.isValid(); ++SubRegs
)
2109 if (RegB
== *SubRegs
)
2112 if (Register::isPhysicalRegister(RegB
))
2113 for (MCSubRegIterator
SubRegs(RegB
, &HRI
); SubRegs
.isValid(); ++SubRegs
)
2114 if (RegA
== *SubRegs
)
2121 // Returns true if the instruction is alread a .cur.
2122 bool HexagonInstrInfo::isDotCurInst(const MachineInstr
&MI
) const {
2123 switch (MI
.getOpcode()) {
2124 case Hexagon::V6_vL32b_cur_pi
:
2125 case Hexagon::V6_vL32b_cur_ai
:
2131 // Returns true, if any one of the operands is a dot new
2132 // insn, whether it is predicated dot new or register dot new.
2133 bool HexagonInstrInfo::isDotNewInst(const MachineInstr
&MI
) const {
2134 if (isNewValueInst(MI
) || (isPredicated(MI
) && isPredicatedNew(MI
)))
2140 /// Symmetrical. See if these two instructions are fit for duplex pair.
2141 bool HexagonInstrInfo::isDuplexPair(const MachineInstr
&MIa
,
2142 const MachineInstr
&MIb
) const {
2143 HexagonII::SubInstructionGroup MIaG
= getDuplexCandidateGroup(MIa
);
2144 HexagonII::SubInstructionGroup MIbG
= getDuplexCandidateGroup(MIb
);
2145 return (isDuplexPairMatch(MIaG
, MIbG
) || isDuplexPairMatch(MIbG
, MIaG
));
2148 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr
&MI
) const {
2149 if (MI
.mayLoad() || MI
.mayStore() || MI
.isCompare())
2153 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2154 return is_TC4x(SchedClass
) || is_TC3x(SchedClass
);
2157 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode
) const {
2158 return (Opcode
== Hexagon::ENDLOOP0
||
2159 Opcode
== Hexagon::ENDLOOP1
);
2162 bool HexagonInstrInfo::isExpr(unsigned OpType
) const {
2164 case MachineOperand::MO_MachineBasicBlock
:
2165 case MachineOperand::MO_GlobalAddress
:
2166 case MachineOperand::MO_ExternalSymbol
:
2167 case MachineOperand::MO_JumpTableIndex
:
2168 case MachineOperand::MO_ConstantPoolIndex
:
2169 case MachineOperand::MO_BlockAddress
:
2176 bool HexagonInstrInfo::isExtendable(const MachineInstr
&MI
) const {
2177 const MCInstrDesc
&MID
= MI
.getDesc();
2178 const uint64_t F
= MID
.TSFlags
;
2179 if ((F
>> HexagonII::ExtendablePos
) & HexagonII::ExtendableMask
)
2182 // TODO: This is largely obsolete now. Will need to be removed
2183 // in consecutive patches.
2184 switch (MI
.getOpcode()) {
2185 // PS_fi and PS_fia remain special cases.
2186 case Hexagon::PS_fi
:
2187 case Hexagon::PS_fia
:
2195 // This returns true in two cases:
2196 // - The OP code itself indicates that this is an extended instruction.
2197 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2198 bool HexagonInstrInfo::isExtended(const MachineInstr
&MI
) const {
2199 // First check if this is permanently extended op code.
2200 const uint64_t F
= MI
.getDesc().TSFlags
;
2201 if ((F
>> HexagonII::ExtendedPos
) & HexagonII::ExtendedMask
)
2203 // Use MO operand flags to determine if one of MI's operands
2204 // has HMOTF_ConstExtended flag set.
2205 for (const MachineOperand
&MO
: MI
.operands())
2206 if (MO
.getTargetFlags() & HexagonII::HMOTF_ConstExtended
)
2211 bool HexagonInstrInfo::isFloat(const MachineInstr
&MI
) const {
2212 unsigned Opcode
= MI
.getOpcode();
2213 const uint64_t F
= get(Opcode
).TSFlags
;
2214 return (F
>> HexagonII::FPPos
) & HexagonII::FPMask
;
2217 // No V60 HVX VMEM with A_INDIRECT.
2218 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr
&I
,
2219 const MachineInstr
&J
) const {
2222 if (!I
.mayLoad() && !I
.mayStore())
2224 return J
.isIndirectBranch() || isIndirectCall(J
) || isIndirectL4Return(J
);
2227 bool HexagonInstrInfo::isIndirectCall(const MachineInstr
&MI
) const {
2228 switch (MI
.getOpcode()) {
2229 case Hexagon::J2_callr
:
2230 case Hexagon::J2_callrf
:
2231 case Hexagon::J2_callrt
:
2232 case Hexagon::PS_call_nr
:
2238 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr
&MI
) const {
2239 switch (MI
.getOpcode()) {
2240 case Hexagon::L4_return
:
2241 case Hexagon::L4_return_t
:
2242 case Hexagon::L4_return_f
:
2243 case Hexagon::L4_return_fnew_pnt
:
2244 case Hexagon::L4_return_fnew_pt
:
2245 case Hexagon::L4_return_tnew_pnt
:
2246 case Hexagon::L4_return_tnew_pt
:
2252 bool HexagonInstrInfo::isJumpR(const MachineInstr
&MI
) const {
2253 switch (MI
.getOpcode()) {
2254 case Hexagon::J2_jumpr
:
2255 case Hexagon::J2_jumprt
:
2256 case Hexagon::J2_jumprf
:
2257 case Hexagon::J2_jumprtnewpt
:
2258 case Hexagon::J2_jumprfnewpt
:
2259 case Hexagon::J2_jumprtnew
:
2260 case Hexagon::J2_jumprfnew
:
2266 // Return true if a given MI can accommodate given offset.
2267 // Use abs estimate as oppose to the exact number.
2268 // TODO: This will need to be changed to use MC level
2269 // definition of instruction extendable field size.
2270 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr
&MI
,
2271 unsigned offset
) const {
2272 // This selection of jump instructions matches to that what
2273 // analyzeBranch can parse, plus NVJ.
2274 if (isNewValueJump(MI
)) // r9:2
2275 return isInt
<11>(offset
);
2277 switch (MI
.getOpcode()) {
2278 // Still missing Jump to address condition on register value.
2281 case Hexagon::J2_jump
: // bits<24> dst; // r22:2
2282 case Hexagon::J2_call
:
2283 case Hexagon::PS_call_nr
:
2284 return isInt
<24>(offset
);
2285 case Hexagon::J2_jumpt
: //bits<17> dst; // r15:2
2286 case Hexagon::J2_jumpf
:
2287 case Hexagon::J2_jumptnew
:
2288 case Hexagon::J2_jumptnewpt
:
2289 case Hexagon::J2_jumpfnew
:
2290 case Hexagon::J2_jumpfnewpt
:
2291 case Hexagon::J2_callt
:
2292 case Hexagon::J2_callf
:
2293 return isInt
<17>(offset
);
2294 case Hexagon::J2_loop0i
:
2295 case Hexagon::J2_loop0iext
:
2296 case Hexagon::J2_loop0r
:
2297 case Hexagon::J2_loop0rext
:
2298 case Hexagon::J2_loop1i
:
2299 case Hexagon::J2_loop1iext
:
2300 case Hexagon::J2_loop1r
:
2301 case Hexagon::J2_loop1rext
:
2302 return isInt
<9>(offset
);
2303 // TODO: Add all the compound branches here. Can we do this in Relation model?
2304 case Hexagon::J4_cmpeqi_tp0_jump_nt
:
2305 case Hexagon::J4_cmpeqi_tp1_jump_nt
:
2306 case Hexagon::J4_cmpeqn1_tp0_jump_nt
:
2307 case Hexagon::J4_cmpeqn1_tp1_jump_nt
:
2308 return isInt
<11>(offset
);
2312 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr
&LRMI
,
2313 const MachineInstr
&ESMI
) const {
2314 bool isLate
= isLateResultInstr(LRMI
);
2315 bool isEarly
= isEarlySourceInstr(ESMI
);
2317 LLVM_DEBUG(dbgs() << "V60" << (isLate
? "-LR " : " -- "));
2318 LLVM_DEBUG(LRMI
.dump());
2319 LLVM_DEBUG(dbgs() << "V60" << (isEarly
? "-ES " : " -- "));
2320 LLVM_DEBUG(ESMI
.dump());
2322 if (isLate
&& isEarly
) {
2323 LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2330 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr
&MI
) const {
2331 switch (MI
.getOpcode()) {
2332 case TargetOpcode::EXTRACT_SUBREG
:
2333 case TargetOpcode::INSERT_SUBREG
:
2334 case TargetOpcode::SUBREG_TO_REG
:
2335 case TargetOpcode::REG_SEQUENCE
:
2336 case TargetOpcode::IMPLICIT_DEF
:
2337 case TargetOpcode::COPY
:
2338 case TargetOpcode::INLINEASM
:
2339 case TargetOpcode::PHI
:
2345 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2346 return !is_TC1(SchedClass
);
2349 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr
&MI
) const {
2350 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2351 // resource, but all operands can be received late like an ALU instruction.
2352 return getType(MI
) == HexagonII::TypeCVI_VX_LATE
;
2355 bool HexagonInstrInfo::isLoopN(const MachineInstr
&MI
) const {
2356 unsigned Opcode
= MI
.getOpcode();
2357 return Opcode
== Hexagon::J2_loop0i
||
2358 Opcode
== Hexagon::J2_loop0r
||
2359 Opcode
== Hexagon::J2_loop0iext
||
2360 Opcode
== Hexagon::J2_loop0rext
||
2361 Opcode
== Hexagon::J2_loop1i
||
2362 Opcode
== Hexagon::J2_loop1r
||
2363 Opcode
== Hexagon::J2_loop1iext
||
2364 Opcode
== Hexagon::J2_loop1rext
;
2367 bool HexagonInstrInfo::isMemOp(const MachineInstr
&MI
) const {
2368 switch (MI
.getOpcode()) {
2369 default: return false;
2370 case Hexagon::L4_iadd_memopw_io
:
2371 case Hexagon::L4_isub_memopw_io
:
2372 case Hexagon::L4_add_memopw_io
:
2373 case Hexagon::L4_sub_memopw_io
:
2374 case Hexagon::L4_and_memopw_io
:
2375 case Hexagon::L4_or_memopw_io
:
2376 case Hexagon::L4_iadd_memoph_io
:
2377 case Hexagon::L4_isub_memoph_io
:
2378 case Hexagon::L4_add_memoph_io
:
2379 case Hexagon::L4_sub_memoph_io
:
2380 case Hexagon::L4_and_memoph_io
:
2381 case Hexagon::L4_or_memoph_io
:
2382 case Hexagon::L4_iadd_memopb_io
:
2383 case Hexagon::L4_isub_memopb_io
:
2384 case Hexagon::L4_add_memopb_io
:
2385 case Hexagon::L4_sub_memopb_io
:
2386 case Hexagon::L4_and_memopb_io
:
2387 case Hexagon::L4_or_memopb_io
:
2388 case Hexagon::L4_ior_memopb_io
:
2389 case Hexagon::L4_ior_memoph_io
:
2390 case Hexagon::L4_ior_memopw_io
:
2391 case Hexagon::L4_iand_memopb_io
:
2392 case Hexagon::L4_iand_memoph_io
:
2393 case Hexagon::L4_iand_memopw_io
:
2399 bool HexagonInstrInfo::isNewValue(const MachineInstr
&MI
) const {
2400 const uint64_t F
= MI
.getDesc().TSFlags
;
2401 return (F
>> HexagonII::NewValuePos
) & HexagonII::NewValueMask
;
2404 bool HexagonInstrInfo::isNewValue(unsigned Opcode
) const {
2405 const uint64_t F
= get(Opcode
).TSFlags
;
2406 return (F
>> HexagonII::NewValuePos
) & HexagonII::NewValueMask
;
2409 bool HexagonInstrInfo::isNewValueInst(const MachineInstr
&MI
) const {
2410 return isNewValueJump(MI
) || isNewValueStore(MI
);
2413 bool HexagonInstrInfo::isNewValueJump(const MachineInstr
&MI
) const {
2414 return isNewValue(MI
) && MI
.isBranch();
2417 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode
) const {
2418 return isNewValue(Opcode
) && get(Opcode
).isBranch() && isPredicated(Opcode
);
2421 bool HexagonInstrInfo::isNewValueStore(const MachineInstr
&MI
) const {
2422 const uint64_t F
= MI
.getDesc().TSFlags
;
2423 return (F
>> HexagonII::NVStorePos
) & HexagonII::NVStoreMask
;
2426 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode
) const {
2427 const uint64_t F
= get(Opcode
).TSFlags
;
2428 return (F
>> HexagonII::NVStorePos
) & HexagonII::NVStoreMask
;
2431 // Returns true if a particular operand is extendable for an instruction.
2432 bool HexagonInstrInfo::isOperandExtended(const MachineInstr
&MI
,
2433 unsigned OperandNum
) const {
2434 const uint64_t F
= MI
.getDesc().TSFlags
;
2435 return ((F
>> HexagonII::ExtendableOpPos
) & HexagonII::ExtendableOpMask
)
2439 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr
&MI
) const {
2440 const uint64_t F
= MI
.getDesc().TSFlags
;
2441 assert(isPredicated(MI
));
2442 return (F
>> HexagonII::PredicatedNewPos
) & HexagonII::PredicatedNewMask
;
2445 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode
) const {
2446 const uint64_t F
= get(Opcode
).TSFlags
;
2447 assert(isPredicated(Opcode
));
2448 return (F
>> HexagonII::PredicatedNewPos
) & HexagonII::PredicatedNewMask
;
2451 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr
&MI
) const {
2452 const uint64_t F
= MI
.getDesc().TSFlags
;
2453 return !((F
>> HexagonII::PredicatedFalsePos
) &
2454 HexagonII::PredicatedFalseMask
);
2457 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode
) const {
2458 const uint64_t F
= get(Opcode
).TSFlags
;
2459 // Make sure that the instruction is predicated.
2460 assert((F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
);
2461 return !((F
>> HexagonII::PredicatedFalsePos
) &
2462 HexagonII::PredicatedFalseMask
);
2465 bool HexagonInstrInfo::isPredicated(unsigned Opcode
) const {
2466 const uint64_t F
= get(Opcode
).TSFlags
;
2467 return (F
>> HexagonII::PredicatedPos
) & HexagonII::PredicatedMask
;
2470 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode
) const {
2471 const uint64_t F
= get(Opcode
).TSFlags
;
2472 return (F
>> HexagonII::PredicateLatePos
) & HexagonII::PredicateLateMask
;
2475 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode
) const {
2476 const uint64_t F
= get(Opcode
).TSFlags
;
2477 assert(get(Opcode
).isBranch() &&
2478 (isPredicatedNew(Opcode
) || isNewValue(Opcode
)));
2479 return (F
>> HexagonII::TakenPos
) & HexagonII::TakenMask
;
2482 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr
&MI
) const {
2483 return MI
.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4
||
2484 MI
.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT
||
2485 MI
.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC
||
2486 MI
.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
;
2489 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr
&MI
) const {
2490 switch (MI
.getOpcode()) {
2492 case Hexagon::L2_loadrb_io
:
2493 case Hexagon::L4_loadrb_ur
:
2494 case Hexagon::L4_loadrb_ap
:
2495 case Hexagon::L2_loadrb_pr
:
2496 case Hexagon::L2_loadrb_pbr
:
2497 case Hexagon::L2_loadrb_pi
:
2498 case Hexagon::L2_loadrb_pci
:
2499 case Hexagon::L2_loadrb_pcr
:
2500 case Hexagon::L2_loadbsw2_io
:
2501 case Hexagon::L4_loadbsw2_ur
:
2502 case Hexagon::L4_loadbsw2_ap
:
2503 case Hexagon::L2_loadbsw2_pr
:
2504 case Hexagon::L2_loadbsw2_pbr
:
2505 case Hexagon::L2_loadbsw2_pi
:
2506 case Hexagon::L2_loadbsw2_pci
:
2507 case Hexagon::L2_loadbsw2_pcr
:
2508 case Hexagon::L2_loadbsw4_io
:
2509 case Hexagon::L4_loadbsw4_ur
:
2510 case Hexagon::L4_loadbsw4_ap
:
2511 case Hexagon::L2_loadbsw4_pr
:
2512 case Hexagon::L2_loadbsw4_pbr
:
2513 case Hexagon::L2_loadbsw4_pi
:
2514 case Hexagon::L2_loadbsw4_pci
:
2515 case Hexagon::L2_loadbsw4_pcr
:
2516 case Hexagon::L4_loadrb_rr
:
2517 case Hexagon::L2_ploadrbt_io
:
2518 case Hexagon::L2_ploadrbt_pi
:
2519 case Hexagon::L2_ploadrbf_io
:
2520 case Hexagon::L2_ploadrbf_pi
:
2521 case Hexagon::L2_ploadrbtnew_io
:
2522 case Hexagon::L2_ploadrbfnew_io
:
2523 case Hexagon::L4_ploadrbt_rr
:
2524 case Hexagon::L4_ploadrbf_rr
:
2525 case Hexagon::L4_ploadrbtnew_rr
:
2526 case Hexagon::L4_ploadrbfnew_rr
:
2527 case Hexagon::L2_ploadrbtnew_pi
:
2528 case Hexagon::L2_ploadrbfnew_pi
:
2529 case Hexagon::L4_ploadrbt_abs
:
2530 case Hexagon::L4_ploadrbf_abs
:
2531 case Hexagon::L4_ploadrbtnew_abs
:
2532 case Hexagon::L4_ploadrbfnew_abs
:
2533 case Hexagon::L2_loadrbgp
:
2535 case Hexagon::L2_loadrh_io
:
2536 case Hexagon::L4_loadrh_ur
:
2537 case Hexagon::L4_loadrh_ap
:
2538 case Hexagon::L2_loadrh_pr
:
2539 case Hexagon::L2_loadrh_pbr
:
2540 case Hexagon::L2_loadrh_pi
:
2541 case Hexagon::L2_loadrh_pci
:
2542 case Hexagon::L2_loadrh_pcr
:
2543 case Hexagon::L4_loadrh_rr
:
2544 case Hexagon::L2_ploadrht_io
:
2545 case Hexagon::L2_ploadrht_pi
:
2546 case Hexagon::L2_ploadrhf_io
:
2547 case Hexagon::L2_ploadrhf_pi
:
2548 case Hexagon::L2_ploadrhtnew_io
:
2549 case Hexagon::L2_ploadrhfnew_io
:
2550 case Hexagon::L4_ploadrht_rr
:
2551 case Hexagon::L4_ploadrhf_rr
:
2552 case Hexagon::L4_ploadrhtnew_rr
:
2553 case Hexagon::L4_ploadrhfnew_rr
:
2554 case Hexagon::L2_ploadrhtnew_pi
:
2555 case Hexagon::L2_ploadrhfnew_pi
:
2556 case Hexagon::L4_ploadrht_abs
:
2557 case Hexagon::L4_ploadrhf_abs
:
2558 case Hexagon::L4_ploadrhtnew_abs
:
2559 case Hexagon::L4_ploadrhfnew_abs
:
2560 case Hexagon::L2_loadrhgp
:
2567 bool HexagonInstrInfo::isSolo(const MachineInstr
&MI
) const {
2568 const uint64_t F
= MI
.getDesc().TSFlags
;
2569 return (F
>> HexagonII::SoloPos
) & HexagonII::SoloMask
;
2572 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr
&MI
) const {
2573 switch (MI
.getOpcode()) {
2574 case Hexagon::STriw_pred
:
2575 case Hexagon::LDriw_pred
:
2582 bool HexagonInstrInfo::isTailCall(const MachineInstr
&MI
) const {
2586 for (auto &Op
: MI
.operands())
2587 if (Op
.isGlobal() || Op
.isSymbol())
2592 // Returns true when SU has a timing class TC1.
2593 bool HexagonInstrInfo::isTC1(const MachineInstr
&MI
) const {
2594 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2595 return is_TC1(SchedClass
);
2598 bool HexagonInstrInfo::isTC2(const MachineInstr
&MI
) const {
2599 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2600 return is_TC2(SchedClass
);
2603 bool HexagonInstrInfo::isTC2Early(const MachineInstr
&MI
) const {
2604 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2605 return is_TC2early(SchedClass
);
2608 bool HexagonInstrInfo::isTC4x(const MachineInstr
&MI
) const {
2609 unsigned SchedClass
= MI
.getDesc().getSchedClass();
2610 return is_TC4x(SchedClass
);
2613 // Schedule this ASAP.
2614 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr
&MI1
,
2615 const MachineInstr
&MI2
) const {
2616 if (mayBeCurLoad(MI1
)) {
2617 // if (result of SU is used in Next) return true;
2618 Register DstReg
= MI1
.getOperand(0).getReg();
2619 int N
= MI2
.getNumOperands();
2620 for (int I
= 0; I
< N
; I
++)
2621 if (MI2
.getOperand(I
).isReg() && DstReg
== MI2
.getOperand(I
).getReg())
2624 if (mayBeNewStore(MI2
))
2625 if (MI2
.getOpcode() == Hexagon::V6_vS32b_pi
)
2626 if (MI1
.getOperand(0).isReg() && MI2
.getOperand(3).isReg() &&
2627 MI1
.getOperand(0).getReg() == MI2
.getOperand(3).getReg())
2632 bool HexagonInstrInfo::isHVXVec(const MachineInstr
&MI
) const {
2633 const uint64_t V
= getType(MI
);
2634 return HexagonII::TypeCVI_FIRST
<= V
&& V
<= HexagonII::TypeCVI_LAST
;
2637 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2638 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT
, int Offset
) const {
2639 int Size
= VT
.getSizeInBits() / 8;
2640 if (Offset
% Size
!= 0)
2642 int Count
= Offset
/ Size
;
2644 switch (VT
.getSimpleVT().SimpleTy
) {
2645 // For scalars the auto-inc is s4
2657 return isInt
<4>(Count
);
2658 // For HVX vectors the auto-inc is s3
2667 return isInt
<3>(Count
);
2672 llvm_unreachable("Not an valid type!");
2675 bool HexagonInstrInfo::isValidOffset(unsigned Opcode
, int Offset
,
2676 const TargetRegisterInfo
*TRI
, bool Extend
) const {
2677 // This function is to check whether the "Offset" is in the correct range of
2678 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2679 // inserted to calculate the final address. Due to this reason, the function
2680 // assumes that the "Offset" has correct alignment.
2681 // We used to assert if the offset was not properly aligned, however,
2682 // there are cases where a misaligned pointer recast can cause this
2683 // problem, and we need to allow for it. The front end warns of such
2684 // misaligns with respect to load size.
2686 case Hexagon::PS_vstorerq_ai
:
2687 case Hexagon::PS_vstorerw_ai
:
2688 case Hexagon::PS_vstorerw_nt_ai
:
2689 case Hexagon::PS_vloadrq_ai
:
2690 case Hexagon::PS_vloadrw_ai
:
2691 case Hexagon::PS_vloadrw_nt_ai
:
2692 case Hexagon::V6_vL32b_ai
:
2693 case Hexagon::V6_vS32b_ai
:
2694 case Hexagon::V6_vL32b_nt_ai
:
2695 case Hexagon::V6_vS32b_nt_ai
:
2696 case Hexagon::V6_vL32Ub_ai
:
2697 case Hexagon::V6_vS32Ub_ai
: {
2698 unsigned VectorSize
= TRI
->getSpillSize(Hexagon::HvxVRRegClass
);
2699 assert(isPowerOf2_32(VectorSize
));
2700 if (Offset
& (VectorSize
-1))
2702 return isInt
<4>(Offset
>> Log2_32(VectorSize
));
2705 case Hexagon::J2_loop0i
:
2706 case Hexagon::J2_loop1i
:
2707 return isUInt
<10>(Offset
);
2709 case Hexagon::S4_storeirb_io
:
2710 case Hexagon::S4_storeirbt_io
:
2711 case Hexagon::S4_storeirbf_io
:
2712 return isUInt
<6>(Offset
);
2714 case Hexagon::S4_storeirh_io
:
2715 case Hexagon::S4_storeirht_io
:
2716 case Hexagon::S4_storeirhf_io
:
2717 return isShiftedUInt
<6,1>(Offset
);
2719 case Hexagon::S4_storeiri_io
:
2720 case Hexagon::S4_storeirit_io
:
2721 case Hexagon::S4_storeirif_io
:
2722 return isShiftedUInt
<6,2>(Offset
);
2729 case Hexagon::L2_loadri_io
:
2730 case Hexagon::S2_storeri_io
:
2731 return (Offset
>= Hexagon_MEMW_OFFSET_MIN
) &&
2732 (Offset
<= Hexagon_MEMW_OFFSET_MAX
);
2734 case Hexagon::L2_loadrd_io
:
2735 case Hexagon::S2_storerd_io
:
2736 return (Offset
>= Hexagon_MEMD_OFFSET_MIN
) &&
2737 (Offset
<= Hexagon_MEMD_OFFSET_MAX
);
2739 case Hexagon::L2_loadrh_io
:
2740 case Hexagon::L2_loadruh_io
:
2741 case Hexagon::S2_storerh_io
:
2742 case Hexagon::S2_storerf_io
:
2743 return (Offset
>= Hexagon_MEMH_OFFSET_MIN
) &&
2744 (Offset
<= Hexagon_MEMH_OFFSET_MAX
);
2746 case Hexagon::L2_loadrb_io
:
2747 case Hexagon::L2_loadrub_io
:
2748 case Hexagon::S2_storerb_io
:
2749 return (Offset
>= Hexagon_MEMB_OFFSET_MIN
) &&
2750 (Offset
<= Hexagon_MEMB_OFFSET_MAX
);
2752 case Hexagon::A2_addi
:
2753 return (Offset
>= Hexagon_ADDI_OFFSET_MIN
) &&
2754 (Offset
<= Hexagon_ADDI_OFFSET_MAX
);
2756 case Hexagon::L4_iadd_memopw_io
:
2757 case Hexagon::L4_isub_memopw_io
:
2758 case Hexagon::L4_add_memopw_io
:
2759 case Hexagon::L4_sub_memopw_io
:
2760 case Hexagon::L4_and_memopw_io
:
2761 case Hexagon::L4_or_memopw_io
:
2762 return (0 <= Offset
&& Offset
<= 255);
2764 case Hexagon::L4_iadd_memoph_io
:
2765 case Hexagon::L4_isub_memoph_io
:
2766 case Hexagon::L4_add_memoph_io
:
2767 case Hexagon::L4_sub_memoph_io
:
2768 case Hexagon::L4_and_memoph_io
:
2769 case Hexagon::L4_or_memoph_io
:
2770 return (0 <= Offset
&& Offset
<= 127);
2772 case Hexagon::L4_iadd_memopb_io
:
2773 case Hexagon::L4_isub_memopb_io
:
2774 case Hexagon::L4_add_memopb_io
:
2775 case Hexagon::L4_sub_memopb_io
:
2776 case Hexagon::L4_and_memopb_io
:
2777 case Hexagon::L4_or_memopb_io
:
2778 return (0 <= Offset
&& Offset
<= 63);
2780 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2781 // any size. Later pass knows how to handle it.
2782 case Hexagon::STriw_pred
:
2783 case Hexagon::LDriw_pred
:
2784 case Hexagon::STriw_ctr
:
2785 case Hexagon::LDriw_ctr
:
2788 case Hexagon::PS_fi
:
2789 case Hexagon::PS_fia
:
2790 case Hexagon::INLINEASM
:
2793 case Hexagon::L2_ploadrbt_io
:
2794 case Hexagon::L2_ploadrbf_io
:
2795 case Hexagon::L2_ploadrubt_io
:
2796 case Hexagon::L2_ploadrubf_io
:
2797 case Hexagon::S2_pstorerbt_io
:
2798 case Hexagon::S2_pstorerbf_io
:
2799 return isUInt
<6>(Offset
);
2801 case Hexagon::L2_ploadrht_io
:
2802 case Hexagon::L2_ploadrhf_io
:
2803 case Hexagon::L2_ploadruht_io
:
2804 case Hexagon::L2_ploadruhf_io
:
2805 case Hexagon::S2_pstorerht_io
:
2806 case Hexagon::S2_pstorerhf_io
:
2807 return isShiftedUInt
<6,1>(Offset
);
2809 case Hexagon::L2_ploadrit_io
:
2810 case Hexagon::L2_ploadrif_io
:
2811 case Hexagon::S2_pstorerit_io
:
2812 case Hexagon::S2_pstorerif_io
:
2813 return isShiftedUInt
<6,2>(Offset
);
2815 case Hexagon::L2_ploadrdt_io
:
2816 case Hexagon::L2_ploadrdf_io
:
2817 case Hexagon::S2_pstorerdt_io
:
2818 case Hexagon::S2_pstorerdf_io
:
2819 return isShiftedUInt
<6,3>(Offset
);
2822 llvm_unreachable("No offset range is defined for this opcode. "
2823 "Please define it in the above switch statement!");
2826 bool HexagonInstrInfo::isVecAcc(const MachineInstr
&MI
) const {
2827 return isHVXVec(MI
) && isAccumulator(MI
);
2830 bool HexagonInstrInfo::isVecALU(const MachineInstr
&MI
) const {
2831 const uint64_t F
= get(MI
.getOpcode()).TSFlags
;
2832 const uint64_t V
= ((F
>> HexagonII::TypePos
) & HexagonII::TypeMask
);
2834 V
== HexagonII::TypeCVI_VA
||
2835 V
== HexagonII::TypeCVI_VA_DV
;
2838 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr
&ProdMI
,
2839 const MachineInstr
&ConsMI
) const {
2840 if (EnableACCForwarding
&& isVecAcc(ProdMI
) && isVecAcc(ConsMI
))
2843 if (EnableALUForwarding
&& (isVecALU(ConsMI
) || isLateSourceInstr(ConsMI
)))
2846 if (mayBeNewStore(ConsMI
))
2852 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr
&MI
) const {
2853 switch (MI
.getOpcode()) {
2855 case Hexagon::L2_loadrub_io
:
2856 case Hexagon::L4_loadrub_ur
:
2857 case Hexagon::L4_loadrub_ap
:
2858 case Hexagon::L2_loadrub_pr
:
2859 case Hexagon::L2_loadrub_pbr
:
2860 case Hexagon::L2_loadrub_pi
:
2861 case Hexagon::L2_loadrub_pci
:
2862 case Hexagon::L2_loadrub_pcr
:
2863 case Hexagon::L2_loadbzw2_io
:
2864 case Hexagon::L4_loadbzw2_ur
:
2865 case Hexagon::L4_loadbzw2_ap
:
2866 case Hexagon::L2_loadbzw2_pr
:
2867 case Hexagon::L2_loadbzw2_pbr
:
2868 case Hexagon::L2_loadbzw2_pi
:
2869 case Hexagon::L2_loadbzw2_pci
:
2870 case Hexagon::L2_loadbzw2_pcr
:
2871 case Hexagon::L2_loadbzw4_io
:
2872 case Hexagon::L4_loadbzw4_ur
:
2873 case Hexagon::L4_loadbzw4_ap
:
2874 case Hexagon::L2_loadbzw4_pr
:
2875 case Hexagon::L2_loadbzw4_pbr
:
2876 case Hexagon::L2_loadbzw4_pi
:
2877 case Hexagon::L2_loadbzw4_pci
:
2878 case Hexagon::L2_loadbzw4_pcr
:
2879 case Hexagon::L4_loadrub_rr
:
2880 case Hexagon::L2_ploadrubt_io
:
2881 case Hexagon::L2_ploadrubt_pi
:
2882 case Hexagon::L2_ploadrubf_io
:
2883 case Hexagon::L2_ploadrubf_pi
:
2884 case Hexagon::L2_ploadrubtnew_io
:
2885 case Hexagon::L2_ploadrubfnew_io
:
2886 case Hexagon::L4_ploadrubt_rr
:
2887 case Hexagon::L4_ploadrubf_rr
:
2888 case Hexagon::L4_ploadrubtnew_rr
:
2889 case Hexagon::L4_ploadrubfnew_rr
:
2890 case Hexagon::L2_ploadrubtnew_pi
:
2891 case Hexagon::L2_ploadrubfnew_pi
:
2892 case Hexagon::L4_ploadrubt_abs
:
2893 case Hexagon::L4_ploadrubf_abs
:
2894 case Hexagon::L4_ploadrubtnew_abs
:
2895 case Hexagon::L4_ploadrubfnew_abs
:
2896 case Hexagon::L2_loadrubgp
:
2898 case Hexagon::L2_loadruh_io
:
2899 case Hexagon::L4_loadruh_ur
:
2900 case Hexagon::L4_loadruh_ap
:
2901 case Hexagon::L2_loadruh_pr
:
2902 case Hexagon::L2_loadruh_pbr
:
2903 case Hexagon::L2_loadruh_pi
:
2904 case Hexagon::L2_loadruh_pci
:
2905 case Hexagon::L2_loadruh_pcr
:
2906 case Hexagon::L4_loadruh_rr
:
2907 case Hexagon::L2_ploadruht_io
:
2908 case Hexagon::L2_ploadruht_pi
:
2909 case Hexagon::L2_ploadruhf_io
:
2910 case Hexagon::L2_ploadruhf_pi
:
2911 case Hexagon::L2_ploadruhtnew_io
:
2912 case Hexagon::L2_ploadruhfnew_io
:
2913 case Hexagon::L4_ploadruht_rr
:
2914 case Hexagon::L4_ploadruhf_rr
:
2915 case Hexagon::L4_ploadruhtnew_rr
:
2916 case Hexagon::L4_ploadruhfnew_rr
:
2917 case Hexagon::L2_ploadruhtnew_pi
:
2918 case Hexagon::L2_ploadruhfnew_pi
:
2919 case Hexagon::L4_ploadruht_abs
:
2920 case Hexagon::L4_ploadruhf_abs
:
2921 case Hexagon::L4_ploadruhtnew_abs
:
2922 case Hexagon::L4_ploadruhfnew_abs
:
2923 case Hexagon::L2_loadruhgp
:
2930 // Add latency to instruction.
2931 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr
&MI1
,
2932 const MachineInstr
&MI2
) const {
2933 if (isHVXVec(MI1
) && isHVXVec(MI2
))
2934 if (!isVecUsableNextPacket(MI1
, MI2
))
2939 /// Get the base register and byte offset of a load/store instr.
2940 bool HexagonInstrInfo::getMemOperandWithOffset(
2941 const MachineInstr
&LdSt
, const MachineOperand
*&BaseOp
, int64_t &Offset
,
2942 const TargetRegisterInfo
*TRI
) const {
2943 unsigned AccessSize
= 0;
2944 BaseOp
= getBaseAndOffset(LdSt
, Offset
, AccessSize
);
2945 assert((!BaseOp
|| BaseOp
->isReg()) &&
2946 "getMemOperandWithOffset only supports base "
2947 "operands of type register.");
2948 return BaseOp
!= nullptr;
2951 /// Can these instructions execute at the same time in a bundle.
2952 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr
&First
,
2953 const MachineInstr
&Second
) const {
2954 if (Second
.mayStore() && First
.getOpcode() == Hexagon::S2_allocframe
) {
2955 const MachineOperand
&Op
= Second
.getOperand(0);
2956 if (Op
.isReg() && Op
.isUse() && Op
.getReg() == Hexagon::R29
)
2959 if (DisableNVSchedule
)
2961 if (mayBeNewStore(Second
)) {
2962 // Make sure the definition of the first instruction is the value being
2964 const MachineOperand
&Stored
=
2965 Second
.getOperand(Second
.getNumOperands() - 1);
2966 if (!Stored
.isReg())
2968 for (unsigned i
= 0, e
= First
.getNumOperands(); i
< e
; ++i
) {
2969 const MachineOperand
&Op
= First
.getOperand(i
);
2970 if (Op
.isReg() && Op
.isDef() && Op
.getReg() == Stored
.getReg())
2977 bool HexagonInstrInfo::doesNotReturn(const MachineInstr
&CallMI
) const {
2978 unsigned Opc
= CallMI
.getOpcode();
2979 return Opc
== Hexagon::PS_call_nr
|| Opc
== Hexagon::PS_callr_nr
;
2982 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock
*B
) const {
2989 // Returns true if an instruction can be converted into a non-extended
2990 // equivalent instruction.
2991 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr
&MI
) const {
2993 // Check if the instruction has a register form that uses register in place
2994 // of the extended operand, if so return that as the non-extended form.
2995 if (Hexagon::getRegForm(MI
.getOpcode()) >= 0)
2998 if (MI
.getDesc().mayLoad() || MI
.getDesc().mayStore()) {
2999 // Check addressing mode and retrieve non-ext equivalent instruction.
3001 switch (getAddrMode(MI
)) {
3002 case HexagonII::Absolute
:
3003 // Load/store with absolute addressing mode can be converted into
3004 // base+offset mode.
3005 NonExtOpcode
= Hexagon::changeAddrMode_abs_io(MI
.getOpcode());
3007 case HexagonII::BaseImmOffset
:
3008 // Load/store with base+offset addressing mode can be converted into
3009 // base+register offset addressing mode. However left shift operand should
3011 NonExtOpcode
= Hexagon::changeAddrMode_io_rr(MI
.getOpcode());
3013 case HexagonII::BaseLongOffset
:
3014 NonExtOpcode
= Hexagon::changeAddrMode_ur_rr(MI
.getOpcode());
3019 if (NonExtOpcode
< 0)
3026 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr
&MI
) const {
3027 return Hexagon::getRealHWInstr(MI
.getOpcode(),
3028 Hexagon::InstrType_Pseudo
) >= 0;
3031 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock
*B
)
3033 MachineBasicBlock::const_iterator I
= B
->getFirstTerminator(), E
= B
->end();
3042 // Returns true, if a LD insn can be promoted to a cur load.
3043 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr
&MI
) const {
3044 const uint64_t F
= MI
.getDesc().TSFlags
;
3045 return ((F
>> HexagonII::mayCVLoadPos
) & HexagonII::mayCVLoadMask
) &&
3046 Subtarget
.hasV60Ops();
3049 // Returns true, if a ST insn can be promoted to a new-value store.
3050 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr
&MI
) const {
3051 if (MI
.mayStore() && !Subtarget
.useNewValueStores())
3054 const uint64_t F
= MI
.getDesc().TSFlags
;
3055 return (F
>> HexagonII::mayNVStorePos
) & HexagonII::mayNVStoreMask
;
3058 bool HexagonInstrInfo::producesStall(const MachineInstr
&ProdMI
,
3059 const MachineInstr
&ConsMI
) const {
3060 // There is no stall when ProdMI is not a V60 vector.
3061 if (!isHVXVec(ProdMI
))
3064 // There is no stall when ProdMI and ConsMI are not dependent.
3065 if (!isDependent(ProdMI
, ConsMI
))
3068 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3069 // are scheduled in consecutive packets.
3070 if (isVecUsableNextPacket(ProdMI
, ConsMI
))
3076 bool HexagonInstrInfo::producesStall(const MachineInstr
&MI
,
3077 MachineBasicBlock::const_instr_iterator BII
) const {
3078 // There is no stall when I is not a V60 vector.
3082 MachineBasicBlock::const_instr_iterator MII
= BII
;
3083 MachineBasicBlock::const_instr_iterator MIE
= MII
->getParent()->instr_end();
3085 if (!MII
->isBundle())
3086 return producesStall(*MII
, MI
);
3088 for (++MII
; MII
!= MIE
&& MII
->isInsideBundle(); ++MII
) {
3089 const MachineInstr
&J
= *MII
;
3090 if (producesStall(J
, MI
))
3096 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr
&MI
,
3097 unsigned PredReg
) const {
3098 for (const MachineOperand
&MO
: MI
.operands()) {
3099 // Predicate register must be explicitly defined.
3100 if (MO
.isRegMask() && MO
.clobbersPhysReg(PredReg
))
3102 if (MO
.isReg() && MO
.isDef() && MO
.isImplicit() && (MO
.getReg() == PredReg
))
3106 // Instruction that produce late predicate cannot be used as sources of
3108 switch (MI
.getOpcode()) {
3109 case Hexagon::A4_addp_c
:
3110 case Hexagon::A4_subp_c
:
3111 case Hexagon::A4_tlbmatch
:
3112 case Hexagon::A5_ACS
:
3113 case Hexagon::F2_sfinvsqrta
:
3114 case Hexagon::F2_sfrecipa
:
3115 case Hexagon::J2_endloop0
:
3116 case Hexagon::J2_endloop01
:
3117 case Hexagon::J2_ploop1si
:
3118 case Hexagon::J2_ploop1sr
:
3119 case Hexagon::J2_ploop2si
:
3120 case Hexagon::J2_ploop2sr
:
3121 case Hexagon::J2_ploop3si
:
3122 case Hexagon::J2_ploop3sr
:
3123 case Hexagon::S2_cabacdecbin
:
3124 case Hexagon::S2_storew_locked
:
3125 case Hexagon::S4_stored_locked
:
3131 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode
) const {
3132 return Opcode
== Hexagon::J2_jumpt
||
3133 Opcode
== Hexagon::J2_jumptpt
||
3134 Opcode
== Hexagon::J2_jumpf
||
3135 Opcode
== Hexagon::J2_jumpfpt
||
3136 Opcode
== Hexagon::J2_jumptnew
||
3137 Opcode
== Hexagon::J2_jumpfnew
||
3138 Opcode
== Hexagon::J2_jumptnewpt
||
3139 Opcode
== Hexagon::J2_jumpfnewpt
;
3142 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef
<MachineOperand
> Cond
) const {
3143 if (Cond
.empty() || !isPredicated(Cond
[0].getImm()))
3145 return !isPredicatedTrue(Cond
[0].getImm());
3148 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr
&MI
) const {
3149 const uint64_t F
= MI
.getDesc().TSFlags
;
3150 return (F
>> HexagonII::AddrModePos
) & HexagonII::AddrModeMask
;
3153 // Returns the base register in a memory access (load/store). The offset is
3154 // returned in Offset and the access size is returned in AccessSize.
3155 // If the base operand has a subregister or the offset field does not contain
3156 // an immediate value, return nullptr.
3157 MachineOperand
*HexagonInstrInfo::getBaseAndOffset(const MachineInstr
&MI
,
3159 unsigned &AccessSize
) const {
3160 // Return if it is not a base+offset type instruction or a MemOp.
3161 if (getAddrMode(MI
) != HexagonII::BaseImmOffset
&&
3162 getAddrMode(MI
) != HexagonII::BaseLongOffset
&&
3163 !isMemOp(MI
) && !isPostIncrement(MI
))
3166 AccessSize
= getMemAccessSize(MI
);
3168 unsigned BasePos
= 0, OffsetPos
= 0;
3169 if (!getBaseAndOffsetPosition(MI
, BasePos
, OffsetPos
))
3172 // Post increment updates its EA after the mem access,
3173 // so we need to treat its offset as zero.
3174 if (isPostIncrement(MI
)) {
3177 const MachineOperand
&OffsetOp
= MI
.getOperand(OffsetPos
);
3178 if (!OffsetOp
.isImm())
3180 Offset
= OffsetOp
.getImm();
3183 const MachineOperand
&BaseOp
= MI
.getOperand(BasePos
);
3184 if (BaseOp
.getSubReg() != 0)
3186 return &const_cast<MachineOperand
&>(BaseOp
);
3189 /// Return the position of the base and offset operands for this instruction.
3190 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr
&MI
,
3191 unsigned &BasePos
, unsigned &OffsetPos
) const {
3192 if (!isAddrModeWithOffset(MI
) && !isPostIncrement(MI
))
3195 // Deal with memops first.
3199 } else if (MI
.mayStore()) {
3202 } else if (MI
.mayLoad()) {
3208 if (isPredicated(MI
)) {
3212 if (isPostIncrement(MI
)) {
3217 if (!MI
.getOperand(BasePos
).isReg() || !MI
.getOperand(OffsetPos
).isImm())
3223 // Inserts branching instructions in reverse order of their occurrence.
3224 // e.g. jump_t t1 (i1)
3226 // Jumpers = {i2, i1}
3227 SmallVector
<MachineInstr
*, 2> HexagonInstrInfo::getBranchingInstrs(
3228 MachineBasicBlock
& MBB
) const {
3229 SmallVector
<MachineInstr
*, 2> Jumpers
;
3230 // If the block has no terminators, it just falls into the block after it.
3231 MachineBasicBlock::instr_iterator I
= MBB
.instr_end();
3232 if (I
== MBB
.instr_begin())
3235 // A basic block may looks like this:
3245 // It has two succs but does not have a terminator
3246 // Don't know how to handle it.
3251 } while (I
!= MBB
.instr_begin());
3253 I
= MBB
.instr_end();
3256 while (I
->isDebugInstr()) {
3257 if (I
== MBB
.instr_begin())
3261 if (!isUnpredicatedTerminator(*I
))
3264 // Get the last instruction in the block.
3265 MachineInstr
*LastInst
= &*I
;
3266 Jumpers
.push_back(LastInst
);
3267 MachineInstr
*SecondLastInst
= nullptr;
3268 // Find one more terminator if present.
3270 if (&*I
!= LastInst
&& !I
->isBundle() && isUnpredicatedTerminator(*I
)) {
3271 if (!SecondLastInst
) {
3272 SecondLastInst
= &*I
;
3273 Jumpers
.push_back(SecondLastInst
);
3274 } else // This is a third branch.
3277 if (I
== MBB
.instr_begin())
3284 // Returns Operand Index for the constant extended instruction.
3285 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr
&MI
) const {
3286 const uint64_t F
= MI
.getDesc().TSFlags
;
3287 return (F
>> HexagonII::ExtendableOpPos
) & HexagonII::ExtendableOpMask
;
3290 // See if instruction could potentially be a duplex candidate.
3291 // If so, return its group. Zero otherwise.
3292 HexagonII::CompoundGroup
HexagonInstrInfo::getCompoundCandidateGroup(
3293 const MachineInstr
&MI
) const {
3294 unsigned DstReg
, SrcReg
, Src1Reg
, Src2Reg
;
3296 switch (MI
.getOpcode()) {
3298 return HexagonII::HCG_None
;
3301 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3302 // "Rd16=#U6 ; jump #r9:2"
3303 // "Rd16=Rs16 ; jump #r9:2"
3305 case Hexagon::C2_cmpeq
:
3306 case Hexagon::C2_cmpgt
:
3307 case Hexagon::C2_cmpgtu
:
3308 DstReg
= MI
.getOperand(0).getReg();
3309 Src1Reg
= MI
.getOperand(1).getReg();
3310 Src2Reg
= MI
.getOperand(2).getReg();
3311 if (Hexagon::PredRegsRegClass
.contains(DstReg
) &&
3312 (Hexagon::P0
== DstReg
|| Hexagon::P1
== DstReg
) &&
3313 isIntRegForSubInst(Src1Reg
) && isIntRegForSubInst(Src2Reg
))
3314 return HexagonII::HCG_A
;
3316 case Hexagon::C2_cmpeqi
:
3317 case Hexagon::C2_cmpgti
:
3318 case Hexagon::C2_cmpgtui
:
3319 // P0 = cmp.eq(Rs,#u2)
3320 DstReg
= MI
.getOperand(0).getReg();
3321 SrcReg
= MI
.getOperand(1).getReg();
3322 if (Hexagon::PredRegsRegClass
.contains(DstReg
) &&
3323 (Hexagon::P0
== DstReg
|| Hexagon::P1
== DstReg
) &&
3324 isIntRegForSubInst(SrcReg
) && MI
.getOperand(2).isImm() &&
3325 ((isUInt
<5>(MI
.getOperand(2).getImm())) ||
3326 (MI
.getOperand(2).getImm() == -1)))
3327 return HexagonII::HCG_A
;
3329 case Hexagon::A2_tfr
:
3331 DstReg
= MI
.getOperand(0).getReg();
3332 SrcReg
= MI
.getOperand(1).getReg();
3333 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
))
3334 return HexagonII::HCG_A
;
3336 case Hexagon::A2_tfrsi
:
3338 // Do not test for #u6 size since the const is getting extended
3339 // regardless and compound could be formed.
3340 DstReg
= MI
.getOperand(0).getReg();
3341 if (isIntRegForSubInst(DstReg
))
3342 return HexagonII::HCG_A
;
3344 case Hexagon::S2_tstbit_i
:
3345 DstReg
= MI
.getOperand(0).getReg();
3346 Src1Reg
= MI
.getOperand(1).getReg();
3347 if (Hexagon::PredRegsRegClass
.contains(DstReg
) &&
3348 (Hexagon::P0
== DstReg
|| Hexagon::P1
== DstReg
) &&
3349 MI
.getOperand(2).isImm() &&
3350 isIntRegForSubInst(Src1Reg
) && (MI
.getOperand(2).getImm() == 0))
3351 return HexagonII::HCG_A
;
3353 // The fact that .new form is used pretty much guarantees
3354 // that predicate register will match. Nevertheless,
3355 // there could be some false positives without additional
3357 case Hexagon::J2_jumptnew
:
3358 case Hexagon::J2_jumpfnew
:
3359 case Hexagon::J2_jumptnewpt
:
3360 case Hexagon::J2_jumpfnewpt
:
3361 Src1Reg
= MI
.getOperand(0).getReg();
3362 if (Hexagon::PredRegsRegClass
.contains(Src1Reg
) &&
3363 (Hexagon::P0
== Src1Reg
|| Hexagon::P1
== Src1Reg
))
3364 return HexagonII::HCG_B
;
3366 // Transfer and jump:
3367 // Rd=#U6 ; jump #r9:2
3368 // Rd=Rs ; jump #r9:2
3369 // Do not test for jump range here.
3370 case Hexagon::J2_jump
:
3371 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4
:
3372 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
:
3373 return HexagonII::HCG_C
;
3376 return HexagonII::HCG_None
;
3379 // Returns -1 when there is no opcode found.
3380 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr
&GA
,
3381 const MachineInstr
&GB
) const {
3382 assert(getCompoundCandidateGroup(GA
) == HexagonII::HCG_A
);
3383 assert(getCompoundCandidateGroup(GB
) == HexagonII::HCG_B
);
3384 if ((GA
.getOpcode() != Hexagon::C2_cmpeqi
) ||
3385 (GB
.getOpcode() != Hexagon::J2_jumptnew
))
3387 Register DestReg
= GA
.getOperand(0).getReg();
3388 if (!GB
.readsRegister(DestReg
))
3390 if (DestReg
!= Hexagon::P0
&& DestReg
!= Hexagon::P1
)
3392 // The value compared against must be either u5 or -1.
3393 const MachineOperand
&CmpOp
= GA
.getOperand(2);
3396 int V
= CmpOp
.getImm();
3398 return DestReg
== Hexagon::P0
? Hexagon::J4_cmpeqn1_tp0_jump_nt
3399 : Hexagon::J4_cmpeqn1_tp1_jump_nt
;
3402 return DestReg
== Hexagon::P0
? Hexagon::J4_cmpeqi_tp0_jump_nt
3403 : Hexagon::J4_cmpeqi_tp1_jump_nt
;
3406 int HexagonInstrInfo::getCondOpcode(int Opc
, bool invertPredicate
) const {
3407 enum Hexagon::PredSense inPredSense
;
3408 inPredSense
= invertPredicate
? Hexagon::PredSense_false
:
3409 Hexagon::PredSense_true
;
3410 int CondOpcode
= Hexagon::getPredOpcode(Opc
, inPredSense
);
3411 if (CondOpcode
>= 0) // Valid Conditional opcode/instruction
3414 llvm_unreachable("Unexpected predicable instruction");
3417 // Return the cur value instruction for a given store.
3418 int HexagonInstrInfo::getDotCurOp(const MachineInstr
&MI
) const {
3419 switch (MI
.getOpcode()) {
3420 default: llvm_unreachable("Unknown .cur type");
3421 case Hexagon::V6_vL32b_pi
:
3422 return Hexagon::V6_vL32b_cur_pi
;
3423 case Hexagon::V6_vL32b_ai
:
3424 return Hexagon::V6_vL32b_cur_ai
;
3425 case Hexagon::V6_vL32b_nt_pi
:
3426 return Hexagon::V6_vL32b_nt_cur_pi
;
3427 case Hexagon::V6_vL32b_nt_ai
:
3428 return Hexagon::V6_vL32b_nt_cur_ai
;
3433 // Return the regular version of the .cur instruction.
3434 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr
&MI
) const {
3435 switch (MI
.getOpcode()) {
3436 default: llvm_unreachable("Unknown .cur type");
3437 case Hexagon::V6_vL32b_cur_pi
:
3438 return Hexagon::V6_vL32b_pi
;
3439 case Hexagon::V6_vL32b_cur_ai
:
3440 return Hexagon::V6_vL32b_ai
;
3441 case Hexagon::V6_vL32b_nt_cur_pi
:
3442 return Hexagon::V6_vL32b_nt_pi
;
3443 case Hexagon::V6_vL32b_nt_cur_ai
:
3444 return Hexagon::V6_vL32b_nt_ai
;
3449 // The diagram below shows the steps involved in the conversion of a predicated
3450 // store instruction to its .new predicated new-value form.
3452 // Note: It doesn't include conditional new-value stores as they can't be
3453 // converted to .new predicate.
3455 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3457 // / \ (not OK. it will cause new-value store to be
3458 // / X conditional on p0.new while R2 producer is
3461 // p.new store p.old NV store
3462 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3468 // [if (p0)memw(R0+#0)=R2]
3470 // The following set of instructions further explains the scenario where
3471 // conditional new-value store becomes invalid when promoted to .new predicate
3474 // { 1) if (p0) r0 = add(r1, r2)
3475 // 2) p0 = cmp.eq(r3, #0) }
3477 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3478 // the first two instructions because in instr 1, r0 is conditional on old value
3479 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3480 // is not valid for new-value stores.
3481 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3482 // from the "Conditional Store" list. Because a predicated new value store
3483 // would NOT be promoted to a double dot new store. See diagram below:
3484 // This function returns yes for those stores that are predicated but not
3485 // yet promoted to predicate dot new instructions.
3487 // +---------------------+
3488 // /-----| if (p0) memw(..)=r0 |---------\~
3489 // || +---------------------+ ||
3490 // promote || /\ /\ || promote
3492 // \||/ demote || \||/
3494 // +-------------------------+ || +-------------------------+
3495 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3496 // +-------------------------+ || +-------------------------+
3499 // promote || \/ NOT possible
3503 // +-----------------------------+
3504 // | if (p0.new) memw(..)=r0.new |
3505 // +-----------------------------+
3506 // Double Dot New Store
3508 // Returns the most basic instruction for the .new predicated instructions and
3509 // new-value stores.
3510 // For example, all of the following instructions will be converted back to the
3511 // same instruction:
3512 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3513 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3514 // 3) if (p0.new) memw(R0+#0) = R1 --->
3516 // To understand the translation of instruction 1 to its original form, consider
3517 // a packet with 3 instructions.
3518 // { p0 = cmp.eq(R0,R1)
3519 // if (p0.new) R2 = add(R3, R4)
3520 // R5 = add (R3, R1)
3522 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3524 // This instruction can be part of the previous packet only if both p0 and R2
3525 // are promoted to .new values. This promotion happens in steps, first
3526 // predicate register is promoted to .new and in the next iteration R2 is
3527 // promoted. Therefore, in case of dependence check failure (due to R5) during
3528 // next iteration, it should be converted back to its most basic form.
3530 // Return the new value instruction for a given store.
3531 int HexagonInstrInfo::getDotNewOp(const MachineInstr
&MI
) const {
3532 int NVOpcode
= Hexagon::getNewValueOpcode(MI
.getOpcode());
3533 if (NVOpcode
>= 0) // Valid new-value store instruction.
3536 switch (MI
.getOpcode()) {
3538 report_fatal_error(std::string("Unknown .new type: ") +
3539 std::to_string(MI
.getOpcode()));
3540 case Hexagon::S4_storerb_ur
:
3541 return Hexagon::S4_storerbnew_ur
;
3543 case Hexagon::S2_storerb_pci
:
3544 return Hexagon::S2_storerb_pci
;
3546 case Hexagon::S2_storeri_pci
:
3547 return Hexagon::S2_storeri_pci
;
3549 case Hexagon::S2_storerh_pci
:
3550 return Hexagon::S2_storerh_pci
;
3552 case Hexagon::S2_storerd_pci
:
3553 return Hexagon::S2_storerd_pci
;
3555 case Hexagon::S2_storerf_pci
:
3556 return Hexagon::S2_storerf_pci
;
3558 case Hexagon::V6_vS32b_ai
:
3559 return Hexagon::V6_vS32b_new_ai
;
3561 case Hexagon::V6_vS32b_pi
:
3562 return Hexagon::V6_vS32b_new_pi
;
3567 // Returns the opcode to use when converting MI, which is a conditional jump,
3568 // into a conditional instruction which uses the .new value of the predicate.
3569 // We also use branch probabilities to add a hint to the jump.
3570 // If MBPI is null, all edges will be treated as equally likely for the
3571 // purposes of establishing a predication hint.
3572 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr
&MI
,
3573 const MachineBranchProbabilityInfo
*MBPI
) const {
3574 // We assume that block can have at most two successors.
3575 const MachineBasicBlock
*Src
= MI
.getParent();
3576 const MachineOperand
&BrTarget
= MI
.getOperand(1);
3578 const BranchProbability
OneHalf(1, 2);
3580 auto getEdgeProbability
= [MBPI
] (const MachineBasicBlock
*Src
,
3581 const MachineBasicBlock
*Dst
) {
3583 return MBPI
->getEdgeProbability(Src
, Dst
);
3584 return BranchProbability(1, Src
->succ_size());
3587 if (BrTarget
.isMBB()) {
3588 const MachineBasicBlock
*Dst
= BrTarget
.getMBB();
3589 Taken
= getEdgeProbability(Src
, Dst
) >= OneHalf
;
3591 // The branch target is not a basic block (most likely a function).
3592 // Since BPI only gives probabilities for targets that are basic blocks,
3593 // try to identify another target of this branch (potentially a fall-
3594 // -through) and check the probability of that target.
3596 // The only handled branch combinations are:
3597 // - one conditional branch,
3598 // - one conditional branch followed by one unconditional branch.
3599 // Otherwise, assume not-taken.
3600 assert(MI
.isConditionalBranch());
3601 const MachineBasicBlock
&B
= *MI
.getParent();
3602 bool SawCond
= false, Bad
= false;
3603 for (const MachineInstr
&I
: B
) {
3606 if (I
.isConditionalBranch()) {
3613 if (I
.isUnconditionalBranch() && !SawCond
) {
3619 MachineBasicBlock::const_instr_iterator
It(MI
);
3620 MachineBasicBlock::const_instr_iterator NextIt
= std::next(It
);
3621 if (NextIt
== B
.instr_end()) {
3622 // If this branch is the last, look for the fall-through block.
3623 for (const MachineBasicBlock
*SB
: B
.successors()) {
3624 if (!B
.isLayoutSuccessor(SB
))
3626 Taken
= getEdgeProbability(Src
, SB
) < OneHalf
;
3630 assert(NextIt
->isUnconditionalBranch());
3631 // Find the first MBB operand and assume it's the target.
3632 const MachineBasicBlock
*BT
= nullptr;
3633 for (const MachineOperand
&Op
: NextIt
->operands()) {
3639 Taken
= BT
&& getEdgeProbability(Src
, BT
) < OneHalf
;
3644 // The Taken flag should be set to something reasonable by this point.
3646 switch (MI
.getOpcode()) {
3647 case Hexagon::J2_jumpt
:
3648 return Taken
? Hexagon::J2_jumptnewpt
: Hexagon::J2_jumptnew
;
3649 case Hexagon::J2_jumpf
:
3650 return Taken
? Hexagon::J2_jumpfnewpt
: Hexagon::J2_jumpfnew
;
3653 llvm_unreachable("Unexpected jump instruction.");
3657 // Return .new predicate version for an instruction.
3658 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr
&MI
,
3659 const MachineBranchProbabilityInfo
*MBPI
) const {
3660 switch (MI
.getOpcode()) {
3662 case Hexagon::J2_jumpt
:
3663 case Hexagon::J2_jumpf
:
3664 return getDotNewPredJumpOp(MI
, MBPI
);
3667 int NewOpcode
= Hexagon::getPredNewOpcode(MI
.getOpcode());
3673 int HexagonInstrInfo::getDotOldOp(const MachineInstr
&MI
) const {
3674 int NewOp
= MI
.getOpcode();
3675 if (isPredicated(NewOp
) && isPredicatedNew(NewOp
)) { // Get predicate old form
3676 NewOp
= Hexagon::getPredOldOpcode(NewOp
);
3677 // All Hexagon architectures have prediction bits on dot-new branches,
3678 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3679 // to pick the right opcode when converting back to dot-old.
3680 if (!Subtarget
.getFeatureBits()[Hexagon::ArchV60
]) {
3682 case Hexagon::J2_jumptpt
:
3683 NewOp
= Hexagon::J2_jumpt
;
3685 case Hexagon::J2_jumpfpt
:
3686 NewOp
= Hexagon::J2_jumpf
;
3688 case Hexagon::J2_jumprtpt
:
3689 NewOp
= Hexagon::J2_jumprt
;
3691 case Hexagon::J2_jumprfpt
:
3692 NewOp
= Hexagon::J2_jumprf
;
3696 assert(NewOp
>= 0 &&
3697 "Couldn't change predicate new instruction to its old form.");
3700 if (isNewValueStore(NewOp
)) { // Convert into non-new-value format
3701 NewOp
= Hexagon::getNonNVStore(NewOp
);
3702 assert(NewOp
>= 0 && "Couldn't change new-value store to its old form.");
3705 if (Subtarget
.hasV60Ops())
3708 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3710 case Hexagon::J2_jumpfpt
:
3711 return Hexagon::J2_jumpf
;
3712 case Hexagon::J2_jumptpt
:
3713 return Hexagon::J2_jumpt
;
3714 case Hexagon::J2_jumprfpt
:
3715 return Hexagon::J2_jumprf
;
3716 case Hexagon::J2_jumprtpt
:
3717 return Hexagon::J2_jumprt
;
3722 // See if instruction could potentially be a duplex candidate.
3723 // If so, return its group. Zero otherwise.
3724 HexagonII::SubInstructionGroup
HexagonInstrInfo::getDuplexCandidateGroup(
3725 const MachineInstr
&MI
) const {
3726 unsigned DstReg
, SrcReg
, Src1Reg
, Src2Reg
;
3727 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
3729 switch (MI
.getOpcode()) {
3731 return HexagonII::HSIG_None
;
3735 // Rd = memw(Rs+#u4:2)
3736 // Rd = memub(Rs+#u4:0)
3737 case Hexagon::L2_loadri_io
:
3738 DstReg
= MI
.getOperand(0).getReg();
3739 SrcReg
= MI
.getOperand(1).getReg();
3740 // Special case this one from Group L2.
3741 // Rd = memw(r29+#u5:2)
3742 if (isIntRegForSubInst(DstReg
)) {
3743 if (Hexagon::IntRegsRegClass
.contains(SrcReg
) &&
3744 HRI
.getStackRegister() == SrcReg
&&
3745 MI
.getOperand(2).isImm() &&
3746 isShiftedUInt
<5,2>(MI
.getOperand(2).getImm()))
3747 return HexagonII::HSIG_L2
;
3748 // Rd = memw(Rs+#u4:2)
3749 if (isIntRegForSubInst(SrcReg
) &&
3750 (MI
.getOperand(2).isImm() &&
3751 isShiftedUInt
<4,2>(MI
.getOperand(2).getImm())))
3752 return HexagonII::HSIG_L1
;
3755 case Hexagon::L2_loadrub_io
:
3756 // Rd = memub(Rs+#u4:0)
3757 DstReg
= MI
.getOperand(0).getReg();
3758 SrcReg
= MI
.getOperand(1).getReg();
3759 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
) &&
3760 MI
.getOperand(2).isImm() && isUInt
<4>(MI
.getOperand(2).getImm()))
3761 return HexagonII::HSIG_L1
;
3766 // Rd = memh/memuh(Rs+#u3:1)
3767 // Rd = memb(Rs+#u3:0)
3768 // Rd = memw(r29+#u5:2) - Handled above.
3769 // Rdd = memd(r29+#u5:3)
3771 // [if ([!]p0[.new])] dealloc_return
3772 // [if ([!]p0[.new])] jumpr r31
3773 case Hexagon::L2_loadrh_io
:
3774 case Hexagon::L2_loadruh_io
:
3775 // Rd = memh/memuh(Rs+#u3:1)
3776 DstReg
= MI
.getOperand(0).getReg();
3777 SrcReg
= MI
.getOperand(1).getReg();
3778 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
) &&
3779 MI
.getOperand(2).isImm() &&
3780 isShiftedUInt
<3,1>(MI
.getOperand(2).getImm()))
3781 return HexagonII::HSIG_L2
;
3783 case Hexagon::L2_loadrb_io
:
3784 // Rd = memb(Rs+#u3:0)
3785 DstReg
= MI
.getOperand(0).getReg();
3786 SrcReg
= MI
.getOperand(1).getReg();
3787 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
) &&
3788 MI
.getOperand(2).isImm() &&
3789 isUInt
<3>(MI
.getOperand(2).getImm()))
3790 return HexagonII::HSIG_L2
;
3792 case Hexagon::L2_loadrd_io
:
3793 // Rdd = memd(r29+#u5:3)
3794 DstReg
= MI
.getOperand(0).getReg();
3795 SrcReg
= MI
.getOperand(1).getReg();
3796 if (isDblRegForSubInst(DstReg
, HRI
) &&
3797 Hexagon::IntRegsRegClass
.contains(SrcReg
) &&
3798 HRI
.getStackRegister() == SrcReg
&&
3799 MI
.getOperand(2).isImm() &&
3800 isShiftedUInt
<5,3>(MI
.getOperand(2).getImm()))
3801 return HexagonII::HSIG_L2
;
3803 // dealloc_return is not documented in Hexagon Manual, but marked
3804 // with A_SUBINSN attribute in iset_v4classic.py.
3805 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4
:
3806 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
:
3807 case Hexagon::L4_return
:
3808 case Hexagon::L2_deallocframe
:
3809 return HexagonII::HSIG_L2
;
3810 case Hexagon::EH_RETURN_JMPR
:
3811 case Hexagon::PS_jmpret
:
3812 case Hexagon::SL2_jumpr31
:
3814 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3815 DstReg
= MI
.getOperand(0).getReg();
3816 if (Hexagon::IntRegsRegClass
.contains(DstReg
) && (Hexagon::R31
== DstReg
))
3817 return HexagonII::HSIG_L2
;
3819 case Hexagon::PS_jmprett
:
3820 case Hexagon::PS_jmpretf
:
3821 case Hexagon::PS_jmprettnewpt
:
3822 case Hexagon::PS_jmpretfnewpt
:
3823 case Hexagon::PS_jmprettnew
:
3824 case Hexagon::PS_jmpretfnew
:
3825 case Hexagon::SL2_jumpr31_t
:
3826 case Hexagon::SL2_jumpr31_f
:
3827 case Hexagon::SL2_jumpr31_tnew
:
3828 DstReg
= MI
.getOperand(1).getReg();
3829 SrcReg
= MI
.getOperand(0).getReg();
3830 // [if ([!]p0[.new])] jumpr r31
3831 if ((Hexagon::PredRegsRegClass
.contains(SrcReg
) &&
3832 (Hexagon::P0
== SrcReg
)) &&
3833 (Hexagon::IntRegsRegClass
.contains(DstReg
) && (Hexagon::R31
== DstReg
)))
3834 return HexagonII::HSIG_L2
;
3836 case Hexagon::L4_return_t
:
3837 case Hexagon::L4_return_f
:
3838 case Hexagon::L4_return_tnew_pnt
:
3839 case Hexagon::L4_return_fnew_pnt
:
3840 case Hexagon::L4_return_tnew_pt
:
3841 case Hexagon::L4_return_fnew_pt
:
3842 // [if ([!]p0[.new])] dealloc_return
3843 SrcReg
= MI
.getOperand(0).getReg();
3844 if (Hexagon::PredRegsRegClass
.contains(SrcReg
) && (Hexagon::P0
== SrcReg
))
3845 return HexagonII::HSIG_L2
;
3850 // memw(Rs+#u4:2) = Rt
3851 // memb(Rs+#u4:0) = Rt
3852 case Hexagon::S2_storeri_io
:
3853 // Special case this one from Group S2.
3854 // memw(r29+#u5:2) = Rt
3855 Src1Reg
= MI
.getOperand(0).getReg();
3856 Src2Reg
= MI
.getOperand(2).getReg();
3857 if (Hexagon::IntRegsRegClass
.contains(Src1Reg
) &&
3858 isIntRegForSubInst(Src2Reg
) &&
3859 HRI
.getStackRegister() == Src1Reg
&& MI
.getOperand(1).isImm() &&
3860 isShiftedUInt
<5,2>(MI
.getOperand(1).getImm()))
3861 return HexagonII::HSIG_S2
;
3862 // memw(Rs+#u4:2) = Rt
3863 if (isIntRegForSubInst(Src1Reg
) && isIntRegForSubInst(Src2Reg
) &&
3864 MI
.getOperand(1).isImm() &&
3865 isShiftedUInt
<4,2>(MI
.getOperand(1).getImm()))
3866 return HexagonII::HSIG_S1
;
3868 case Hexagon::S2_storerb_io
:
3869 // memb(Rs+#u4:0) = Rt
3870 Src1Reg
= MI
.getOperand(0).getReg();
3871 Src2Reg
= MI
.getOperand(2).getReg();
3872 if (isIntRegForSubInst(Src1Reg
) && isIntRegForSubInst(Src2Reg
) &&
3873 MI
.getOperand(1).isImm() && isUInt
<4>(MI
.getOperand(1).getImm()))
3874 return HexagonII::HSIG_S1
;
3879 // memh(Rs+#u3:1) = Rt
3880 // memw(r29+#u5:2) = Rt
3881 // memd(r29+#s6:3) = Rtt
3882 // memw(Rs+#u4:2) = #U1
3883 // memb(Rs+#u4) = #U1
3884 // allocframe(#u5:3)
3885 case Hexagon::S2_storerh_io
:
3886 // memh(Rs+#u3:1) = Rt
3887 Src1Reg
= MI
.getOperand(0).getReg();
3888 Src2Reg
= MI
.getOperand(2).getReg();
3889 if (isIntRegForSubInst(Src1Reg
) && isIntRegForSubInst(Src2Reg
) &&
3890 MI
.getOperand(1).isImm() &&
3891 isShiftedUInt
<3,1>(MI
.getOperand(1).getImm()))
3892 return HexagonII::HSIG_S1
;
3894 case Hexagon::S2_storerd_io
:
3895 // memd(r29+#s6:3) = Rtt
3896 Src1Reg
= MI
.getOperand(0).getReg();
3897 Src2Reg
= MI
.getOperand(2).getReg();
3898 if (isDblRegForSubInst(Src2Reg
, HRI
) &&
3899 Hexagon::IntRegsRegClass
.contains(Src1Reg
) &&
3900 HRI
.getStackRegister() == Src1Reg
&& MI
.getOperand(1).isImm() &&
3901 isShiftedInt
<6,3>(MI
.getOperand(1).getImm()))
3902 return HexagonII::HSIG_S2
;
3904 case Hexagon::S4_storeiri_io
:
3905 // memw(Rs+#u4:2) = #U1
3906 Src1Reg
= MI
.getOperand(0).getReg();
3907 if (isIntRegForSubInst(Src1Reg
) && MI
.getOperand(1).isImm() &&
3908 isShiftedUInt
<4,2>(MI
.getOperand(1).getImm()) &&
3909 MI
.getOperand(2).isImm() && isUInt
<1>(MI
.getOperand(2).getImm()))
3910 return HexagonII::HSIG_S2
;
3912 case Hexagon::S4_storeirb_io
:
3913 // memb(Rs+#u4) = #U1
3914 Src1Reg
= MI
.getOperand(0).getReg();
3915 if (isIntRegForSubInst(Src1Reg
) &&
3916 MI
.getOperand(1).isImm() && isUInt
<4>(MI
.getOperand(1).getImm()) &&
3917 MI
.getOperand(2).isImm() && isUInt
<1>(MI
.getOperand(2).getImm()))
3918 return HexagonII::HSIG_S2
;
3920 case Hexagon::S2_allocframe
:
3921 if (MI
.getOperand(2).isImm() &&
3922 isShiftedUInt
<5,3>(MI
.getOperand(2).getImm()))
3923 return HexagonII::HSIG_S1
;
3932 // if ([!]P0[.new]) Rd = #0
3933 // Rd = add(r29,#u6:2)
3935 // P0 = cmp.eq(Rs,#u2)
3936 // Rdd = combine(#0,Rs)
3937 // Rdd = combine(Rs,#0)
3938 // Rdd = combine(#u2,#U2)
3941 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3943 case Hexagon::A2_addi
:
3944 DstReg
= MI
.getOperand(0).getReg();
3945 SrcReg
= MI
.getOperand(1).getReg();
3946 if (isIntRegForSubInst(DstReg
)) {
3947 // Rd = add(r29,#u6:2)
3948 if (Hexagon::IntRegsRegClass
.contains(SrcReg
) &&
3949 HRI
.getStackRegister() == SrcReg
&& MI
.getOperand(2).isImm() &&
3950 isShiftedUInt
<6,2>(MI
.getOperand(2).getImm()))
3951 return HexagonII::HSIG_A
;
3953 if ((DstReg
== SrcReg
) && MI
.getOperand(2).isImm() &&
3954 isInt
<7>(MI
.getOperand(2).getImm()))
3955 return HexagonII::HSIG_A
;
3958 if (isIntRegForSubInst(SrcReg
) && MI
.getOperand(2).isImm() &&
3959 ((MI
.getOperand(2).getImm() == 1) ||
3960 (MI
.getOperand(2).getImm() == -1)))
3961 return HexagonII::HSIG_A
;
3964 case Hexagon::A2_add
:
3966 DstReg
= MI
.getOperand(0).getReg();
3967 Src1Reg
= MI
.getOperand(1).getReg();
3968 Src2Reg
= MI
.getOperand(2).getReg();
3969 if (isIntRegForSubInst(DstReg
) && (DstReg
== Src1Reg
) &&
3970 isIntRegForSubInst(Src2Reg
))
3971 return HexagonII::HSIG_A
;
3973 case Hexagon::A2_andir
:
3975 // Rd16=and(Rs16,#255)
3976 // Rd16=and(Rs16,#1)
3977 DstReg
= MI
.getOperand(0).getReg();
3978 SrcReg
= MI
.getOperand(1).getReg();
3979 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
) &&
3980 MI
.getOperand(2).isImm() &&
3981 ((MI
.getOperand(2).getImm() == 1) ||
3982 (MI
.getOperand(2).getImm() == 255)))
3983 return HexagonII::HSIG_A
;
3985 case Hexagon::A2_tfr
:
3987 DstReg
= MI
.getOperand(0).getReg();
3988 SrcReg
= MI
.getOperand(1).getReg();
3989 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
))
3990 return HexagonII::HSIG_A
;
3992 case Hexagon::A2_tfrsi
:
3994 // Do not test for #u6 size since the const is getting extended
3995 // regardless and compound could be formed.
3997 DstReg
= MI
.getOperand(0).getReg();
3998 if (isIntRegForSubInst(DstReg
))
3999 return HexagonII::HSIG_A
;
4001 case Hexagon::C2_cmoveit
:
4002 case Hexagon::C2_cmovenewit
:
4003 case Hexagon::C2_cmoveif
:
4004 case Hexagon::C2_cmovenewif
:
4005 // if ([!]P0[.new]) Rd = #0
4007 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4008 DstReg
= MI
.getOperand(0).getReg();
4009 SrcReg
= MI
.getOperand(1).getReg();
4010 if (isIntRegForSubInst(DstReg
) &&
4011 Hexagon::PredRegsRegClass
.contains(SrcReg
) && Hexagon::P0
== SrcReg
&&
4012 MI
.getOperand(2).isImm() && MI
.getOperand(2).getImm() == 0)
4013 return HexagonII::HSIG_A
;
4015 case Hexagon::C2_cmpeqi
:
4016 // P0 = cmp.eq(Rs,#u2)
4017 DstReg
= MI
.getOperand(0).getReg();
4018 SrcReg
= MI
.getOperand(1).getReg();
4019 if (Hexagon::PredRegsRegClass
.contains(DstReg
) &&
4020 Hexagon::P0
== DstReg
&& isIntRegForSubInst(SrcReg
) &&
4021 MI
.getOperand(2).isImm() && isUInt
<2>(MI
.getOperand(2).getImm()))
4022 return HexagonII::HSIG_A
;
4024 case Hexagon::A2_combineii
:
4025 case Hexagon::A4_combineii
:
4026 // Rdd = combine(#u2,#U2)
4027 DstReg
= MI
.getOperand(0).getReg();
4028 if (isDblRegForSubInst(DstReg
, HRI
) &&
4029 ((MI
.getOperand(1).isImm() && isUInt
<2>(MI
.getOperand(1).getImm())) ||
4030 (MI
.getOperand(1).isGlobal() &&
4031 isUInt
<2>(MI
.getOperand(1).getOffset()))) &&
4032 ((MI
.getOperand(2).isImm() && isUInt
<2>(MI
.getOperand(2).getImm())) ||
4033 (MI
.getOperand(2).isGlobal() &&
4034 isUInt
<2>(MI
.getOperand(2).getOffset()))))
4035 return HexagonII::HSIG_A
;
4037 case Hexagon::A4_combineri
:
4038 // Rdd = combine(Rs,#0)
4039 DstReg
= MI
.getOperand(0).getReg();
4040 SrcReg
= MI
.getOperand(1).getReg();
4041 if (isDblRegForSubInst(DstReg
, HRI
) && isIntRegForSubInst(SrcReg
) &&
4042 ((MI
.getOperand(2).isImm() && MI
.getOperand(2).getImm() == 0) ||
4043 (MI
.getOperand(2).isGlobal() && MI
.getOperand(2).getOffset() == 0)))
4044 return HexagonII::HSIG_A
;
4046 case Hexagon::A4_combineir
:
4047 // Rdd = combine(#0,Rs)
4048 DstReg
= MI
.getOperand(0).getReg();
4049 SrcReg
= MI
.getOperand(2).getReg();
4050 if (isDblRegForSubInst(DstReg
, HRI
) && isIntRegForSubInst(SrcReg
) &&
4051 ((MI
.getOperand(1).isImm() && MI
.getOperand(1).getImm() == 0) ||
4052 (MI
.getOperand(1).isGlobal() && MI
.getOperand(1).getOffset() == 0)))
4053 return HexagonII::HSIG_A
;
4055 case Hexagon::A2_sxtb
:
4056 case Hexagon::A2_sxth
:
4057 case Hexagon::A2_zxtb
:
4058 case Hexagon::A2_zxth
:
4059 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4060 DstReg
= MI
.getOperand(0).getReg();
4061 SrcReg
= MI
.getOperand(1).getReg();
4062 if (isIntRegForSubInst(DstReg
) && isIntRegForSubInst(SrcReg
))
4063 return HexagonII::HSIG_A
;
4067 return HexagonII::HSIG_None
;
4070 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr
&MI
) const {
4071 return Hexagon::getRealHWInstr(MI
.getOpcode(), Hexagon::InstrType_Real
);
4074 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4075 const InstrItineraryData
*ItinData
, const MachineInstr
&MI
) const {
4076 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4077 // still have a MinLatency property, which getStageLatency checks.
4079 return getInstrLatency(ItinData
, MI
);
4081 if (MI
.isTransient())
4083 return ItinData
->getStageLatency(MI
.getDesc().getSchedClass());
4086 /// getOperandLatency - Compute and return the use operand latency of a given
4087 /// pair of def and use.
4088 /// In most cases, the static scheduling itinerary was enough to determine the
4089 /// operand latency. But it may not be possible for instructions with variable
4090 /// number of defs / uses.
4092 /// This is a raw interface to the itinerary that may be directly overriden by
4093 /// a target. Use computeOperandLatency to get the best estimate of latency.
4094 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData
*ItinData
,
4095 const MachineInstr
&DefMI
,
4097 const MachineInstr
&UseMI
,
4098 unsigned UseIdx
) const {
4099 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
4101 // Get DefIdx and UseIdx for super registers.
4102 const MachineOperand
&DefMO
= DefMI
.getOperand(DefIdx
);
4104 if (DefMO
.isReg() && Register::isPhysicalRegister(DefMO
.getReg())) {
4105 if (DefMO
.isImplicit()) {
4106 for (MCSuperRegIterator
SR(DefMO
.getReg(), &HRI
); SR
.isValid(); ++SR
) {
4107 int Idx
= DefMI
.findRegisterDefOperandIdx(*SR
, false, false, &HRI
);
4115 const MachineOperand
&UseMO
= UseMI
.getOperand(UseIdx
);
4116 if (UseMO
.isImplicit()) {
4117 for (MCSuperRegIterator
SR(UseMO
.getReg(), &HRI
); SR
.isValid(); ++SR
) {
4118 int Idx
= UseMI
.findRegisterUseOperandIdx(*SR
, false, &HRI
);
4127 int Latency
= TargetInstrInfo::getOperandLatency(ItinData
, DefMI
, DefIdx
,
4130 // We should never have 0 cycle latency between two instructions unless
4131 // they can be packetized together. However, this decision can't be made
4137 // inverts the predication logic.
4140 bool HexagonInstrInfo::getInvertedPredSense(
4141 SmallVectorImpl
<MachineOperand
> &Cond
) const {
4144 unsigned Opc
= getInvertedPredicatedOpcode(Cond
[0].getImm());
4145 Cond
[0].setImm(Opc
);
4149 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc
) const {
4151 InvPredOpcode
= isPredicatedTrue(Opc
) ? Hexagon::getFalsePredOpcode(Opc
)
4152 : Hexagon::getTruePredOpcode(Opc
);
4153 if (InvPredOpcode
>= 0) // Valid instruction with the inverted predicate.
4154 return InvPredOpcode
;
4156 llvm_unreachable("Unexpected predicated instruction");
4159 // Returns the max value that doesn't need to be extended.
4160 int HexagonInstrInfo::getMaxValue(const MachineInstr
&MI
) const {
4161 const uint64_t F
= MI
.getDesc().TSFlags
;
4162 unsigned isSigned
= (F
>> HexagonII::ExtentSignedPos
)
4163 & HexagonII::ExtentSignedMask
;
4164 unsigned bits
= (F
>> HexagonII::ExtentBitsPos
)
4165 & HexagonII::ExtentBitsMask
;
4167 if (isSigned
) // if value is signed
4168 return ~(-1U << (bits
- 1));
4170 return ~(-1U << bits
);
4174 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr
&MI
) const {
4175 switch (MI
.getOpcode()) {
4176 case Hexagon::L2_loadrbgp
:
4177 case Hexagon::L2_loadrdgp
:
4178 case Hexagon::L2_loadrhgp
:
4179 case Hexagon::L2_loadrigp
:
4180 case Hexagon::L2_loadrubgp
:
4181 case Hexagon::L2_loadruhgp
:
4182 case Hexagon::S2_storerbgp
:
4183 case Hexagon::S2_storerbnewgp
:
4184 case Hexagon::S2_storerhgp
:
4185 case Hexagon::S2_storerhnewgp
:
4186 case Hexagon::S2_storerigp
:
4187 case Hexagon::S2_storerinewgp
:
4188 case Hexagon::S2_storerdgp
:
4189 case Hexagon::S2_storerfgp
:
4192 const uint64_t F
= MI
.getDesc().TSFlags
;
4194 ((F
>> HexagonII::AddrModePos
) & HexagonII::AddrModeMask
);
4195 // Disallow any base+offset instruction. The assembler does not yet reorder
4196 // based up any zero offset instruction.
4197 return (addrMode
== HexagonII::BaseRegOffset
||
4198 addrMode
== HexagonII::BaseImmOffset
||
4199 addrMode
== HexagonII::BaseLongOffset
);
4202 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr
&MI
) const {
4203 using namespace HexagonII
;
4205 const uint64_t F
= MI
.getDesc().TSFlags
;
4206 unsigned S
= (F
>> MemAccessSizePos
) & MemAccesSizeMask
;
4207 unsigned Size
= getMemAccessSizeInBytes(MemAccessSize(S
));
4211 // Handle vector access sizes.
4212 const HexagonRegisterInfo
&HRI
= *Subtarget
.getRegisterInfo();
4214 case HexagonII::HVXVectorAccess
:
4215 return HRI
.getSpillSize(Hexagon::HvxVRRegClass
);
4217 llvm_unreachable("Unexpected instruction");
4221 // Returns the min value that doesn't need to be extended.
4222 int HexagonInstrInfo::getMinValue(const MachineInstr
&MI
) const {
4223 const uint64_t F
= MI
.getDesc().TSFlags
;
4224 unsigned isSigned
= (F
>> HexagonII::ExtentSignedPos
)
4225 & HexagonII::ExtentSignedMask
;
4226 unsigned bits
= (F
>> HexagonII::ExtentBitsPos
)
4227 & HexagonII::ExtentBitsMask
;
4229 if (isSigned
) // if value is signed
4230 return -1U << (bits
- 1);
4235 // Returns opcode of the non-extended equivalent instruction.
4236 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr
&MI
) const {
4237 // Check if the instruction has a register form that uses register in place
4238 // of the extended operand, if so return that as the non-extended form.
4239 short NonExtOpcode
= Hexagon::getRegForm(MI
.getOpcode());
4240 if (NonExtOpcode
>= 0)
4241 return NonExtOpcode
;
4243 if (MI
.getDesc().mayLoad() || MI
.getDesc().mayStore()) {
4244 // Check addressing mode and retrieve non-ext equivalent instruction.
4245 switch (getAddrMode(MI
)) {
4246 case HexagonII::Absolute
:
4247 return Hexagon::changeAddrMode_abs_io(MI
.getOpcode());
4248 case HexagonII::BaseImmOffset
:
4249 return Hexagon::changeAddrMode_io_rr(MI
.getOpcode());
4250 case HexagonII::BaseLongOffset
:
4251 return Hexagon::changeAddrMode_ur_rr(MI
.getOpcode());
4260 bool HexagonInstrInfo::getPredReg(ArrayRef
<MachineOperand
> Cond
,
4261 unsigned &PredReg
, unsigned &PredRegPos
, unsigned &PredRegFlags
) const {
4264 assert(Cond
.size() == 2);
4265 if (isNewValueJump(Cond
[0].getImm()) || Cond
[1].isMBB()) {
4266 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4269 PredReg
= Cond
[1].getReg();
4271 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4273 if (Cond
[1].isImplicit())
4274 PredRegFlags
= RegState::Implicit
;
4275 if (Cond
[1].isUndef())
4276 PredRegFlags
|= RegState::Undef
;
4280 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr
&MI
) const {
4281 return Hexagon::getRealHWInstr(MI
.getOpcode(), Hexagon::InstrType_Pseudo
);
4284 short HexagonInstrInfo::getRegForm(const MachineInstr
&MI
) const {
4285 return Hexagon::getRegForm(MI
.getOpcode());
4288 // Return the number of bytes required to encode the instruction.
4289 // Hexagon instructions are fixed length, 4 bytes, unless they
4290 // use a constant extender, which requires another 4 bytes.
4291 // For debug instructions and prolog labels, return 0.
4292 unsigned HexagonInstrInfo::getSize(const MachineInstr
&MI
) const {
4293 if (MI
.isDebugInstr() || MI
.isPosition())
4296 unsigned Size
= MI
.getDesc().getSize();
4298 // Assume the default insn size in case it cannot be determined
4299 // for whatever reason.
4300 Size
= HEXAGON_INSTR_SIZE
;
4302 if (isConstExtended(MI
) || isExtended(MI
))
4303 Size
+= HEXAGON_INSTR_SIZE
;
4305 // Try and compute number of instructions in asm.
4306 if (BranchRelaxAsmLarge
&& MI
.getOpcode() == Hexagon::INLINEASM
) {
4307 const MachineBasicBlock
&MBB
= *MI
.getParent();
4308 const MachineFunction
*MF
= MBB
.getParent();
4309 const MCAsmInfo
*MAI
= MF
->getTarget().getMCAsmInfo();
4311 // Count the number of register definitions to find the asm string.
4312 unsigned NumDefs
= 0;
4313 for (; MI
.getOperand(NumDefs
).isReg() && MI
.getOperand(NumDefs
).isDef();
4315 assert(NumDefs
!= MI
.getNumOperands()-2 && "No asm string?");
4317 assert(MI
.getOperand(NumDefs
).isSymbol() && "No asm string?");
4318 // Disassemble the AsmStr and approximate number of instructions.
4319 const char *AsmStr
= MI
.getOperand(NumDefs
).getSymbolName();
4320 Size
= getInlineAsmLength(AsmStr
, *MAI
);
4326 uint64_t HexagonInstrInfo::getType(const MachineInstr
&MI
) const {
4327 const uint64_t F
= MI
.getDesc().TSFlags
;
4328 return (F
>> HexagonII::TypePos
) & HexagonII::TypeMask
;
4331 unsigned HexagonInstrInfo::getUnits(const MachineInstr
&MI
) const {
4332 const InstrItineraryData
&II
= *Subtarget
.getInstrItineraryData();
4333 const InstrStage
&IS
= *II
.beginStage(MI
.getDesc().getSchedClass());
4335 return IS
.getUnits();
4338 // Calculate size of the basic block without debug instructions.
4339 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock
*BB
) const {
4340 return nonDbgMICount(BB
->instr_begin(), BB
->instr_end());
4343 unsigned HexagonInstrInfo::nonDbgBundleSize(
4344 MachineBasicBlock::const_iterator BundleHead
) const {
4345 assert(BundleHead
->isBundle() && "Not a bundle header");
4346 auto MII
= BundleHead
.getInstrIterator();
4347 // Skip the bundle header.
4348 return nonDbgMICount(++MII
, getBundleEnd(BundleHead
.getInstrIterator()));
4351 /// immediateExtend - Changes the instruction in place to one using an immediate
4353 void HexagonInstrInfo::immediateExtend(MachineInstr
&MI
) const {
4354 assert((isExtendable(MI
)||isConstExtended(MI
)) &&
4355 "Instruction must be extendable");
4356 // Find which operand is extendable.
4357 short ExtOpNum
= getCExtOpNum(MI
);
4358 MachineOperand
&MO
= MI
.getOperand(ExtOpNum
);
4359 // This needs to be something we understand.
4360 assert((MO
.isMBB() || MO
.isImm()) &&
4361 "Branch with unknown extendable field type");
4362 // Mark given operand as extended.
4363 MO
.addTargetFlag(HexagonII::HMOTF_ConstExtended
);
4366 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4367 MachineInstr
&MI
, MachineBasicBlock
*NewTarget
) const {
4368 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4369 << printMBBReference(*NewTarget
);
4371 assert(MI
.isBranch());
4372 unsigned NewOpcode
= getInvertedPredicatedOpcode(MI
.getOpcode());
4373 int TargetPos
= MI
.getNumOperands() - 1;
4374 // In general branch target is the last operand,
4375 // but some implicit defs added at the end might change it.
4376 while ((TargetPos
> -1) && !MI
.getOperand(TargetPos
).isMBB())
4378 assert((TargetPos
>= 0) && MI
.getOperand(TargetPos
).isMBB());
4379 MI
.getOperand(TargetPos
).setMBB(NewTarget
);
4380 if (EnableBranchPrediction
&& isPredicatedNew(MI
)) {
4381 NewOpcode
= reversePrediction(NewOpcode
);
4383 MI
.setDesc(get(NewOpcode
));
4387 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction
&MF
) const {
4388 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4389 MachineFunction::iterator A
= MF
.begin();
4390 MachineBasicBlock
&B
= *A
;
4391 MachineBasicBlock::iterator I
= B
.begin();
4392 DebugLoc DL
= I
->getDebugLoc();
4393 MachineInstr
*NewMI
;
4395 for (unsigned insn
= TargetOpcode::GENERIC_OP_END
+1;
4396 insn
< Hexagon::INSTRUCTION_LIST_END
; ++insn
) {
4397 NewMI
= BuildMI(B
, I
, DL
, get(insn
));
4398 LLVM_DEBUG(dbgs() << "\n"
4399 << getName(NewMI
->getOpcode())
4400 << " Class: " << NewMI
->getDesc().getSchedClass());
4401 NewMI
->eraseFromParent();
4403 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4406 // inverts the predication logic.
4409 bool HexagonInstrInfo::reversePredSense(MachineInstr
&MI
) const {
4410 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI
.dump());
4411 MI
.setDesc(get(getInvertedPredicatedOpcode(MI
.getOpcode())));
4415 // Reverse the branch prediction.
4416 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode
) const {
4417 int PredRevOpcode
= -1;
4418 if (isPredictedTaken(Opcode
))
4419 PredRevOpcode
= Hexagon::notTakenBranchPrediction(Opcode
);
4421 PredRevOpcode
= Hexagon::takenBranchPrediction(Opcode
);
4422 assert(PredRevOpcode
> 0);
4423 return PredRevOpcode
;
4426 // TODO: Add more rigorous validation.
4427 bool HexagonInstrInfo::validateBranchCond(const ArrayRef
<MachineOperand
> &Cond
)
4429 return Cond
.empty() || (Cond
[0].isImm() && (Cond
.size() != 1));
4432 void HexagonInstrInfo::
4433 setBundleNoShuf(MachineBasicBlock::instr_iterator MIB
) const {
4434 assert(MIB
->isBundle());
4435 MachineOperand
&Operand
= MIB
->getOperand(0);
4436 if (Operand
.isImm())
4437 Operand
.setImm(Operand
.getImm() | memShufDisabledMask
);
4439 MIB
->addOperand(MachineOperand::CreateImm(memShufDisabledMask
));
4442 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr
&MIB
) const {
4443 assert(MIB
.isBundle());
4444 const MachineOperand
&Operand
= MIB
.getOperand(0);
4445 return (Operand
.isImm() && (Operand
.getImm() & memShufDisabledMask
) != 0);
4448 // Addressing mode relations.
4449 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc
) const {
4450 return Opc
>= 0 ? Hexagon::changeAddrMode_abs_io(Opc
) : Opc
;
4453 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc
) const {
4454 return Opc
>= 0 ? Hexagon::changeAddrMode_io_abs(Opc
) : Opc
;
4457 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc
) const {
4458 return Opc
>= 0 ? Hexagon::changeAddrMode_io_pi(Opc
) : Opc
;
4461 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc
) const {
4462 return Opc
>= 0 ? Hexagon::changeAddrMode_io_rr(Opc
) : Opc
;
4465 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc
) const {
4466 return Opc
>= 0 ? Hexagon::changeAddrMode_pi_io(Opc
) : Opc
;
4469 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc
) const {
4470 return Opc
>= 0 ? Hexagon::changeAddrMode_rr_io(Opc
) : Opc
;
4473 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc
) const {
4474 return Opc
>= 0 ? Hexagon::changeAddrMode_rr_ur(Opc
) : Opc
;
4477 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc
) const {
4478 return Opc
>= 0 ? Hexagon::changeAddrMode_ur_rr(Opc
) : Opc
;