lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

   1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the RISCVMCCodeEmitter class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MCTargetDesc/RISCVFixupKinds.h"
  14 #include "MCTargetDesc/RISCVMCExpr.h"
  15 #include "MCTargetDesc/RISCVMCTargetDesc.h"
  16 #include "Utils/RISCVBaseInfo.h"
  17 #include "llvm/ADT/Statistic.h"
  18 #include "llvm/CodeGen/Register.h"
  19 #include "llvm/MC/MCAsmInfo.h"
  20 #include "llvm/MC/MCCodeEmitter.h"
  21 #include "llvm/MC/MCContext.h"
  22 #include "llvm/MC/MCExpr.h"
  23 #include "llvm/MC/MCInst.h"
  24 #include "llvm/MC/MCInstBuilder.h"
  25 #include "llvm/MC/MCInstrInfo.h"
  26 #include "llvm/MC/MCRegisterInfo.h"
  27 #include "llvm/MC/MCSymbol.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/EndianStream.h"
  30 #include "llvm/Support/raw_ostream.h"
  31
  32 using namespace llvm;
  33
  34 #define DEBUG_TYPE "mccodeemitter"
  35
  36 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
  37 STATISTIC(MCNumFixups, "Number of MC fixups created");
  38
  39 namespace {
  40 class RISCVMCCodeEmitter : public MCCodeEmitter {
  41   RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
  42   void operator=(const RISCVMCCodeEmitter &) = delete;
  43   MCContext &Ctx;
  44   MCInstrInfo const &MCII;
  45
  46 public:
  47   RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
  48       : Ctx(ctx), MCII(MCII) {}
  49
  50   ~RISCVMCCodeEmitter() override {}
  51
  52   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
  53                          SmallVectorImpl<MCFixup> &Fixups,
  54                          const MCSubtargetInfo &STI) const override;
  55
  56   void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
  57                           SmallVectorImpl<MCFixup> &Fixups,
  58                           const MCSubtargetInfo &STI) const;
  59
  60   void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
  61                       SmallVectorImpl<MCFixup> &Fixups,
  62                       const MCSubtargetInfo &STI) const;
  63
  64   /// TableGen'erated function for getting the binary encoding for an
  65   /// instruction.
  66   uint64_t getBinaryCodeForInstr(const MCInst &MI,
  67                                  SmallVectorImpl<MCFixup> &Fixups,
  68                                  const MCSubtargetInfo &STI) const;
  69
  70   /// Return binary encoding of operand. If the machine operand requires
  71   /// relocation, record the relocation and return zero.
  72   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
  73                              SmallVectorImpl<MCFixup> &Fixups,
  74                              const MCSubtargetInfo &STI) const;
  75
  76   unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
  77                              SmallVectorImpl<MCFixup> &Fixups,
  78                              const MCSubtargetInfo &STI) const;
  79
  80   unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
  81                          SmallVectorImpl<MCFixup> &Fixups,
  82                          const MCSubtargetInfo &STI) const;
  83 };
  84 } // end anonymous namespace
  85
  86 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
  87                                               const MCRegisterInfo &MRI,
  88                                               MCContext &Ctx) {
  89   return new RISCVMCCodeEmitter(Ctx, MCII);
  90 }
  91
  92 // Expand PseudoCALL(Reg) and PseudoTAIL to AUIPC and JALR with relocation
  93 // types. We expand PseudoCALL(Reg) and PseudoTAIL while encoding, meaning AUIPC
  94 // and JALR won't go through RISCV MC to MC compressed instruction
  95 // transformation. This is acceptable because AUIPC has no 16-bit form and
  96 // C_JALR have no immediate operand field.  We let linker relaxation deal with
  97 // it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL.
  98 // If C extension is enabled, JAL has chance relax to C_JAL.
  99 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
 100                                             SmallVectorImpl<MCFixup> &Fixups,
 101                                             const MCSubtargetInfo &STI) const {
 102   MCInst TmpInst;
 103   MCOperand Func;
 104   Register Ra;
 105   if (MI.getOpcode() == RISCV::PseudoTAIL) {
 106     Func = MI.getOperand(0);
 107     Ra = RISCV::X6;
 108   } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
 109     Func = MI.getOperand(1);
 110     Ra = MI.getOperand(0).getReg();
 111   } else {
 112     Func = MI.getOperand(0);
 113     Ra = RISCV::X1;
 114   }
 115   uint32_t Binary;
 116
 117   assert(Func.isExpr() && "Expected expression");
 118
 119   const MCExpr *CallExpr = Func.getExpr();
 120
 121   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
 122   TmpInst = MCInstBuilder(RISCV::AUIPC)
 123                 .addReg(Ra)
 124                 .addOperand(MCOperand::createExpr(CallExpr));
 125   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
 126   support::endian::write(OS, Binary, support::little);
 127
 128   if (MI.getOpcode() == RISCV::PseudoTAIL)
 129     // Emit JALR X0, X6, 0
 130     TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
 131   else
 132     // Emit JALR Ra, Ra, 0
 133     TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
 134   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
 135   support::endian::write(OS, Binary, support::little);
 136 }
 137
 138 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
 139 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
 140                                         SmallVectorImpl<MCFixup> &Fixups,
 141                                         const MCSubtargetInfo &STI) const {
 142   MCOperand DestReg = MI.getOperand(0);
 143   MCOperand SrcReg = MI.getOperand(1);
 144   MCOperand TPReg = MI.getOperand(2);
 145   assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
 146          "Expected thread pointer as second input to TP-relative add");
 147
 148   MCOperand SrcSymbol = MI.getOperand(3);
 149   assert(SrcSymbol.isExpr() &&
 150          "Expected expression as third input to TP-relative add");
 151
 152   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
 153   assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
 154          "Expected tprel_add relocation on TP-relative symbol");
 155
 156   // Emit the correct tprel_add relocation for the symbol.
 157   Fixups.push_back(MCFixup::create(
 158       0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
 159
 160   // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
 161   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
 162     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
 163     Fixups.push_back(MCFixup::create(
 164         0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
 165   }
 166
 167   // Emit a normal ADD instruction with the given operands.
 168   MCInst TmpInst = MCInstBuilder(RISCV::ADD)
 169                        .addOperand(DestReg)
 170                        .addOperand(SrcReg)
 171                        .addOperand(TPReg);
 172   uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
 173   support::endian::write(OS, Binary, support::little);
 174 }
 175
 176 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
 177                                            SmallVectorImpl<MCFixup> &Fixups,
 178                                            const MCSubtargetInfo &STI) const {
 179   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
 180   // Get byte count of instruction.
 181   unsigned Size = Desc.getSize();
 182
 183   if (MI.getOpcode() == RISCV::PseudoCALLReg ||
 184       MI.getOpcode() == RISCV::PseudoCALL ||
 185       MI.getOpcode() == RISCV::PseudoTAIL) {
 186     expandFunctionCall(MI, OS, Fixups, STI);
 187     MCNumEmitted += 2;
 188     return;
 189   }
 190
 191   if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
 192     expandAddTPRel(MI, OS, Fixups, STI);
 193     MCNumEmitted += 1;
 194     return;
 195   }
 196
 197   switch (Size) {
 198   default:
 199     llvm_unreachable("Unhandled encodeInstruction length!");
 200   case 2: {
 201     uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
 202     support::endian::write<uint16_t>(OS, Bits, support::little);
 203     break;
 204   }
 205   case 4: {
 206     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
 207     support::endian::write(OS, Bits, support::little);
 208     break;
 209   }
 210   }
 211
 212   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 213 }
 214
 215 unsigned
 216 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
 217                                       SmallVectorImpl<MCFixup> &Fixups,
 218                                       const MCSubtargetInfo &STI) const {
 219
 220   if (MO.isReg())
 221     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
 222
 223   if (MO.isImm())
 224     return static_cast<unsigned>(MO.getImm());
 225
 226   llvm_unreachable("Unhandled expression!");
 227   return 0;
 228 }
 229
 230 unsigned
 231 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
 232                                       SmallVectorImpl<MCFixup> &Fixups,
 233                                       const MCSubtargetInfo &STI) const {
 234   const MCOperand &MO = MI.getOperand(OpNo);
 235
 236   if (MO.isImm()) {
 237     unsigned Res = MO.getImm();
 238     assert((Res & 1) == 0 && "LSB is non-zero");
 239     return Res >> 1;
 240   }
 241
 242   return getImmOpValue(MI, OpNo, Fixups, STI);
 243 }
 244
 245 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
 246                                            SmallVectorImpl<MCFixup> &Fixups,
 247                                            const MCSubtargetInfo &STI) const {
 248   bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
 249   const MCOperand &MO = MI.getOperand(OpNo);
 250
 251   MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
 252   unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
 253
 254   // If the destination is an immediate, there is nothing to do.
 255   if (MO.isImm())
 256     return MO.getImm();
 257
 258   assert(MO.isExpr() &&
 259          "getImmOpValue expects only expressions or immediates");
 260   const MCExpr *Expr = MO.getExpr();
 261   MCExpr::ExprKind Kind = Expr->getKind();
 262   RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
 263   bool RelaxCandidate = false;
 264   if (Kind == MCExpr::Target) {
 265     const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
 266
 267     switch (RVExpr->getKind()) {
 268     case RISCVMCExpr::VK_RISCV_None:
 269     case RISCVMCExpr::VK_RISCV_Invalid:
 270     case RISCVMCExpr::VK_RISCV_32_PCREL:
 271       llvm_unreachable("Unhandled fixup kind!");
 272     case RISCVMCExpr::VK_RISCV_TPREL_ADD:
 273       // tprel_add is only used to indicate that a relocation should be emitted
 274       // for an add instruction used in TP-relative addressing. It should not be
 275       // expanded as if representing an actual instruction operand and so to
 276       // encounter it here is an error.
 277       llvm_unreachable(
 278           "VK_RISCV_TPREL_ADD should not represent an instruction operand");
 279     case RISCVMCExpr::VK_RISCV_LO:
 280       if (MIFrm == RISCVII::InstFormatI)
 281         FixupKind = RISCV::fixup_riscv_lo12_i;
 282       else if (MIFrm == RISCVII::InstFormatS)
 283         FixupKind = RISCV::fixup_riscv_lo12_s;
 284       else
 285         llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
 286       RelaxCandidate = true;
 287       break;
 288     case RISCVMCExpr::VK_RISCV_HI:
 289       FixupKind = RISCV::fixup_riscv_hi20;
 290       RelaxCandidate = true;
 291       break;
 292     case RISCVMCExpr::VK_RISCV_PCREL_LO:
 293       if (MIFrm == RISCVII::InstFormatI)
 294         FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
 295       else if (MIFrm == RISCVII::InstFormatS)
 296         FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
 297       else
 298         llvm_unreachable(
 299             "VK_RISCV_PCREL_LO used with unexpected instruction format");
 300       RelaxCandidate = true;
 301       break;
 302     case RISCVMCExpr::VK_RISCV_PCREL_HI:
 303       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
 304       RelaxCandidate = true;
 305       break;
 306     case RISCVMCExpr::VK_RISCV_GOT_HI:
 307       FixupKind = RISCV::fixup_riscv_got_hi20;
 308       break;
 309     case RISCVMCExpr::VK_RISCV_TPREL_LO:
 310       if (MIFrm == RISCVII::InstFormatI)
 311         FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
 312       else if (MIFrm == RISCVII::InstFormatS)
 313         FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
 314       else
 315         llvm_unreachable(
 316             "VK_RISCV_TPREL_LO used with unexpected instruction format");
 317       RelaxCandidate = true;
 318       break;
 319     case RISCVMCExpr::VK_RISCV_TPREL_HI:
 320       FixupKind = RISCV::fixup_riscv_tprel_hi20;
 321       RelaxCandidate = true;
 322       break;
 323     case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
 324       FixupKind = RISCV::fixup_riscv_tls_got_hi20;
 325       break;
 326     case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
 327       FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
 328       break;
 329     case RISCVMCExpr::VK_RISCV_CALL:
 330       FixupKind = RISCV::fixup_riscv_call;
 331       RelaxCandidate = true;
 332       break;
 333     case RISCVMCExpr::VK_RISCV_CALL_PLT:
 334       FixupKind = RISCV::fixup_riscv_call_plt;
 335       RelaxCandidate = true;
 336       break;
 337     }
 338   } else if (Kind == MCExpr::SymbolRef &&
 339              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
 340     if (Desc.getOpcode() == RISCV::JAL) {
 341       FixupKind = RISCV::fixup_riscv_jal;
 342     } else if (MIFrm == RISCVII::InstFormatB) {
 343       FixupKind = RISCV::fixup_riscv_branch;
 344     } else if (MIFrm == RISCVII::InstFormatCJ) {
 345       FixupKind = RISCV::fixup_riscv_rvc_jump;
 346     } else if (MIFrm == RISCVII::InstFormatCB) {
 347       FixupKind = RISCV::fixup_riscv_rvc_branch;
 348     }
 349   }
 350
 351   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
 352
 353   Fixups.push_back(
 354       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
 355   ++MCNumFixups;
 356
 357   // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
 358   // enabled and the current fixup will result in a relocation that may be
 359   // relaxed.
 360   if (EnableRelax && RelaxCandidate) {
 361     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
 362     Fixups.push_back(
 363     MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
 364                     MI.getLoc()));
 365     ++MCNumFixups;
 366   }
 367
 368   return 0;
 369 }
 370
 371 #include "RISCVGenMCCodeEmitter.inc"