1 // WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// WebAssembly Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // WebAssembly Instruction Predicate Definitions.
16 //===----------------------------------------------------------------------===//
18 def IsPIC : Predicate<"TM.isPositionIndependent()">;
19 def IsNotPIC : Predicate<"!TM.isPositionIndependent()">;
21 def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
23 def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
26 Predicate<"Subtarget->hasSIMD128()">,
27 AssemblerPredicate<"FeatureSIMD128", "simd128">;
29 def HasUnimplementedSIMD128 :
30 Predicate<"Subtarget->hasUnimplementedSIMD128()">,
31 AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">;
34 Predicate<"Subtarget->hasAtomics()">,
35 AssemblerPredicate<"FeatureAtomics", "atomics">;
38 Predicate<"Subtarget->hasMultivalue()">,
39 AssemblerPredicate<"FeatureMultivalue", "multivalue">;
41 def HasNontrappingFPToInt :
42 Predicate<"Subtarget->hasNontrappingFPToInt()">,
43 AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">;
45 def NotHasNontrappingFPToInt :
46 Predicate<"!Subtarget->hasNontrappingFPToInt()">,
47 AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">;
50 Predicate<"Subtarget->hasSignExt()">,
51 AssemblerPredicate<"FeatureSignExt", "sign-ext">;
54 Predicate<"Subtarget->hasTailCall()">,
55 AssemblerPredicate<"FeatureTailCall", "tail-call">;
57 def HasExceptionHandling :
58 Predicate<"Subtarget->hasExceptionHandling()">,
59 AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">;
62 Predicate<"Subtarget->hasBulkMemory()">,
63 AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">;
65 //===----------------------------------------------------------------------===//
66 // WebAssembly-specific DAG Node Types.
67 //===----------------------------------------------------------------------===//
69 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
71 def SDT_WebAssemblyCallSeqEnd :
72 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
73 def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
74 def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
75 def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
76 def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
77 def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
78 def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
80 def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
82 def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
84 //===----------------------------------------------------------------------===//
85 // WebAssembly-specific DAG Nodes.
86 //===----------------------------------------------------------------------===//
88 def WebAssemblycallseq_start :
89 SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
90 [SDNPHasChain, SDNPOutGlue]>;
91 def WebAssemblycallseq_end :
92 SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
93 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
94 def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
96 [SDNPHasChain, SDNPVariadic]>;
97 def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
99 [SDNPHasChain, SDNPVariadic]>;
100 def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL",
101 SDT_WebAssemblyCall0,
102 [SDNPHasChain, SDNPVariadic]>;
103 def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
104 SDT_WebAssemblyBrTable,
105 [SDNPHasChain, SDNPVariadic]>;
106 def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
107 SDT_WebAssemblyArgument>;
108 def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
109 SDT_WebAssemblyReturn, [SDNPHasChain]>;
110 def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
111 SDT_WebAssemblyWrapper>;
112 def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC",
113 SDT_WebAssemblyWrapperPIC>;
114 def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow,
115 [SDNPHasChain, SDNPVariadic]>;
117 //===----------------------------------------------------------------------===//
118 // WebAssembly-specific Operands.
119 //===----------------------------------------------------------------------===//
121 // Default Operand has AsmOperandClass "Imm" which is for integers (and
122 // symbols), so specialize one for floats:
123 def FPImmAsmOperand : AsmOperandClass {
125 let PredicateMethod = "isFPImm";
128 class FPOperand<ValueType ty> : Operand<ty> {
129 AsmOperandClass ParserMatchClass = FPImmAsmOperand;
132 let OperandNamespace = "WebAssembly" in {
134 let OperandType = "OPERAND_BASIC_BLOCK" in
135 def bb_op : Operand<OtherVT>;
137 let OperandType = "OPERAND_LOCAL" in
138 def local_op : Operand<i32>;
140 let OperandType = "OPERAND_GLOBAL" in
141 def global_op : Operand<i32>;
143 let OperandType = "OPERAND_I32IMM" in
144 def i32imm_op : Operand<i32>;
146 let OperandType = "OPERAND_I64IMM" in
147 def i64imm_op : Operand<i64>;
149 let OperandType = "OPERAND_F32IMM" in
150 def f32imm_op : FPOperand<f32>;
152 let OperandType = "OPERAND_F64IMM" in
153 def f64imm_op : FPOperand<f64>;
155 let OperandType = "OPERAND_VEC_I8IMM" in
156 def vec_i8imm_op : Operand<i32>;
158 let OperandType = "OPERAND_VEC_I16IMM" in
159 def vec_i16imm_op : Operand<i32>;
161 let OperandType = "OPERAND_VEC_I32IMM" in
162 def vec_i32imm_op : Operand<i32>;
164 let OperandType = "OPERAND_VEC_I64IMM" in
165 def vec_i64imm_op : Operand<i64>;
167 let OperandType = "OPERAND_FUNCTION32" in
168 def function32_op : Operand<i32>;
170 let OperandType = "OPERAND_OFFSET32" in
171 def offset32_op : Operand<i32>;
173 let OperandType = "OPERAND_P2ALIGN" in {
174 def P2Align : Operand<i32> {
175 let PrintMethod = "printWebAssemblyP2AlignOperand";
178 let OperandType = "OPERAND_EVENT" in
179 def event_op : Operand<i32>;
181 } // OperandType = "OPERAND_P2ALIGN"
183 let OperandType = "OPERAND_SIGNATURE" in
184 def Signature : Operand<i32> {
185 let PrintMethod = "printWebAssemblySignatureOperand";
188 let OperandType = "OPERAND_TYPEINDEX" in
189 def TypeIndex : Operand<i32>;
191 } // OperandNamespace = "WebAssembly"
193 //===----------------------------------------------------------------------===//
194 // WebAssembly Register to Stack instruction mapping
195 //===----------------------------------------------------------------------===//
198 def getStackOpcode : InstrMapping {
199 let FilterClass = "StackRel";
200 let RowFields = ["BaseName"];
201 let ColFields = ["StackBased"];
202 let KeyCol = ["false"];
203 let ValueCols = [["true"]];
206 //===----------------------------------------------------------------------===//
207 // WebAssembly Instruction Format Definitions.
208 //===----------------------------------------------------------------------===//
210 include "WebAssemblyInstrFormats.td"
212 //===----------------------------------------------------------------------===//
213 // Additional instructions.
214 //===----------------------------------------------------------------------===//
216 multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
217 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>,
218 Uses = [ARGUMENTS] in
220 I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
221 [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
223 defm "": ARGUMENT<I32, i32>;
224 defm "": ARGUMENT<I64, i64>;
225 defm "": ARGUMENT<F32, f32>;
226 defm "": ARGUMENT<F64, f64>;
227 defm "": ARGUMENT<EXNREF, exnref>;
229 // local.get and local.set are not generated by instruction selection; they
230 // are implied by virtual register uses and defs.
231 multiclass LOCAL<WebAssemblyRegClass vt> {
232 let hasSideEffects = 0 in {
233 // COPY is not an actual instruction in wasm, but since we allow local.get and
234 // local.set to be implicit during most of codegen, we can have a COPY which
235 // is actually a no-op because all the work is done in the implied local.get
236 // and local.set. COPYs are eliminated (and replaced with
237 // local.get/local.set) in the ExplicitLocals pass.
238 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
239 defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [],
240 "local.copy\t$res, $src", "local.copy">;
242 // TEE is similar to COPY, but writes two copies of its result. Typically
243 // this would be used to stackify one result and write the other result to a
245 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
246 defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [],
247 "local.tee\t$res, $also, $src", "local.tee">;
249 // This is the actual local.get instruction in wasm. These are made explicit
250 // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm
251 // local, which is a side effect not otherwise modeled in LLVM.
252 let mayLoad = 1, isAsCheapAsAMove = 1 in
253 defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local),
254 (outs), (ins local_op:$local), [],
255 "local.get\t$res, $local", "local.get\t$local", 0x20>;
257 // This is the actual local.set instruction in wasm. These are made explicit
258 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm
259 // local, which is a side effect not otherwise modeled in LLVM.
260 let mayStore = 1, isAsCheapAsAMove = 1 in
261 defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src),
262 (outs), (ins local_op:$local), [],
263 "local.set\t$local, $src", "local.set\t$local", 0x21>;
265 // This is the actual local.tee instruction in wasm. TEEs are turned into
266 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason
268 let mayStore = 1, isAsCheapAsAMove = 1 in
269 defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src),
270 (outs), (ins local_op:$local), [],
271 "local.tee\t$res, $local, $src", "local.tee\t$local",
274 // Unused values must be dropped in some contexts.
275 defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [],
276 "drop\t$src", "drop", 0x1a>;
279 defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local),
280 (outs), (ins global_op:$local), [],
281 "global.get\t$res, $local", "global.get\t$local",
285 defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src),
286 (outs), (ins global_op:$local), [],
287 "global.set\t$local, $src", "global.set\t$local",
290 } // hasSideEffects = 0
292 defm "" : LOCAL<I32>;
293 defm "" : LOCAL<I64>;
294 defm "" : LOCAL<F32>;
295 defm "" : LOCAL<F64>;
296 defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
297 defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>;
299 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
300 defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
301 (outs), (ins i32imm_op:$imm),
302 [(set I32:$res, imm:$imm)],
303 "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>;
304 defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
305 (outs), (ins i64imm_op:$imm),
306 [(set I64:$res, imm:$imm)],
307 "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>;
308 defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
309 (outs), (ins f32imm_op:$imm),
310 [(set F32:$res, fpimm:$imm)],
311 "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>;
312 defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
313 (outs), (ins f64imm_op:$imm),
314 [(set F64:$res, fpimm:$imm)],
315 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>;
316 } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
318 def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
319 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>;
321 def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
322 (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
324 def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)),
325 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>;
327 def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
328 (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>;
330 def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
331 (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>;
333 def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>;
334 def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>;
336 //===----------------------------------------------------------------------===//
337 // Additional sets of instructions.
338 //===----------------------------------------------------------------------===//
340 include "WebAssemblyInstrMemory.td"
341 include "WebAssemblyInstrCall.td"
342 include "WebAssemblyInstrControl.td"
343 include "WebAssemblyInstrInteger.td"
344 include "WebAssemblyInstrConv.td"
345 include "WebAssemblyInstrFloat.td"
346 include "WebAssemblyInstrAtomics.td"
347 include "WebAssemblyInstrSIMD.td"
348 include "WebAssemblyInstrRef.td"
349 include "WebAssemblyInstrBulkMemory.td"