lib/Target/X86/X86CallLowering.cpp

   1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// This file implements the lowering of LLVM calls to machine code calls for
  11 /// GlobalISel.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86CallLowering.h"
  16 #include "X86CallingConv.h"
  17 #include "X86ISelLowering.h"
  18 #include "X86InstrInfo.h"
  19 #include "X86RegisterInfo.h"
  20 #include "X86Subtarget.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/ADT/SmallVector.h"
  23 #include "llvm/CodeGen/Analysis.h"
  24 #include "llvm/CodeGen/CallingConvLower.h"
  25 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  26 #include "llvm/CodeGen/GlobalISel/Utils.h"
  27 #include "llvm/CodeGen/LowLevelType.h"
  28 #include "llvm/CodeGen/MachineBasicBlock.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineFunction.h"
  31 #include "llvm/CodeGen/MachineInstrBuilder.h"
  32 #include "llvm/CodeGen/MachineMemOperand.h"
  33 #include "llvm/CodeGen/MachineOperand.h"
  34 #include "llvm/CodeGen/MachineRegisterInfo.h"
  35 #include "llvm/CodeGen/TargetInstrInfo.h"
  36 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  37 #include "llvm/CodeGen/ValueTypes.h"
  38 #include "llvm/IR/Attributes.h"
  39 #include "llvm/IR/DataLayout.h"
  40 #include "llvm/IR/Function.h"
  41 #include "llvm/IR/Value.h"
  42 #include "llvm/MC/MCRegisterInfo.h"
  43 #include "llvm/Support/LowLevelTypeImpl.h"
  44 #include "llvm/Support/MachineValueType.h"
  45 #include <cassert>
  46 #include <cstdint>
  47
  48 using namespace llvm;
  49
  50 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
  51     : CallLowering(&TLI) {}
  52
  53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
  54                                         SmallVectorImpl<ArgInfo> &SplitArgs,
  55                                         const DataLayout &DL,
  56                                         MachineRegisterInfo &MRI,
  57                                         SplitArgTy PerformArgSplit) const {
  58   const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
  59   LLVMContext &Context = OrigArg.Ty->getContext();
  60
  61   SmallVector<EVT, 4> SplitVTs;
  62   SmallVector<uint64_t, 4> Offsets;
  63   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
  64   assert(OrigArg.Regs.size() == 1 && "Can't handle multple regs yet");
  65
  66   if (OrigArg.Ty->isVoidTy())
  67     return true;
  68
  69   EVT VT = SplitVTs[0];
  70   unsigned NumParts = TLI.getNumRegisters(Context, VT);
  71
  72   if (NumParts == 1) {
  73     // replace the original type ( pointer -> GPR ).
  74     SplitArgs.emplace_back(OrigArg.Regs[0], VT.getTypeForEVT(Context),
  75                            OrigArg.Flags, OrigArg.IsFixed);
  76     return true;
  77   }
  78
  79   SmallVector<Register, 8> SplitRegs;
  80
  81   EVT PartVT = TLI.getRegisterType(Context, VT);
  82   Type *PartTy = PartVT.getTypeForEVT(Context);
  83
  84   for (unsigned i = 0; i < NumParts; ++i) {
  85     ArgInfo Info =
  86         ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
  87                 PartTy, OrigArg.Flags};
  88     SplitArgs.push_back(Info);
  89     SplitRegs.push_back(Info.Regs[0]);
  90   }
  91
  92   PerformArgSplit(SplitRegs);
  93   return true;
  94 }
  95
  96 namespace {
  97
  98 struct OutgoingValueHandler : public CallLowering::ValueHandler {
  99   OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 100                        MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
 101       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
 102         DL(MIRBuilder.getMF().getDataLayout()),
 103         STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
 104
 105   Register getStackAddress(uint64_t Size, int64_t Offset,
 106                            MachinePointerInfo &MPO) override {
 107     LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
 108     LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
 109     Register SPReg = MRI.createGenericVirtualRegister(p0);
 110     MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
 111
 112     Register OffsetReg = MRI.createGenericVirtualRegister(SType);
 113     MIRBuilder.buildConstant(OffsetReg, Offset);
 114
 115     Register AddrReg = MRI.createGenericVirtualRegister(p0);
 116     MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
 117
 118     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
 119     return AddrReg;
 120   }
 121
 122   void assignValueToReg(Register ValVReg, Register PhysReg,
 123                         CCValAssign &VA) override {
 124     MIB.addUse(PhysReg, RegState::Implicit);
 125
 126     Register ExtReg;
 127     // If we are copying the value to a physical register with the
 128     // size larger than the size of the value itself - build AnyExt
 129     // to the size of the register first and only then do the copy.
 130     // The example of that would be copying from s32 to xmm0, for which
 131     // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
 132     // we expect normal extendRegister mechanism to work.
 133     unsigned PhysRegSize =
 134         MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
 135     unsigned ValSize = VA.getValVT().getSizeInBits();
 136     unsigned LocSize = VA.getLocVT().getSizeInBits();
 137     if (PhysRegSize > ValSize && LocSize == ValSize) {
 138       assert((PhysRegSize == 128 || PhysRegSize == 80)  && "We expect that to be 128 bit");
 139       auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
 140       ExtReg = MIB->getOperand(0).getReg();
 141     } else
 142       ExtReg = extendRegister(ValVReg, VA);
 143
 144     MIRBuilder.buildCopy(PhysReg, ExtReg);
 145   }
 146
 147   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
 148                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 149     Register ExtReg = extendRegister(ValVReg, VA);
 150     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 151         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
 152         /* Alignment */ 1);
 153     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
 154   }
 155
 156   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
 157                  CCValAssign::LocInfo LocInfo,
 158                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
 159                  CCState &State) override {
 160     bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
 161     StackSize = State.getNextStackOffset();
 162
 163     static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
 164                                            X86::XMM3, X86::XMM4, X86::XMM5,
 165                                            X86::XMM6, X86::XMM7};
 166     if (!Info.IsFixed)
 167       NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
 168
 169     return Res;
 170   }
 171
 172   uint64_t getStackSize() { return StackSize; }
 173   uint64_t getNumXmmRegs() { return NumXMMRegs; }
 174
 175 protected:
 176   MachineInstrBuilder &MIB;
 177   uint64_t StackSize = 0;
 178   const DataLayout &DL;
 179   const X86Subtarget &STI;
 180   unsigned NumXMMRegs = 0;
 181 };
 182
 183 } // end anonymous namespace
 184
 185 bool X86CallLowering::lowerReturn(
 186     MachineIRBuilder &MIRBuilder, const Value *Val,
 187     ArrayRef<Register> VRegs) const {
 188   assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
 189          "Return value without a vreg");
 190   auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
 191
 192   if (!VRegs.empty()) {
 193     MachineFunction &MF = MIRBuilder.getMF();
 194     const Function &F = MF.getFunction();
 195     MachineRegisterInfo &MRI = MF.getRegInfo();
 196     auto &DL = MF.getDataLayout();
 197     LLVMContext &Ctx = Val->getType()->getContext();
 198     const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
 199
 200     SmallVector<EVT, 4> SplitEVTs;
 201     ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
 202     assert(VRegs.size() == SplitEVTs.size() &&
 203            "For each split Type there should be exactly one VReg.");
 204
 205     SmallVector<ArgInfo, 8> SplitArgs;
 206     for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
 207       ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
 208       setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
 209       if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
 210                              [&](ArrayRef<Register> Regs) {
 211                                MIRBuilder.buildUnmerge(Regs, VRegs[i]);
 212                              }))
 213         return false;
 214     }
 215
 216     OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
 217     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 218       return false;
 219   }
 220
 221   MIRBuilder.insertInstr(MIB);
 222   return true;
 223 }
 224
 225 namespace {
 226
 227 struct IncomingValueHandler : public CallLowering::ValueHandler {
 228   IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 229                        CCAssignFn *AssignFn)
 230       : ValueHandler(MIRBuilder, MRI, AssignFn),
 231         DL(MIRBuilder.getMF().getDataLayout()) {}
 232
 233   bool isIncomingArgumentHandler() const override { return true; }
 234
 235   Register getStackAddress(uint64_t Size, int64_t Offset,
 236                            MachinePointerInfo &MPO) override {
 237     auto &MFI = MIRBuilder.getMF().getFrameInfo();
 238     int FI = MFI.CreateFixedObject(Size, Offset, true);
 239     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
 240
 241     Register AddrReg = MRI.createGenericVirtualRegister(
 242         LLT::pointer(0, DL.getPointerSizeInBits(0)));
 243     MIRBuilder.buildFrameIndex(AddrReg, FI);
 244     return AddrReg;
 245   }
 246
 247   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
 248                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 249     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 250         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
 251         1);
 252     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
 253   }
 254
 255   void assignValueToReg(Register ValVReg, Register PhysReg,
 256                         CCValAssign &VA) override {
 257     markPhysRegUsed(PhysReg);
 258
 259     switch (VA.getLocInfo()) {
 260     default: {
 261       // If we are copying the value from a physical register with the
 262       // size larger than the size of the value itself - build the copy
 263       // of the phys reg first and then build the truncation of that copy.
 264       // The example of that would be copying from xmm0 to s32, for which
 265       // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
 266       // we expect this to be handled in SExt/ZExt/AExt case.
 267       unsigned PhysRegSize =
 268           MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
 269       unsigned ValSize = VA.getValVT().getSizeInBits();
 270       unsigned LocSize = VA.getLocVT().getSizeInBits();
 271       if (PhysRegSize > ValSize && LocSize == ValSize) {
 272         auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
 273         MIRBuilder.buildTrunc(ValVReg, Copy);
 274         return;
 275       }
 276
 277       MIRBuilder.buildCopy(ValVReg, PhysReg);
 278       break;
 279     }
 280     case CCValAssign::LocInfo::SExt:
 281     case CCValAssign::LocInfo::ZExt:
 282     case CCValAssign::LocInfo::AExt: {
 283       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
 284       MIRBuilder.buildTrunc(ValVReg, Copy);
 285       break;
 286     }
 287     }
 288   }
 289
 290   /// How the physical register gets marked varies between formal
 291   /// parameters (it's a basic-block live-in), and a call instruction
 292   /// (it's an implicit-def of the BL).
 293   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
 294
 295 protected:
 296   const DataLayout &DL;
 297 };
 298
 299 struct FormalArgHandler : public IncomingValueHandler {
 300   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 301                    CCAssignFn *AssignFn)
 302       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
 303
 304   void markPhysRegUsed(unsigned PhysReg) override {
 305     MIRBuilder.getMRI()->addLiveIn(PhysReg);
 306     MIRBuilder.getMBB().addLiveIn(PhysReg);
 307   }
 308 };
 309
 310 struct CallReturnHandler : public IncomingValueHandler {
 311   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 312                     CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
 313       : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
 314
 315   void markPhysRegUsed(unsigned PhysReg) override {
 316     MIB.addDef(PhysReg, RegState::Implicit);
 317   }
 318
 319 protected:
 320   MachineInstrBuilder &MIB;
 321 };
 322
 323 } // end anonymous namespace
 324
 325 bool X86CallLowering::lowerFormalArguments(
 326     MachineIRBuilder &MIRBuilder, const Function &F,
 327     ArrayRef<ArrayRef<Register>> VRegs) const {
 328   if (F.arg_empty())
 329     return true;
 330
 331   // TODO: handle variadic function
 332   if (F.isVarArg())
 333     return false;
 334
 335   MachineFunction &MF = MIRBuilder.getMF();
 336   MachineRegisterInfo &MRI = MF.getRegInfo();
 337   auto DL = MF.getDataLayout();
 338
 339   SmallVector<ArgInfo, 8> SplitArgs;
 340   unsigned Idx = 0;
 341   for (auto &Arg : F.args()) {
 342
 343     // TODO: handle not simple cases.
 344     if (Arg.hasAttribute(Attribute::ByVal) ||
 345         Arg.hasAttribute(Attribute::InReg) ||
 346         Arg.hasAttribute(Attribute::StructRet) ||
 347         Arg.hasAttribute(Attribute::SwiftSelf) ||
 348         Arg.hasAttribute(Attribute::SwiftError) ||
 349         Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
 350       return false;
 351
 352     ArgInfo OrigArg(VRegs[Idx], Arg.getType());
 353     setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
 354     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
 355                            [&](ArrayRef<Register> Regs) {
 356                              MIRBuilder.buildMerge(VRegs[Idx][0], Regs);
 357                            }))
 358       return false;
 359     Idx++;
 360   }
 361
 362   MachineBasicBlock &MBB = MIRBuilder.getMBB();
 363   if (!MBB.empty())
 364     MIRBuilder.setInstr(*MBB.begin());
 365
 366   FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
 367   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 368     return false;
 369
 370   // Move back to the end of the basic block.
 371   MIRBuilder.setMBB(MBB);
 372
 373   return true;
 374 }
 375
 376 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 377                                 CallLoweringInfo &Info) const {
 378   MachineFunction &MF = MIRBuilder.getMF();
 379   const Function &F = MF.getFunction();
 380   MachineRegisterInfo &MRI = MF.getRegInfo();
 381   auto &DL = F.getParent()->getDataLayout();
 382   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
 383   const TargetInstrInfo &TII = *STI.getInstrInfo();
 384   auto TRI = STI.getRegisterInfo();
 385
 386   // Handle only Linux C, X86_64_SysV calling conventions for now.
 387   if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
 388                                 Info.CallConv == CallingConv::X86_64_SysV))
 389     return false;
 390
 391   unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
 392   auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
 393
 394   // Create a temporarily-floating call instruction so we can add the implicit
 395   // uses of arg registers.
 396   bool Is64Bit = STI.is64Bit();
 397   unsigned CallOpc = Info.Callee.isReg()
 398                          ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
 399                          : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
 400
 401   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
 402                  .add(Info.Callee)
 403                  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
 404
 405   SmallVector<ArgInfo, 8> SplitArgs;
 406   for (const auto &OrigArg : Info.OrigArgs) {
 407
 408     // TODO: handle not simple cases.
 409     if (OrigArg.Flags[0].isByVal())
 410       return false;
 411
 412     if (OrigArg.Regs.size() > 1)
 413       return false;
 414
 415     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
 416                            [&](ArrayRef<Register> Regs) {
 417                              MIRBuilder.buildUnmerge(Regs, OrigArg.Regs[0]);
 418                            }))
 419       return false;
 420   }
 421   // Do the actual argument marshalling.
 422   OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
 423   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 424     return false;
 425
 426   bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
 427   if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(Info.CallConv)) {
 428     // From AMD64 ABI document:
 429     // For calls that may call functions that use varargs or stdargs
 430     // (prototype-less calls or calls to functions containing ellipsis (...) in
 431     // the declaration) %al is used as hidden argument to specify the number
 432     // of SSE registers used. The contents of %al do not need to match exactly
 433     // the number of registers, but must be an ubound on the number of SSE
 434     // registers used and is in the range 0 - 8 inclusive.
 435
 436     MIRBuilder.buildInstr(X86::MOV8ri)
 437         .addDef(X86::AL)
 438         .addImm(Handler.getNumXmmRegs());
 439     MIB.addUse(X86::AL, RegState::Implicit);
 440   }
 441
 442   // Now we can add the actual call instruction to the correct basic block.
 443   MIRBuilder.insertInstr(MIB);
 444
 445   // If Callee is a reg, since it is used by a target specific
 446   // instruction, it must have a register class matching the
 447   // constraint of that instruction.
 448   if (Info.Callee.isReg())
 449     MIB->getOperand(0).setReg(constrainOperandRegClass(
 450         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
 451         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
 452         0));
 453
 454   // Finally we can copy the returned value back into its virtual-register. In
 455   // symmetry with the arguments, the physical register must be an
 456   // implicit-define of the call instruction.
 457
 458   if (!Info.OrigRet.Ty->isVoidTy()) {
 459     if (Info.OrigRet.Regs.size() > 1)
 460       return false;
 461
 462     SplitArgs.clear();
 463     SmallVector<Register, 8> NewRegs;
 464
 465     if (!splitToValueTypes(Info.OrigRet, SplitArgs, DL, MRI,
 466                            [&](ArrayRef<Register> Regs) {
 467                              NewRegs.assign(Regs.begin(), Regs.end());
 468                            }))
 469       return false;
 470
 471     CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
 472     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 473       return false;
 474
 475     if (!NewRegs.empty())
 476       MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
 477   }
 478
 479   CallSeqStart.addImm(Handler.getStackSize())
 480       .addImm(0 /* see getFrameTotalSize */)
 481       .addImm(0 /* see getFrameAdjustment */);
 482
 483   unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
 484   MIRBuilder.buildInstr(AdjStackUp)
 485       .addImm(Handler.getStackSize())
 486       .addImm(0 /* NumBytesForCalleeToPop */);
 487
 488   return true;
 489 }