1 //===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the instructions that make up the Intel TSX instruction
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
17 def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
18 [SDNPHasChain, SDNPSideEffect]>;
20 let SchedRW = [WriteSystem] in {
22 let usesCustomInserter = 1 in
23 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
24 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
27 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
28 def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst),
29 "xbegin\t$dst", []>, OpSize16;
30 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst),
31 "xbegin\t$dst", []>, OpSize32;
34 // Psuedo instruction to fake the definition of EAX on the fallback code path.
35 let isPseudo = 1, Defs = [EAX] in {
36 def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
39 def XEND : I<0x01, MRM_D5, (outs), (ins),
40 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
42 let Defs = [EFLAGS] in
43 def XTEST : I<0x01, MRM_D6, (outs), (ins),
44 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>;
46 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
48 [(int_x86_xabort timm:$imm)]>, Requires<[HasRTM]>;
52 let SchedRW = [WriteSystem] in {
54 let isAsmParserOnly = 1 in {
55 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>;
56 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>;