| blob | a8c65435ab9bcc6fe715c38aaebfc5ade4580664 |
1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the machine model for Skylake Server to support
10 // instruction scheduling and other instruction cost heuristics.
11 //
12 //===----------------------------------------------------------------------===//
14 def SkylakeServerModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and SKylake can
16 // decode 6 instructions per cycle.
17 let IssueWidth = 6;
18 let MicroOpBufferSize = 224; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 14;
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
27 let CompleteModel = 0;
28 }
30 let SchedModel = SkylakeServerModel in {
32 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
34 // Ports 0, 1, 5, and 6 handle all computation.
35 // Port 4 gets the data half of stores. Store data can be available later than
36 // the store address, but since we don't model the latency of stores, we can
37 // ignore that.
38 // Ports 2 and 3 are identical. They handle loads and the address half of
39 // stores. Port 7 can handle address calculations.
40 def SKXPort0 : ProcResource<1>;
41 def SKXPort1 : ProcResource<1>;
42 def SKXPort2 : ProcResource<1>;
43 def SKXPort3 : ProcResource<1>;
44 def SKXPort4 : ProcResource<1>;
45 def SKXPort5 : ProcResource<1>;
46 def SKXPort6 : ProcResource<1>;
47 def SKXPort7 : ProcResource<1>;
49 // Many micro-ops are capable of issuing on multiple ports.
50 def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;
51 def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;
52 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
53 def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;
54 def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;
55 def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;
56 def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;
57 def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;
58 def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;
59 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
60 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
61 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
63 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
64 // FP division and sqrt on port 0.
65 def SKXFPDivider : ProcResource<1>;
67 // 60 Entry Unified Scheduler
68 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
69 SKXPort5, SKXPort6, SKXPort7]> {
70 let BufferSize=60;
71 }
73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 5>;
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
79 def : ReadAdvance<ReadAfterVecLd, 5>;
80 def : ReadAdvance<ReadAfterVecXLd, 6>;
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
83 def : ReadAdvance<ReadInt2Fpu, 0>;
85 // Many SchedWrites are defined in pairs with and without a folded load.
86 // Instructions with folded loads are usually micro-fused, so they only appear
87 // as two micro-ops when queued in the reservation station.
88 // This multiclass defines the resource usage for variants with and without
89 // folded loads.
90 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
91 list<ProcResourceKind> ExePorts,
92 int Lat, list<int> Res = [1], int UOps = 1,
93 int LoadLat = 5> {
94 // Register variant is using a single cycle on ExePort.
95 def : WriteRes<SchedRW, ExePorts> {
96 let Latency = Lat;
97 let ResourceCycles = Res;
98 let NumMicroOps = UOps;
99 }
101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102 // the latency (default = 5).
103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
104 let Latency = !add(Lat, LoadLat);
105 let ResourceCycles = !listconcat([1], Res);
106 let NumMicroOps = !add(UOps, 1);
107 }
108 }
110 // A folded store needs a cycle on port 4 for the store data, and an extra port
111 // 2/3/7 cycle to recompute the address.
112 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
114 // Arithmetic.
115 defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
116 defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
118 // Integer multiplication.
119 defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>;
120 defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>;
121 defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>;
122 defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
123 defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>;
124 defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>;
125 defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>;
126 defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>;
127 defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>;
128 defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>;
129 defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>;
130 defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>;
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
133 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
134 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
135 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
136 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
137 defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
139 // TODO: Why isn't the SKXDivider used?
140 defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
141 defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
142 defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
143 defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
144 defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
145 defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
146 defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>;
148 defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>;
149 defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
150 defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
151 defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>;
152 defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
153 defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
154 defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
155 defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>;
157 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
159 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
161 defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.
162 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
163 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
164 def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
165 let Latency = 2;
166 let NumMicroOps = 3;
167 }
168 defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
169 defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
170 defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
171 defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
172 defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
173 defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>;
174 defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
176 // Integer shifts and rotates.
177 defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
178 defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>;
179 defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>;
180 defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>;
182 // SHLD/SHRD.
183 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
184 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
185 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
186 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
188 // Bit counts.
189 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
190 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
191 defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
192 defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
193 defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
195 // BMI1 BEXTR/BLS, BMI2 BZHI
196 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
197 defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;
198 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
200 // Loads, stores, and moves, not folded with other operations.
201 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
202 defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;
203 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
204 defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;
206 // Idioms that clear a register, like xorps %xmm0, %xmm0.
207 // These can often bypass execution ports completely.
208 def : WriteRes<WriteZero, []>;
210 // Branches don't produce values, so they have no latency, but they still
211 // consume resources. Indirect branches can fold loads.
212 defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;
214 // Floating point. This covers both scalar and vector operations.
215 defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;
216 defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;
217 defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;
218 defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;
219 defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;
220 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
221 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
222 defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
223 defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
224 defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
225 defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
226 defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
227 defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
228 defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
230 defm : X86WriteRes<WriteFMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>;
231 defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
232 defm : X86WriteRes<WriteFMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>;
233 defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>;
235 defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;
236 defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;
237 defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;
238 defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
240 defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.
241 defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;
242 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
243 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
244 defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.
245 defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;
246 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
247 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
249 defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.
250 defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;
251 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
252 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
253 defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.
254 defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;
255 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
256 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
258 defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
260 defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.
261 defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;
262 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
263 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
264 defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.
265 defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;
266 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
267 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
269 defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
270 //defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
271 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
272 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
273 //defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
274 //defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
275 //defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
276 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
278 defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
279 defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
280 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
281 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
282 defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
283 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
284 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
285 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
286 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
288 defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
289 defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;
290 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
291 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
293 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
294 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;
295 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
296 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
298 defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.
299 defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;
300 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
301 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
302 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.
303 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
304 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
305 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
306 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
307 defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
308 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
309 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
310 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
311 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
312 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
313 defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
314 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
315 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
316 defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
317 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
318 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
319 defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
320 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
321 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
322 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
323 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
324 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
325 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
326 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
327 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
329 // FMA Scheduling helper class.
330 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
332 // Vector integer operations.
333 defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;
334 defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;
335 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
336 defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>;
337 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>;
338 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
339 defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
340 defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
341 defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
342 defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
343 defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
344 defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
345 defm : X86WriteRes<WriteVecMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>;
346 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
347 defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;
348 defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;
349 defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;
350 defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;
351 defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;
353 defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
354 defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;
355 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
356 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
357 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
358 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
359 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
360 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
361 defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
362 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
363 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
364 defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 4, [1], 1, 5>; // Vector integer multiply.
365 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 4, [1], 1, 6>;
366 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 4, [1], 1, 7>;
367 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 4, [1], 1, 7>;
368 defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
369 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
370 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
371 defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
372 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
373 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
374 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
375 defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
376 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
377 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
378 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
379 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
380 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
381 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
382 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
383 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
384 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;
385 defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
386 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
387 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
388 defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
389 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
390 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
391 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
392 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
394 // Vector integer shifts.
395 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
396 defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;
397 defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;
398 defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;
399 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
400 defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;
401 defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;
403 defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;
404 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
405 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
406 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
407 defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
408 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
409 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
411 // Vector insert/extract operations.
412 def : WriteRes<WriteVecInsert, [SKXPort5]> {
413 let Latency = 2;
414 let NumMicroOps = 2;
415 let ResourceCycles = [2];
416 }
417 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
418 let Latency = 6;
419 let NumMicroOps = 2;
420 }
421 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
423 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
424 let Latency = 3;
425 let NumMicroOps = 2;
426 }
427 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
428 let Latency = 2;
429 let NumMicroOps = 3;
430 }
432 // Conversion between integer and float.
433 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
434 defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;
435 defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;
436 defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;
437 defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;
438 defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;
439 defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;
440 defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;
442 defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;
443 defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;
444 defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;
445 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
446 defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;
447 defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;
448 defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;
449 defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;
451 defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;
452 defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;
453 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
454 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
455 defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>;
456 defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>;
457 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
458 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
460 defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;
461 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
462 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
463 defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;
464 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
465 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
467 defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;
468 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
469 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
470 defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
471 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
472 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
474 // Strings instructions.
476 // Packed Compare Implicit Length Strings, Return Mask
477 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
478 let Latency = 10;
479 let NumMicroOps = 3;
480 let ResourceCycles = [3];
481 }
482 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
483 let Latency = 16;
484 let NumMicroOps = 4;
485 let ResourceCycles = [3,1];
486 }
488 // Packed Compare Explicit Length Strings, Return Mask
489 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
490 let Latency = 19;
491 let NumMicroOps = 9;
492 let ResourceCycles = [4,3,1,1];
493 }
494 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
495 let Latency = 25;
496 let NumMicroOps = 10;
497 let ResourceCycles = [4,3,1,1,1];
498 }
500 // Packed Compare Implicit Length Strings, Return Index
501 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
502 let Latency = 10;
503 let NumMicroOps = 3;
504 let ResourceCycles = [3];
505 }
506 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
507 let Latency = 16;
508 let NumMicroOps = 4;
509 let ResourceCycles = [3,1];
510 }
512 // Packed Compare Explicit Length Strings, Return Index
513 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
514 let Latency = 18;
515 let NumMicroOps = 8;
516 let ResourceCycles = [4,3,1];
517 }
518 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
519 let Latency = 24;
520 let NumMicroOps = 9;
521 let ResourceCycles = [4,3,1,1];
522 }
524 // MOVMSK Instructions.
525 def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
526 def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
527 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
528 def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
530 // AES instructions.
531 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
532 let Latency = 4;
533 let NumMicroOps = 1;
534 let ResourceCycles = [1];
535 }
536 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
537 let Latency = 10;
538 let NumMicroOps = 2;
539 let ResourceCycles = [1,1];
540 }
542 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
543 let Latency = 8;
544 let NumMicroOps = 2;
545 let ResourceCycles = [2];
546 }
547 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
548 let Latency = 14;
549 let NumMicroOps = 3;
550 let ResourceCycles = [2,1];
551 }
553 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
554 let Latency = 20;
555 let NumMicroOps = 11;
556 let ResourceCycles = [3,6,2];
557 }
558 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
559 let Latency = 25;
560 let NumMicroOps = 11;
561 let ResourceCycles = [3,6,1,1];
562 }
564 // Carry-less multiplication instructions.
565 def : WriteRes<WriteCLMul, [SKXPort5]> {
566 let Latency = 6;
567 let NumMicroOps = 1;
568 let ResourceCycles = [1];
569 }
570 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
571 let Latency = 12;
572 let NumMicroOps = 2;
573 let ResourceCycles = [1,1];
574 }
576 // Catch-all for expensive system instructions.
577 def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
579 // AVX2.
580 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
581 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
582 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
583 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
585 // Old microcoded instructions that nobody use.
586 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
588 // Fence instructions.
589 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
591 // Load/store MXCSR.
592 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
593 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
595 // Nop, not very useful expect it provides a model for nops!
596 def : WriteRes<WriteNop, []>;
598 ////////////////////////////////////////////////////////////////////////////////
599 // Horizontal add/sub instructions.
600 ////////////////////////////////////////////////////////////////////////////////
602 defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
603 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
604 defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;
605 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
606 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
608 // Remaining instrs.
610 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
611 let Latency = 1;
612 let NumMicroOps = 1;
613 let ResourceCycles = [1];
614 }
615 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
616 "KANDN(B|D|Q|W)rr",
617 "KMOV(B|D|Q|W)kk",
618 "KNOT(B|D|Q|W)rr",
619 "KOR(B|D|Q|W)rr",
620 "KXNOR(B|D|Q|W)rr",
621 "KXOR(B|D|Q|W)rr",
622 "MMX_PADDS(B|W)irr",
623 "MMX_PADDUS(B|W)irr",
624 "MMX_PAVG(B|W)irr",
625 "MMX_PCMPEQ(B|D|W)irr",
626 "MMX_PCMPGT(B|D|W)irr",
627 "MMX_P(MAX|MIN)SWirr",
628 "MMX_P(MAX|MIN)UBirr",
629 "MMX_PSUBS(B|W)irr",
630 "MMX_PSUBUS(B|W)irr",
631 "VPMOVB2M(Z|Z128|Z256)rr",
632 "VPMOVD2M(Z|Z128|Z256)rr",
633 "VPMOVQ2M(Z|Z128|Z256)rr",
634 "VPMOVW2M(Z|Z128|Z256)rr")>;
636 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
637 let Latency = 1;
638 let NumMicroOps = 1;
639 let ResourceCycles = [1];
640 }
641 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
642 "KMOV(B|D|Q|W)kr",
643 "UCOM_F(P?)r")>;
645 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
646 let Latency = 1;
647 let NumMicroOps = 1;
648 let ResourceCycles = [1];
649 }
650 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
652 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
653 let Latency = 1;
654 let NumMicroOps = 1;
655 let ResourceCycles = [1];
656 }
657 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
659 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
660 let Latency = 1;
661 let NumMicroOps = 1;
662 let ResourceCycles = [1];
663 }
664 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
666 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
667 let Latency = 1;
668 let NumMicroOps = 1;
669 let ResourceCycles = [1];
670 }
671 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
673 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
674 let Latency = 1;
675 let NumMicroOps = 1;
676 let ResourceCycles = [1];
677 }
678 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
679 "VBLENDMPS(Z128|Z256)rr",
680 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
681 "(V?)PADD(B|D|Q|W)rr",
682 "VPBLENDD(Y?)rri",
683 "VPBLENDMB(Z128|Z256)rr",
684 "VPBLENDMD(Z128|Z256)rr",
685 "VPBLENDMQ(Z128|Z256)rr",
686 "VPBLENDMW(Z128|Z256)rr",
687 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
688 "VPTERNLOGD(Z|Z128|Z256)rri",
689 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
691 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
692 let Latency = 1;
693 let NumMicroOps = 1;
694 let ResourceCycles = [1];
695 }
696 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
697 CMC, STC,
698 SGDT64m,
699 SIDT64m,
700 SMSW16m,
701 STRm,
702 SYSCALL)>;
704 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
705 let Latency = 1;
706 let NumMicroOps = 2;
707 let ResourceCycles = [1,1];
708 }
709 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
710 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
711 "ST_FP(32|64|80)m")>;
713 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
714 let Latency = 2;
715 let NumMicroOps = 2;
716 let ResourceCycles = [2];
717 }
718 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
720 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
721 let Latency = 2;
722 let NumMicroOps = 2;
723 let ResourceCycles = [2];
724 }
725 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
726 MMX_MOVDQ2Qrr)>;
728 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
729 let Latency = 2;
730 let NumMicroOps = 2;
731 let ResourceCycles = [2];
732 }
733 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
734 WAIT,
735 XGETBV)>;
737 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
738 let Latency = 2;
739 let NumMicroOps = 2;
740 let ResourceCycles = [1,1];
741 }
742 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
744 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
745 let Latency = 2;
746 let NumMicroOps = 2;
747 let ResourceCycles = [1,1];
748 }
749 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
751 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
752 let Latency = 2;
753 let NumMicroOps = 2;
754 let ResourceCycles = [1,1];
755 }
756 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
757 JCXZ, JECXZ, JRCXZ,
758 ADC8i8, SBB8i8,
759 ADC16i16, SBB16i16,
760 ADC32i32, SBB32i32,
761 ADC64i32, SBB64i32)>;
763 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
764 let Latency = 2;
765 let NumMicroOps = 3;
766 let ResourceCycles = [1,1,1];
767 }
768 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
770 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
771 let Latency = 2;
772 let NumMicroOps = 3;
773 let ResourceCycles = [1,1,1];
774 }
775 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
777 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
778 let Latency = 2;
779 let NumMicroOps = 3;
780 let ResourceCycles = [1,1,1];
781 }
782 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
783 STOSB, STOSL, STOSQ, STOSW)>;
784 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
786 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
787 let Latency = 2;
788 let NumMicroOps = 5;
789 let ResourceCycles = [2,2,1];
790 }
791 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
793 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
794 let Latency = 3;
795 let NumMicroOps = 1;
796 let ResourceCycles = [1];
797 }
798 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
799 "KORTEST(B|D|Q|W)rr",
800 "KTEST(B|D|Q|W)rr")>;
802 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
803 let Latency = 3;
804 let NumMicroOps = 1;
805 let ResourceCycles = [1];
806 }
807 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
808 "PEXT(32|64)rr")>;
810 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
811 let Latency = 3;
812 let NumMicroOps = 1;
813 let ResourceCycles = [1];
814 }
815 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
816 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
817 "KADD(B|D|Q|W)rr",
818 "KSHIFTL(B|D|Q|W)ri",
819 "KSHIFTR(B|D|Q|W)ri",
820 "KUNPCK(BW|DQ|WD)rr",
821 "VALIGND(Z|Z128|Z256)rri",
822 "VALIGNQ(Z|Z128|Z256)rri",
823 "VCMPPD(Z|Z128|Z256)rri",
824 "VCMPPS(Z|Z128|Z256)rri",
825 "VCMP(SD|SS)Zrr",
826 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
827 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
828 "VFPCLASS(SD|SS)Zrr",
829 "VPBROADCAST(B|W)rr",
830 "VPCMPB(Z|Z128|Z256)rri",
831 "VPCMPD(Z|Z128|Z256)rri",
832 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
833 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
834 "VPCMPQ(Z|Z128|Z256)rri",
835 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
836 "VPCMPW(Z|Z128|Z256)rri",
837 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
838 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
840 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
841 let Latency = 3;
842 let NumMicroOps = 2;
843 let ResourceCycles = [1,1];
844 }
845 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
847 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
848 let Latency = 3;
849 let NumMicroOps = 3;
850 let ResourceCycles = [1,2];
851 }
852 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
854 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
855 let Latency = 3;
856 let NumMicroOps = 3;
857 let ResourceCycles = [2,1];
858 }
859 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
861 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
862 let Latency = 3;
863 let NumMicroOps = 3;
864 let ResourceCycles = [2,1];
865 }
866 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
867 MMX_PACKSSWBirr,
868 MMX_PACKUSWBirr)>;
870 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
871 let Latency = 3;
872 let NumMicroOps = 3;
873 let ResourceCycles = [1,2];
874 }
875 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
877 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
878 let Latency = 3;
879 let NumMicroOps = 3;
880 let ResourceCycles = [1,2];
881 }
882 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
884 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
885 let Latency = 3;
886 let NumMicroOps = 3;
887 let ResourceCycles = [1,2];
888 }
889 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
890 "RCR(8|16|32|64)r(1|i)")>;
892 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
893 let Latency = 3;
894 let NumMicroOps = 3;
895 let ResourceCycles = [1,1,1];
896 }
897 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
899 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
900 let Latency = 3;
901 let NumMicroOps = 4;
902 let ResourceCycles = [1,1,1,1];
903 }
904 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
906 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
907 let Latency = 3;
908 let NumMicroOps = 4;
909 let ResourceCycles = [1,1,1,1];
910 }
911 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
913 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
914 let Latency = 4;
915 let NumMicroOps = 1;
916 let ResourceCycles = [1];
917 }
918 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
920 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
921 let Latency = 4;
922 let NumMicroOps = 1;
923 let ResourceCycles = [1];
924 }
925 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
926 "(V?)CVTDQ2PSrr",
927 "VCVTPD2QQ(Z128|Z256)rr",
928 "VCVTPD2UQQ(Z128|Z256)rr",
929 "VCVTPS2DQ(Y|Z128|Z256)rr",
930 "(V?)CVTPS2DQrr",
931 "VCVTPS2UDQ(Z128|Z256)rr",
932 "VCVTQQ2PD(Z128|Z256)rr",
933 "VCVTTPD2QQ(Z128|Z256)rr",
934 "VCVTTPD2UQQ(Z128|Z256)rr",
935 "VCVTTPS2DQ(Z128|Z256)rr",
936 "(V?)CVTTPS2DQrr",
937 "VCVTTPS2UDQ(Z128|Z256)rr",
938 "VCVTUDQ2PS(Z128|Z256)rr",
939 "VCVTUQQ2PD(Z128|Z256)rr")>;
941 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
942 let Latency = 4;
943 let NumMicroOps = 1;
944 let ResourceCycles = [1];
945 }
946 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
947 VCVTPD2QQZrr,
948 VCVTPD2UQQZrr,
949 VCVTPS2DQZrr,
950 VCVTPS2UDQZrr,
951 VCVTQQ2PDZrr,
952 VCVTTPD2QQZrr,
953 VCVTTPD2UQQZrr,
954 VCVTTPS2DQZrr,
955 VCVTTPS2UDQZrr,
956 VCVTUDQ2PSZrr,
957 VCVTUQQ2PDZrr)>;
959 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
960 let Latency = 4;
961 let NumMicroOps = 2;
962 let ResourceCycles = [2];
963 }
964 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
965 "VEXPANDPS(Z|Z128|Z256)rr",
966 "VPEXPANDD(Z|Z128|Z256)rr",
967 "VPEXPANDQ(Z|Z128|Z256)rr",
968 "VPMOVDB(Z|Z128|Z256)rr",
969 "VPMOVDW(Z|Z128|Z256)rr",
970 "VPMOVQB(Z|Z128|Z256)rr",
971 "VPMOVQW(Z|Z128|Z256)rr",
972 "VPMOVSDB(Z|Z128|Z256)rr",
973 "VPMOVSDW(Z|Z128|Z256)rr",
974 "VPMOVSQB(Z|Z128|Z256)rr",
975 "VPMOVSQD(Z|Z128|Z256)rr",
976 "VPMOVSQW(Z|Z128|Z256)rr",
977 "VPMOVSWB(Z|Z128|Z256)rr",
978 "VPMOVUSDB(Z|Z128|Z256)rr",
979 "VPMOVUSDW(Z|Z128|Z256)rr",
980 "VPMOVUSQB(Z|Z128|Z256)rr",
981 "VPMOVUSQD(Z|Z128|Z256)rr",
982 "VPMOVUSWB(Z|Z128|Z256)rr",
983 "VPMOVWB(Z|Z128|Z256)rr")>;
985 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
986 let Latency = 4;
987 let NumMicroOps = 3;
988 let ResourceCycles = [1,1,1];
989 }
990 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
991 "IST_F(16|32)m",
992 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
994 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
995 let Latency = 4;
996 let NumMicroOps = 4;
997 let ResourceCycles = [4];
998 }
999 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1001 def SKXWriteResGroup56 : SchedWriteRes<[]> {
1002 let Latency = 0;
1003 let NumMicroOps = 4;
1004 let ResourceCycles = [];
1005 }
1006 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1008 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1009 let Latency = 4;
1010 let NumMicroOps = 4;
1011 let ResourceCycles = [1,1,2];
1012 }
1013 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1015 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1016 let Latency = 5;
1017 let NumMicroOps = 1;
1018 let ResourceCycles = [1];
1019 }
1020 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1021 "MOVZX(16|32|64)rm(8|16)",
1022 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71?
1024 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1025 let Latency = 5;
1026 let NumMicroOps = 2;
1027 let ResourceCycles = [1,1];
1028 }
1029 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1030 "MMX_CVT(T?)PS2PIirr",
1031 "VCVTDQ2PDZ128rr",
1032 "VCVTPD2DQZ128rr",
1033 "(V?)CVT(T?)PD2DQrr",
1034 "VCVTPD2PSZ128rr",
1035 "(V?)CVTPD2PSrr",
1036 "VCVTPD2UDQZ128rr",
1037 "VCVTPS2PDZ128rr",
1038 "(V?)CVTPS2PDrr",
1039 "VCVTPS2QQZ128rr",
1040 "VCVTPS2UQQZ128rr",
1041 "VCVTQQ2PSZ128rr",
1042 "(V?)CVTSD2SS(Z?)rr",
1043 "(V?)CVTSI(64)?2SDrr",
1044 "VCVTSI2SSZrr",
1045 "(V?)CVTSI2SSrr",
1046 "VCVTSI(64)?2SDZrr",
1047 "VCVTSS2SDZrr",
1048 "(V?)CVTSS2SDrr",
1049 "VCVTTPD2DQZ128rr",
1050 "VCVTTPD2UDQZ128rr",
1051 "VCVTTPS2QQZ128rr",
1052 "VCVTTPS2UQQZ128rr",
1053 "VCVTUDQ2PDZ128rr",
1054 "VCVTUQQ2PSZ128rr",
1055 "VCVTUSI2SSZrr",
1056 "VCVTUSI(64)?2SDZrr")>;
1058 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1059 let Latency = 5;
1060 let NumMicroOps = 3;
1061 let ResourceCycles = [2,1];
1062 }
1063 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1065 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1066 let Latency = 5;
1067 let NumMicroOps = 3;
1068 let ResourceCycles = [1,1,1];
1069 }
1070 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1072 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1073 let Latency = 5;
1074 let NumMicroOps = 3;
1075 let ResourceCycles = [1,1,1];
1076 }
1077 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1078 "VCVTPS2PHZ256mr(b?)",
1079 "VCVTPS2PHZmr(b?)")>;
1081 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1082 let Latency = 5;
1083 let NumMicroOps = 4;
1084 let ResourceCycles = [1,2,1];
1085 }
1086 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1087 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1088 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1089 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1090 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1091 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1092 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1093 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1094 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1095 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1096 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1097 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1098 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1099 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1100 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1101 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1102 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1104 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1105 let Latency = 5;
1106 let NumMicroOps = 5;
1107 let ResourceCycles = [1,4];
1108 }
1109 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1111 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1112 let Latency = 5;
1113 let NumMicroOps = 6;
1114 let ResourceCycles = [1,1,4];
1115 }
1116 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1118 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1119 let Latency = 6;
1120 let NumMicroOps = 1;
1121 let ResourceCycles = [1];
1122 }
1123 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1124 VPBROADCASTDrm,
1125 VPBROADCASTQrm,
1126 VMOVSHDUPrm,
1127 VMOVSLDUPrm,
1128 MOVSHDUPrm,
1129 MOVSLDUPrm)>;
1131 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1132 let Latency = 6;
1133 let NumMicroOps = 2;
1134 let ResourceCycles = [2];
1135 }
1136 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1137 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1138 "VCOMPRESSPS(Z|Z128|Z256)rr",
1139 "VPCOMPRESSD(Z|Z128|Z256)rr",
1140 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1141 "VPERMW(Z|Z128|Z256)rr")>;
1143 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1144 let Latency = 6;
1145 let NumMicroOps = 2;
1146 let ResourceCycles = [1,1];
1147 }
1148 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1149 MMX_PADDSWirm,
1150 MMX_PADDUSBirm,
1151 MMX_PADDUSWirm,
1152 MMX_PAVGBirm,
1153 MMX_PAVGWirm,
1154 MMX_PCMPEQBirm,
1155 MMX_PCMPEQDirm,
1156 MMX_PCMPEQWirm,
1157 MMX_PCMPGTBirm,
1158 MMX_PCMPGTDirm,
1159 MMX_PCMPGTWirm,
1160 MMX_PMAXSWirm,
1161 MMX_PMAXUBirm,
1162 MMX_PMINSWirm,
1163 MMX_PMINUBirm,
1164 MMX_PSUBSBirm,
1165 MMX_PSUBSWirm,
1166 MMX_PSUBUSBirm,
1167 MMX_PSUBUSWirm)>;
1169 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1170 let Latency = 6;
1171 let NumMicroOps = 2;
1172 let ResourceCycles = [1,1];
1173 }
1174 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
1175 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1177 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1178 let Latency = 6;
1179 let NumMicroOps = 2;
1180 let ResourceCycles = [1,1];
1181 }
1182 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1183 "MOVBE(16|32|64)rm")>;
1185 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1186 let Latency = 6;
1187 let NumMicroOps = 2;
1188 let ResourceCycles = [1,1];
1189 }
1190 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1191 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1193 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1194 let Latency = 6;
1195 let NumMicroOps = 2;
1196 let ResourceCycles = [1,1];
1197 }
1198 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1199 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1201 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1202 let Latency = 6;
1203 let NumMicroOps = 3;
1204 let ResourceCycles = [2,1];
1205 }
1206 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1207 "VCVTSI642SSZrr",
1208 "VCVTUSI642SSZrr")>;
1210 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1211 let Latency = 6;
1212 let NumMicroOps = 4;
1213 let ResourceCycles = [1,1,1,1];
1214 }
1215 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1217 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1218 let Latency = 6;
1219 let NumMicroOps = 4;
1220 let ResourceCycles = [1,1,1,1];
1221 }
1222 def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)",
1223 "SHL(8|16|32|64)m(1|i)",
1224 "SHR(8|16|32|64)m(1|i)")>;
1226 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1227 let Latency = 6;
1228 let NumMicroOps = 4;
1229 let ResourceCycles = [1,1,1,1];
1230 }
1231 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1232 "PUSH(16|32|64)rmm")>;
1234 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1235 let Latency = 6;
1236 let NumMicroOps = 6;
1237 let ResourceCycles = [1,5];
1238 }
1239 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1241 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1242 let Latency = 7;
1243 let NumMicroOps = 1;
1244 let ResourceCycles = [1];
1245 }
1246 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1247 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1248 VBROADCASTI128,
1249 VBROADCASTSDYrm,
1250 VBROADCASTSSYrm,
1251 VMOVDDUPYrm,
1252 VMOVSHDUPYrm,
1253 VMOVSLDUPYrm,
1254 VPBROADCASTDYrm,
1255 VPBROADCASTQYrm)>;
1257 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1258 let Latency = 7;
1259 let NumMicroOps = 2;
1260 let ResourceCycles = [1,1];
1261 }
1262 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1264 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1265 let Latency = 7;
1266 let NumMicroOps = 2;
1267 let ResourceCycles = [1,1];
1268 }
1269 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1270 "VMOVSSZrm(b?)")>;
1272 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1273 let Latency = 6;
1274 let NumMicroOps = 2;
1275 let ResourceCycles = [1,1];
1276 }
1277 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1278 "(V?)PMOV(SX|ZX)BQrm",
1279 "(V?)PMOV(SX|ZX)BWrm",
1280 "(V?)PMOV(SX|ZX)DQrm",
1281 "(V?)PMOV(SX|ZX)WDrm",
1282 "(V?)PMOV(SX|ZX)WQrm")>;
1284 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1285 let Latency = 7;
1286 let NumMicroOps = 2;
1287 let ResourceCycles = [1,1];
1288 }
1289 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1290 "VCVTPD2DQ(Y|Z256)rr",
1291 "VCVTPD2PS(Y|Z256)rr",
1292 "VCVTPD2UDQZ256rr",
1293 "VCVTPS2PD(Y|Z256)rr",
1294 "VCVTPS2QQZ256rr",
1295 "VCVTPS2UQQZ256rr",
1296 "VCVTQQ2PSZ256rr",
1297 "VCVTTPD2DQ(Y|Z256)rr",
1298 "VCVTTPD2UDQZ256rr",
1299 "VCVTTPS2QQZ256rr",
1300 "VCVTTPS2UQQZ256rr",
1301 "VCVTUDQ2PDZ256rr",
1302 "VCVTUQQ2PSZ256rr")>;
1304 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1305 let Latency = 7;
1306 let NumMicroOps = 2;
1307 let ResourceCycles = [1,1];
1308 }
1309 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1310 VCVTPD2DQZrr,
1311 VCVTPD2PSZrr,
1312 VCVTPD2UDQZrr,
1313 VCVTPS2PDZrr,
1314 VCVTPS2QQZrr,
1315 VCVTPS2UQQZrr,
1316 VCVTQQ2PSZrr,
1317 VCVTTPD2DQZrr,
1318 VCVTTPD2UDQZrr,
1319 VCVTTPS2QQZrr,
1320 VCVTTPS2UQQZrr,
1321 VCVTUDQ2PDZrr,
1322 VCVTUQQ2PSZrr)>;
1324 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1325 let Latency = 7;
1326 let NumMicroOps = 2;
1327 let ResourceCycles = [1,1];
1328 }
1329 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1330 VPBLENDDrmi)>;
1331 def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd],
1332 (instregex "VBLENDMPDZ128rm(b?)",
1333 "VBLENDMPSZ128rm(b?)",
1334 "VBROADCASTI32X2Z128m(b?)",
1335 "VBROADCASTSSZ128m(b?)",
1336 "VINSERT(F|I)128rm",
1337 "VMOVAPDZ128rm(b?)",
1338 "VMOVAPSZ128rm(b?)",
1339 "VMOVDDUPZ128rm(b?)",
1340 "VMOVDQA32Z128rm(b?)",
1341 "VMOVDQA64Z128rm(b?)",
1342 "VMOVDQU16Z128rm(b?)",
1343 "VMOVDQU32Z128rm(b?)",
1344 "VMOVDQU64Z128rm(b?)",
1345 "VMOVDQU8Z128rm(b?)",
1346 "VMOVSHDUPZ128rm(b?)",
1347 "VMOVSLDUPZ128rm(b?)",
1348 "VMOVUPDZ128rm(b?)",
1349 "VMOVUPSZ128rm(b?)",
1350 "VPADD(B|D|Q|W)Z128rm(b?)",
1351 "(V?)PADD(B|D|Q|W)rm",
1352 "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1353 "VPBROADCASTDZ128m(b?)",
1354 "VPBROADCASTQZ128m(b?)",
1355 "VPSUB(B|D|Q|W)Z128rm(b?)",
1356 "(V?)PSUB(B|D|Q|W)rm",
1357 "VPTERNLOGDZ128rm(b?)i",
1358 "VPTERNLOGQZ128rm(b?)i")>;
1360 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1361 let Latency = 7;
1362 let NumMicroOps = 3;
1363 let ResourceCycles = [2,1];
1364 }
1365 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1366 MMX_PACKSSWBirm,
1367 MMX_PACKUSWBirm)>;
1369 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1370 let Latency = 7;
1371 let NumMicroOps = 3;
1372 let ResourceCycles = [2,1];
1373 }
1374 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1375 "VPERMI2W256rr",
1376 "VPERMI2Wrr",
1377 "VPERMT2W128rr",
1378 "VPERMT2W256rr",
1379 "VPERMT2Wrr")>;
1381 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1382 let Latency = 7;
1383 let NumMicroOps = 3;
1384 let ResourceCycles = [1,2];
1385 }
1386 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1387 SCASB, SCASL, SCASQ, SCASW)>;
1389 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1390 let Latency = 7;
1391 let NumMicroOps = 3;
1392 let ResourceCycles = [1,1,1];
1393 }
1394 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1395 "(V?)CVTSS2SI64(Z?)rr",
1396 "(V?)CVTTSS2SI64(Z?)rr",
1397 "VCVTTSS2USI64Zrr")>;
1399 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1400 let Latency = 7;
1401 let NumMicroOps = 3;
1402 let ResourceCycles = [1,1,1];
1403 }
1404 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1406 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1407 let Latency = 7;
1408 let NumMicroOps = 3;
1409 let ResourceCycles = [1,1,1];
1410 }
1411 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1413 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1414 let Latency = 7;
1415 let NumMicroOps = 3;
1416 let ResourceCycles = [1,1,1];
1417 }
1418 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1420 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1421 let Latency = 7;
1422 let NumMicroOps = 4;
1423 let ResourceCycles = [1,2,1];
1424 }
1425 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1426 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1427 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1428 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1430 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1431 let Latency = 7;
1432 let NumMicroOps = 5;
1433 let ResourceCycles = [1,1,1,2];
1434 }
1435 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1436 "ROR(8|16|32|64)m(1|i)")>;
1438 def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> {
1439 let Latency = 2;
1440 let NumMicroOps = 2;
1441 let ResourceCycles = [2];
1442 }
1443 def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1444 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1446 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1447 let Latency = 7;
1448 let NumMicroOps = 5;
1449 let ResourceCycles = [1,1,1,2];
1450 }
1451 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1453 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1454 let Latency = 7;
1455 let NumMicroOps = 5;
1456 let ResourceCycles = [1,1,1,1,1];
1457 }
1458 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1459 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64)>;
1461 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1462 let Latency = 7;
1463 let NumMicroOps = 7;
1464 let ResourceCycles = [1,2,2,2];
1465 }
1466 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1467 VPSCATTERQQZ128mr,
1468 VSCATTERDPDZ128mr,
1469 VSCATTERQPDZ128mr)>;
1471 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1472 let Latency = 7;
1473 let NumMicroOps = 7;
1474 let ResourceCycles = [1,3,1,2];
1475 }
1476 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1478 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1479 let Latency = 7;
1480 let NumMicroOps = 11;
1481 let ResourceCycles = [1,4,4,2];
1482 }
1483 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1484 VPSCATTERQQZ256mr,
1485 VSCATTERDPDZ256mr,
1486 VSCATTERQPDZ256mr)>;
1488 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1489 let Latency = 7;
1490 let NumMicroOps = 19;
1491 let ResourceCycles = [1,8,8,2];
1492 }
1493 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1494 VPSCATTERQQZmr,
1495 VSCATTERDPDZmr,
1496 VSCATTERQPDZmr)>;
1498 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1499 let Latency = 7;
1500 let NumMicroOps = 36;
1501 let ResourceCycles = [1,16,1,16,2];
1502 }
1503 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1505 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1506 let Latency = 8;
1507 let NumMicroOps = 2;
1508 let ResourceCycles = [1,1];
1509 }
1510 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1511 "PEXT(32|64)rm")>;
1513 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1514 let Latency = 8;
1515 let NumMicroOps = 2;
1516 let ResourceCycles = [1,1];
1517 }
1518 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1519 "VFPCLASSSDZrm(b?)",
1520 "VPBROADCASTB(Z|Z256)m(b?)",
1521 "VPBROADCASTW(Z|Z256)m(b?)")>;
1522 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1523 VPBROADCASTWYrm,
1524 VPMOVSXBDYrm,
1525 VPMOVSXBQYrm,
1526 VPMOVSXWQYrm)>;
1528 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1529 let Latency = 8;
1530 let NumMicroOps = 2;
1531 let ResourceCycles = [1,1];
1532 }
1533 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1534 VPBLENDDYrmi)>;
1535 def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd],
1536 (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1537 "VBLENDMPS(Z|Z256)rm(b?)",
1538 "VBROADCASTF32X2Z256m(b?)",
1539 "VBROADCASTF32X2Zm(b?)",
1540 "VBROADCASTF32X4Z256rm(b?)",
1541 "VBROADCASTF32X4rm(b?)",
1542 "VBROADCASTF32X8rm(b?)",
1543 "VBROADCASTF64X2Z128rm(b?)",
1544 "VBROADCASTF64X2rm(b?)",
1545 "VBROADCASTF64X4rm(b?)",
1546 "VBROADCASTI32X2Z256m(b?)",
1547 "VBROADCASTI32X2Zm(b?)",
1548 "VBROADCASTI32X4Z256rm(b?)",
1549 "VBROADCASTI32X4rm(b?)",
1550 "VBROADCASTI32X8rm(b?)",
1551 "VBROADCASTI64X2Z128rm(b?)",
1552 "VBROADCASTI64X2rm(b?)",
1553 "VBROADCASTI64X4rm(b?)",
1554 "VBROADCASTSD(Z|Z256)m(b?)",
1555 "VBROADCASTSS(Z|Z256)m(b?)",
1556 "VINSERTF32x4(Z|Z256)rm(b?)",
1557 "VINSERTF32x8Zrm(b?)",
1558 "VINSERTF64x2(Z|Z256)rm(b?)",
1559 "VINSERTF64x4Zrm(b?)",
1560 "VINSERTI32x4(Z|Z256)rm(b?)",
1561 "VINSERTI32x8Zrm(b?)",
1562 "VINSERTI64x2(Z|Z256)rm(b?)",
1563 "VINSERTI64x4Zrm(b?)",
1564 "VMOVAPD(Z|Z256)rm(b?)",
1565 "VMOVAPS(Z|Z256)rm(b?)",
1566 "VMOVDDUP(Z|Z256)rm(b?)",
1567 "VMOVDQA32(Z|Z256)rm(b?)",
1568 "VMOVDQA64(Z|Z256)rm(b?)",
1569 "VMOVDQU16(Z|Z256)rm(b?)",
1570 "VMOVDQU32(Z|Z256)rm(b?)",
1571 "VMOVDQU64(Z|Z256)rm(b?)",
1572 "VMOVDQU8(Z|Z256)rm(b?)",
1573 "VMOVSHDUP(Z|Z256)rm(b?)",
1574 "VMOVSLDUP(Z|Z256)rm(b?)",
1575 "VMOVUPD(Z|Z256)rm(b?)",
1576 "VMOVUPS(Z|Z256)rm(b?)",
1577 "VPADD(B|D|Q|W)Yrm",
1578 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1579 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1580 "VPBROADCASTD(Z|Z256)m(b?)",
1581 "VPBROADCASTQ(Z|Z256)m(b?)",
1582 "VPSUB(B|D|Q|W)Yrm",
1583 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1584 "VPTERNLOGD(Z|Z256)rm(b?)i",
1585 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1587 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1588 let Latency = 8;
1589 let NumMicroOps = 4;
1590 let ResourceCycles = [1,2,1];
1591 }
1592 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1594 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1595 let Latency = 8;
1596 let NumMicroOps = 5;
1597 let ResourceCycles = [1,1,1,2];
1598 }
1599 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1600 "RCR(8|16|32|64)m(1|i)")>;
1602 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1603 let Latency = 8;
1604 let NumMicroOps = 6;
1605 let ResourceCycles = [1,1,1,3];
1606 }
1607 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1608 "ROR(8|16|32|64)mCL",
1609 "SAR(8|16|32|64)mCL",
1610 "SHL(8|16|32|64)mCL",
1611 "SHR(8|16|32|64)mCL")>;
1613 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1614 let Latency = 8;
1615 let NumMicroOps = 6;
1616 let ResourceCycles = [1,1,1,2,1];
1617 }
1618 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1620 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1621 let Latency = 8;
1622 let NumMicroOps = 8;
1623 let ResourceCycles = [1,2,1,2,2];
1624 }
1625 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1626 VPSCATTERQDZ256mr,
1627 VSCATTERQPSZ128mr,
1628 VSCATTERQPSZ256mr)>;
1630 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1631 let Latency = 8;
1632 let NumMicroOps = 12;
1633 let ResourceCycles = [1,4,1,4,2];
1634 }
1635 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1636 VSCATTERDPSZ128mr)>;
1638 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1639 let Latency = 8;
1640 let NumMicroOps = 20;
1641 let ResourceCycles = [1,8,1,8,2];
1642 }
1643 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1644 VSCATTERDPSZ256mr)>;
1646 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1647 let Latency = 8;
1648 let NumMicroOps = 36;
1649 let ResourceCycles = [1,16,1,16,2];
1650 }
1651 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1653 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1654 let Latency = 9;
1655 let NumMicroOps = 2;
1656 let ResourceCycles = [1,1];
1657 }
1658 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1660 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1661 let Latency = 9;
1662 let NumMicroOps = 2;
1663 let ResourceCycles = [1,1];
1664 }
1665 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1666 VPMOVSXDQYrm,
1667 VPMOVSXWDYrm,
1668 VPMOVZXWDYrm)>;
1669 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1670 "VCMP(PD|PS)Z128rm(b?)i",
1671 "VCMP(SD|SS)Zrm",
1672 "VFPCLASSSSZrm(b?)",
1673 "VPCMPBZ128rmi(b?)",
1674 "VPCMPDZ128rmi(b?)",
1675 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1676 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1677 "(V?)PCMPGTQrm",
1678 "VPCMPQZ128rmi(b?)",
1679 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1680 "VPCMPWZ128rmi(b?)",
1681 "VPERMI2D128rm(b?)",
1682 "VPERMI2PD128rm(b?)",
1683 "VPERMI2PS128rm(b?)",
1684 "VPERMI2Q128rm(b?)",
1685 "VPERMT2D128rm(b?)",
1686 "VPERMT2PD128rm(b?)",
1687 "VPERMT2PS128rm(b?)",
1688 "VPERMT2Q128rm(b?)",
1689 "VPMAXSQZ128rm(b?)",
1690 "VPMAXUQZ128rm(b?)",
1691 "VPMINSQZ128rm(b?)",
1692 "VPMINUQZ128rm(b?)",
1693 "VPMOVSXBDZ128rm(b?)",
1694 "VPMOVSXBQZ128rm(b?)",
1695 "VPMOVSXBWZ128rm(b?)",
1696 "VPMOVSXDQZ128rm(b?)",
1697 "VPMOVSXWDZ128rm(b?)",
1698 "VPMOVSXWQZ128rm(b?)",
1699 "VPMOVZXBDZ128rm(b?)",
1700 "VPMOVZXBQZ128rm(b?)",
1701 "VPMOVZXBWZ128rm(b?)",
1702 "VPMOVZXDQZ128rm(b?)",
1703 "VPMOVZXWDZ128rm(b?)",
1704 "VPMOVZXWQZ128rm(b?)",
1705 "VPTESTMBZ128rm(b?)",
1706 "VPTESTMDZ128rm(b?)",
1707 "VPTESTMQZ128rm(b?)",
1708 "VPTESTMWZ128rm(b?)",
1709 "VPTESTNMBZ128rm(b?)",
1710 "VPTESTNMDZ128rm(b?)",
1711 "VPTESTNMQZ128rm(b?)",
1712 "VPTESTNMWZ128rm(b?)")>;
1714 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1715 let Latency = 9;
1716 let NumMicroOps = 2;
1717 let ResourceCycles = [1,1];
1718 }
1719 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1720 "(V?)CVTPS2PDrm")>;
1722 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1723 let Latency = 9;
1724 let NumMicroOps = 4;
1725 let ResourceCycles = [2,1,1];
1726 }
1727 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1728 "(V?)PHSUBSWrm")>;
1730 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1731 let Latency = 9;
1732 let NumMicroOps = 5;
1733 let ResourceCycles = [1,2,1,1];
1734 }
1735 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1736 "LSL(16|32|64)rm")>;
1738 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1739 let Latency = 10;
1740 let NumMicroOps = 2;
1741 let ResourceCycles = [1,1];
1742 }
1743 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1744 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1745 "ILD_F(16|32|64)m",
1746 "VALIGND(Z|Z256)rm(b?)i",
1747 "VALIGNQ(Z|Z256)rm(b?)i",
1748 "VCMPPD(Z|Z256)rm(b?)i",
1749 "VCMPPS(Z|Z256)rm(b?)i",
1750 "VPCMPB(Z|Z256)rmi(b?)",
1751 "VPCMPD(Z|Z256)rmi(b?)",
1752 "VPCMPEQB(Z|Z256)rm(b?)",
1753 "VPCMPEQD(Z|Z256)rm(b?)",
1754 "VPCMPEQQ(Z|Z256)rm(b?)",
1755 "VPCMPEQW(Z|Z256)rm(b?)",
1756 "VPCMPGTB(Z|Z256)rm(b?)",
1757 "VPCMPGTD(Z|Z256)rm(b?)",
1758 "VPCMPGTQ(Z|Z256)rm(b?)",
1759 "VPCMPGTW(Z|Z256)rm(b?)",
1760 "VPCMPQ(Z|Z256)rmi(b?)",
1761 "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1762 "VPCMPU(B|D|Q|W)Zrmi(b?)",
1763 "VPCMPW(Z|Z256)rmi(b?)",
1764 "VPMAXSQ(Z|Z256)rm(b?)",
1765 "VPMAXUQ(Z|Z256)rm(b?)",
1766 "VPMINSQ(Z|Z256)rm(b?)",
1767 "VPMINUQ(Z|Z256)rm(b?)",
1768 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1769 "VPTESTM(B|D|Q|W)Zrm(b?)",
1770 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1771 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1773 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1774 let Latency = 10;
1775 let NumMicroOps = 2;
1776 let ResourceCycles = [1,1];
1777 }
1778 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1779 "VCVTDQ2PSZ128rm(b?)",
1780 "(V?)CVTDQ2PSrm",
1781 "VCVTPD2QQZ128rm(b?)",
1782 "VCVTPD2UQQZ128rm(b?)",
1783 "VCVTPH2PSZ128rm(b?)",
1784 "VCVTPS2DQZ128rm(b?)",
1785 "(V?)CVTPS2DQrm",
1786 "VCVTPS2PDZ128rm(b?)",
1787 "VCVTPS2QQZ128rm(b?)",
1788 "VCVTPS2UDQZ128rm(b?)",
1789 "VCVTPS2UQQZ128rm(b?)",
1790 "VCVTQQ2PDZ128rm(b?)",
1791 "VCVTQQ2PSZ128rm(b?)",
1792 "VCVTSS2SDZrm",
1793 "(V?)CVTSS2SDrm",
1794 "VCVTTPD2QQZ128rm(b?)",
1795 "VCVTTPD2UQQZ128rm(b?)",
1796 "VCVTTPS2DQZ128rm(b?)",
1797 "(V?)CVTTPS2DQrm",
1798 "VCVTTPS2QQZ128rm(b?)",
1799 "VCVTTPS2UDQZ128rm(b?)",
1800 "VCVTTPS2UQQZ128rm(b?)",
1801 "VCVTUDQ2PDZ128rm(b?)",
1802 "VCVTUDQ2PSZ128rm(b?)",
1803 "VCVTUQQ2PDZ128rm(b?)",
1804 "VCVTUQQ2PSZ128rm(b?)")>;
1806 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1807 let Latency = 10;
1808 let NumMicroOps = 3;
1809 let ResourceCycles = [2,1];
1810 }
1811 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1812 "VEXPANDPSZ128rm(b?)",
1813 "VPEXPANDDZ128rm(b?)",
1814 "VPEXPANDQZ128rm(b?)")>;
1816 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1817 let Latency = 10;
1818 let NumMicroOps = 3;
1819 let ResourceCycles = [1,1,1];
1820 }
1821 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1823 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1824 let Latency = 10;
1825 let NumMicroOps = 4;
1826 let ResourceCycles = [2,1,1];
1827 }
1828 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1829 VPHSUBSWYrm)>;
1831 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1832 let Latency = 10;
1833 let NumMicroOps = 8;
1834 let ResourceCycles = [1,1,1,1,1,3];
1835 }
1836 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1838 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1839 let Latency = 11;
1840 let NumMicroOps = 1;
1841 let ResourceCycles = [1,3];
1842 }
1843 def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1845 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1846 let Latency = 11;
1847 let NumMicroOps = 2;
1848 let ResourceCycles = [1,1];
1849 }
1850 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1852 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1853 let Latency = 11;
1854 let NumMicroOps = 2;
1855 let ResourceCycles = [1,1];
1856 }
1857 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1858 VCVTPS2PDYrm)>;
1859 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1860 "VCVTPH2PS(Z|Z256)rm(b?)",
1861 "VCVTPS2PD(Z|Z256)rm(b?)",
1862 "VCVTQQ2PD(Z|Z256)rm(b?)",
1863 "VCVTQQ2PSZ256rm(b?)",
1864 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1865 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1866 "VCVT(T?)PS2DQYrm",
1867 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1868 "VCVT(T?)PS2QQZ256rm(b?)",
1869 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1870 "VCVT(T?)PS2UQQZ256rm(b?)",
1871 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1872 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1873 "VCVTUQQ2PSZ256rm(b?)")>;
1875 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1876 let Latency = 11;
1877 let NumMicroOps = 3;
1878 let ResourceCycles = [2,1];
1879 }
1880 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1881 "VEXPANDPD(Z|Z256)rm(b?)",
1882 "VEXPANDPS(Z|Z256)rm(b?)",
1883 "VPEXPANDD(Z|Z256)rm(b?)",
1884 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1886 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1887 let Latency = 11;
1888 let NumMicroOps = 3;
1889 let ResourceCycles = [1,2];
1890 }
1891 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1893 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1894 let Latency = 11;
1895 let NumMicroOps = 3;
1896 let ResourceCycles = [1,1,1];
1897 }
1898 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1900 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1901 let Latency = 11;
1902 let NumMicroOps = 3;
1903 let ResourceCycles = [1,1,1];
1904 }
1905 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1906 CVTPD2DQrm,
1907 CVTTPD2DQrm,
1908 MMX_CVTPD2PIirm,
1909 MMX_CVTTPD2PIirm)>;
1911 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1912 let Latency = 11;
1913 let NumMicroOps = 4;
1914 let ResourceCycles = [2,1,1];
1915 }
1916 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1918 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1919 let Latency = 11;
1920 let NumMicroOps = 7;
1921 let ResourceCycles = [2,3,2];
1922 }
1923 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1924 "RCR(16|32|64)rCL")>;
1926 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1927 let Latency = 11;
1928 let NumMicroOps = 9;
1929 let ResourceCycles = [1,5,1,2];
1930 }
1931 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1933 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1934 let Latency = 11;
1935 let NumMicroOps = 11;
1936 let ResourceCycles = [2,9];
1937 }
1938 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1940 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1941 let Latency = 12;
1942 let NumMicroOps = 3;
1943 let ResourceCycles = [3];
1944 }
1945 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1947 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
1948 let Latency = 12;
1949 let NumMicroOps = 3;
1950 let ResourceCycles = [3];
1951 }
1952 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
1954 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1955 let Latency = 12;
1956 let NumMicroOps = 3;
1957 let ResourceCycles = [2,1];
1958 }
1959 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
1961 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
1962 let Latency = 12;
1963 let NumMicroOps = 3;
1964 let ResourceCycles = [1,1,1];
1965 }
1966 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
1967 "VCVT(T?)SS2USI64Zrm(b?)")>;
1969 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1970 let Latency = 12;
1971 let NumMicroOps = 3;
1972 let ResourceCycles = [1,1,1];
1973 }
1974 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
1975 "VCVT(T?)PS2UQQZrm(b?)")>;
1977 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
1978 let Latency = 12;
1979 let NumMicroOps = 4;
1980 let ResourceCycles = [1,1,1,1];
1981 }
1982 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
1984 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1985 let Latency = 13;
1986 let NumMicroOps = 3;
1987 let ResourceCycles = [2,1];
1988 }
1989 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
1990 "VPERMWZ256rm(b?)",
1991 "VPERMWZrm(b?)")>;
1993 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1994 let Latency = 13;
1995 let NumMicroOps = 3;
1996 let ResourceCycles = [1,1,1];
1997 }
1998 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
2000 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2001 let Latency = 13;
2002 let NumMicroOps = 4;
2003 let ResourceCycles = [2,1,1];
2004 }
2005 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2006 "VPERMT2W128rm(b?)")>;
2008 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2009 let Latency = 14;
2010 let NumMicroOps = 1;
2011 let ResourceCycles = [1,3];
2012 }
2013 def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2014 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2016 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2017 let Latency = 14;
2018 let NumMicroOps = 1;
2019 let ResourceCycles = [1,5];
2020 }
2021 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2023 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2024 let Latency = 14;
2025 let NumMicroOps = 3;
2026 let ResourceCycles = [1,1,1];
2027 }
2028 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2030 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2031 let Latency = 14;
2032 let NumMicroOps = 3;
2033 let ResourceCycles = [1,1,1];
2034 }
2035 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2036 "VCVTPD2PSZrm(b?)",
2037 "VCVTPD2UDQZrm(b?)",
2038 "VCVTQQ2PSZrm(b?)",
2039 "VCVTTPD2DQZrm(b?)",
2040 "VCVTTPD2UDQZrm(b?)",
2041 "VCVTUQQ2PSZrm(b?)")>;
2043 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2044 let Latency = 14;
2045 let NumMicroOps = 4;
2046 let ResourceCycles = [2,1,1];
2047 }
2048 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2049 "VPERMI2Wrm(b?)",
2050 "VPERMT2W256rm(b?)",
2051 "VPERMT2Wrm(b?)")>;
2053 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2054 let Latency = 14;
2055 let NumMicroOps = 10;
2056 let ResourceCycles = [2,4,1,3];
2057 }
2058 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2060 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2061 let Latency = 15;
2062 let NumMicroOps = 1;
2063 let ResourceCycles = [1];
2064 }
2065 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2067 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2068 let Latency = 15;
2069 let NumMicroOps = 8;
2070 let ResourceCycles = [1,2,2,1,2];
2071 }
2072 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2074 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2075 let Latency = 15;
2076 let NumMicroOps = 10;
2077 let ResourceCycles = [1,1,1,5,1,1];
2078 }
2079 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2081 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2082 let Latency = 16;
2083 let NumMicroOps = 14;
2084 let ResourceCycles = [1,1,1,4,2,5];
2085 }
2086 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2088 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> {
2089 let Latency = 12;
2090 let NumMicroOps = 34;
2091 let ResourceCycles = [1, 4, 5];
2092 }
2093 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2095 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2096 let Latency = 17;
2097 let NumMicroOps = 2;
2098 let ResourceCycles = [1,1,5];
2099 }
2100 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2102 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2103 let Latency = 17;
2104 let NumMicroOps = 15;
2105 let ResourceCycles = [2,1,2,4,2,4];
2106 }
2107 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2109 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2110 let Latency = 18;
2111 let NumMicroOps = 4;
2112 let ResourceCycles = [1,3];
2113 }
2114 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2116 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2117 let Latency = 18;
2118 let NumMicroOps = 8;
2119 let ResourceCycles = [1,1,1,5];
2120 }
2121 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2123 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2124 let Latency = 18;
2125 let NumMicroOps = 11;
2126 let ResourceCycles = [2,1,1,4,1,2];
2127 }
2128 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2130 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2131 let Latency = 19;
2132 let NumMicroOps = 2;
2133 let ResourceCycles = [1,1,4];
2134 }
2135 def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2137 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2138 let Latency = 19;
2139 let NumMicroOps = 4;
2140 let ResourceCycles = [1,3];
2141 }
2142 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2143 "VPMULLQZrm(b?)")>;
2145 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2146 let Latency = 20;
2147 let NumMicroOps = 0;
2148 }
2149 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2150 VGATHERQPSZrm,
2151 VPGATHERDDZ128rm)>;
2153 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2154 let Latency = 20;
2155 let NumMicroOps = 1;
2156 let ResourceCycles = [1];
2157 }
2158 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2160 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2161 let Latency = 20;
2162 let NumMicroOps = 2;
2163 let ResourceCycles = [1,1,4];
2164 }
2165 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2167 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2168 let Latency = 20;
2169 let NumMicroOps = 5;
2170 let ResourceCycles = [1,2,1,1];
2171 }
2172 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2173 VGATHERQPSZ256rm,
2174 VPGATHERQDZ128rm,
2175 VPGATHERQDZ256rm)>;
2177 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2178 let Latency = 20;
2179 let NumMicroOps = 8;
2180 let ResourceCycles = [1,1,1,1,1,1,2];
2181 }
2182 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2184 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2185 let Latency = 20;
2186 let NumMicroOps = 10;
2187 let ResourceCycles = [1,2,7];
2188 }
2189 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2191 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2192 let Latency = 21;
2193 let NumMicroOps = 2;
2194 let ResourceCycles = [1,1,8];
2195 }
2196 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2198 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2199 let Latency = 22;
2200 let NumMicroOps = 2;
2201 let ResourceCycles = [1,1];
2202 }
2203 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2205 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2206 let Latency = 22;
2207 let NumMicroOps = 5;
2208 let ResourceCycles = [1,2,1,1];
2209 }
2210 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2211 VGATHERQPDZ128rm,
2212 VPGATHERDQZ128rm,
2213 VPGATHERQQZ128rm)>;
2215 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2216 let Latency = 22;
2217 let NumMicroOps = 5;
2218 let ResourceCycles = [1,2,1,1];
2219 }
2220 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2221 VGATHERDPDrm,
2222 VGATHERQPDrm,
2223 VGATHERQPSrm,
2224 VPGATHERDDrm,
2225 VPGATHERDQrm,
2226 VPGATHERQDrm,
2227 VPGATHERQQrm,
2228 VPGATHERDDrm,
2229 VPGATHERQDrm,
2230 VPGATHERDQrm,
2231 VPGATHERQQrm,
2232 VGATHERDPSrm,
2233 VGATHERQPSrm,
2234 VGATHERDPDrm,
2235 VGATHERQPDrm)>;
2237 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2238 let Latency = 25;
2239 let NumMicroOps = 5;
2240 let ResourceCycles = [1,2,1,1];
2241 }
2242 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2243 VGATHERQPDYrm,
2244 VGATHERQPSYrm,
2245 VPGATHERDDYrm,
2246 VPGATHERDQYrm,
2247 VPGATHERQDYrm,
2248 VPGATHERQQYrm,
2249 VPGATHERDDYrm,
2250 VPGATHERQDYrm,
2251 VPGATHERDQYrm,
2252 VPGATHERQQYrm,
2253 VGATHERDPSYrm,
2254 VGATHERQPSYrm,
2255 VGATHERDPDYrm)>;
2257 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2258 let Latency = 22;
2259 let NumMicroOps = 14;
2260 let ResourceCycles = [5,5,4];
2261 }
2262 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2263 "VPCONFLICTQZ256rr")>;
2265 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2266 let Latency = 23;
2267 let NumMicroOps = 19;
2268 let ResourceCycles = [2,1,4,1,1,4,6];
2269 }
2270 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2272 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2273 let Latency = 25;
2274 let NumMicroOps = 3;
2275 let ResourceCycles = [1,1,1];
2276 }
2277 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2279 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2280 let Latency = 25;
2281 let NumMicroOps = 5;
2282 let ResourceCycles = [1,2,1,1];
2283 }
2284 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2285 VGATHERQPDZ256rm,
2286 VPGATHERDQZ256rm,
2287 VPGATHERQDZrm,
2288 VPGATHERQQZ256rm)>;
2290 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2291 let Latency = 26;
2292 let NumMicroOps = 5;
2293 let ResourceCycles = [1,2,1,1];
2294 }
2295 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2296 VGATHERQPDZrm,
2297 VPGATHERDQZrm,
2298 VPGATHERQQZrm)>;
2300 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2301 let Latency = 27;
2302 let NumMicroOps = 2;
2303 let ResourceCycles = [1,1];
2304 }
2305 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2307 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2308 let Latency = 27;
2309 let NumMicroOps = 5;
2310 let ResourceCycles = [1,2,1,1];
2311 }
2312 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2313 VPGATHERDDZ256rm)>;
2315 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2316 let Latency = 29;
2317 let NumMicroOps = 15;
2318 let ResourceCycles = [5,5,1,4];
2319 }
2320 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2322 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2323 let Latency = 30;
2324 let NumMicroOps = 3;
2325 let ResourceCycles = [1,1,1];
2326 }
2327 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2329 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2330 let Latency = 30;
2331 let NumMicroOps = 5;
2332 let ResourceCycles = [1,2,1,1];
2333 }
2334 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2335 VPGATHERDDZrm)>;
2337 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2338 let Latency = 35;
2339 let NumMicroOps = 23;
2340 let ResourceCycles = [1,5,3,4,10];
2341 }
2342 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2343 "IN(8|16|32)rr")>;
2345 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2346 let Latency = 35;
2347 let NumMicroOps = 23;
2348 let ResourceCycles = [1,5,2,1,4,10];
2349 }
2350 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2351 "OUT(8|16|32)rr")>;
2353 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2354 let Latency = 37;
2355 let NumMicroOps = 21;
2356 let ResourceCycles = [9,7,5];
2357 }
2358 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2359 "VPCONFLICTQZrr")>;
2361 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2362 let Latency = 37;
2363 let NumMicroOps = 31;
2364 let ResourceCycles = [1,8,1,21];
2365 }
2366 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2368 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2369 let Latency = 40;
2370 let NumMicroOps = 18;
2371 let ResourceCycles = [1,1,2,3,1,1,1,8];
2372 }
2373 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2375 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2376 let Latency = 41;
2377 let NumMicroOps = 39;
2378 let ResourceCycles = [1,10,1,1,26];
2379 }
2380 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2382 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2383 let Latency = 42;
2384 let NumMicroOps = 22;
2385 let ResourceCycles = [2,20];
2386 }
2387 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2389 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2390 let Latency = 42;
2391 let NumMicroOps = 40;
2392 let ResourceCycles = [1,11,1,1,26];
2393 }
2394 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2395 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2397 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2398 let Latency = 44;
2399 let NumMicroOps = 22;
2400 let ResourceCycles = [9,7,1,5];
2401 }
2402 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2403 "VPCONFLICTQZrm(b?)")>;
2405 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2406 let Latency = 62;
2407 let NumMicroOps = 64;
2408 let ResourceCycles = [2,8,5,10,39];
2409 }
2410 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2412 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2413 let Latency = 63;
2414 let NumMicroOps = 88;
2415 let ResourceCycles = [4,4,31,1,2,1,45];
2416 }
2417 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2419 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2420 let Latency = 63;
2421 let NumMicroOps = 90;
2422 let ResourceCycles = [4,2,33,1,2,1,47];
2423 }
2424 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2426 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2427 let Latency = 67;
2428 let NumMicroOps = 35;
2429 let ResourceCycles = [17,11,7];
2430 }
2431 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2433 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2434 let Latency = 74;
2435 let NumMicroOps = 36;
2436 let ResourceCycles = [17,11,1,7];
2437 }
2438 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2440 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2441 let Latency = 75;
2442 let NumMicroOps = 15;
2443 let ResourceCycles = [6,3,6];
2444 }
2445 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2447 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2448 let Latency = 106;
2449 let NumMicroOps = 100;
2450 let ResourceCycles = [9,1,11,16,1,11,21,30];
2451 }
2452 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2454 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2455 let Latency = 140;
2456 let NumMicroOps = 4;
2457 let ResourceCycles = [1,3];
2458 }
2459 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2461 def: InstRW<[WriteZero], (instrs CLC)>;
2464 // Intruction variants handled by the renamer. These might not need execution
2465 // ports in certain conditions.
2466 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
2467 // section "Skylake Pipeline" > "Register allocation and renaming".
2468 // These can be investigated with llvm-exegesis, e.g.
2469 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2470 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2472 def SKXWriteZeroLatency : SchedWriteRes<[]> {
2473 let Latency = 0;
2474 }
2476 def SKXWriteZeroIdiom : SchedWriteVariant<[
2477 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2478 SchedVar<NoSchedPred, [WriteALU]>
2479 ]>;
2480 def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
2481 XOR32rr, XOR64rr)>;
2483 def SKXWriteFZeroIdiom : SchedWriteVariant<[
2484 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2485 SchedVar<NoSchedPred, [WriteFLogic]>
2486 ]>;
2487 def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr,
2488 XORPDrr, VXORPDrr,
2489 VXORPSZ128rr,
2490 VXORPDZ128rr)>;
2492 def SKXWriteFZeroIdiomY : SchedWriteVariant<[
2493 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2494 SchedVar<NoSchedPred, [WriteFLogicY]>
2495 ]>;
2496 def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr,
2497 VXORPSZ256rr, VXORPDZ256rr)>;
2499 def SKXWriteFZeroIdiomZ : SchedWriteVariant<[
2500 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2501 SchedVar<NoSchedPred, [WriteFLogicZ]>
2502 ]>;
2503 def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>;
2505 def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[
2506 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2507 SchedVar<NoSchedPred, [WriteVecLogicX]>
2508 ]>;
2509 def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
2510 VPXORDZ128rr, VPXORQZ128rr)>;
2512 def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[
2513 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2514 SchedVar<NoSchedPred, [WriteVecLogicY]>
2515 ]>;
2516 def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr,
2517 VPXORDZ256rr, VPXORQZ256rr)>;
2519 def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[
2520 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2521 SchedVar<NoSchedPred, [WriteVecLogicZ]>
2522 ]>;
2523 def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>;
2525 def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[
2526 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2527 SchedVar<NoSchedPred, [WriteVecALUX]>
2528 ]>;
2529 def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
2530 PCMPGTDrr, VPCMPGTDrr,
2531 PCMPGTWrr, VPCMPGTWrr)>;
2533 def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[
2534 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2535 SchedVar<NoSchedPred, [WriteVecALUY]>
2536 ]>;
2537 def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
2538 VPCMPGTDYrr,
2539 VPCMPGTWYrr)>;
2541 def SKXWritePSUB : SchedWriteRes<[SKXPort015]> {
2542 let Latency = 1;
2543 let NumMicroOps = 1;
2544 let ResourceCycles = [1];
2545 }
2547 def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[
2548 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2549 SchedVar<NoSchedPred, [SKXWritePSUB]>
2550 ]>;
2552 def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr,
2553 PSUBDrr, VPSUBDrr, VPSUBDZ128rr,
2554 PSUBQrr, VPSUBQrr, VPSUBQZ128rr,
2555 PSUBWrr, VPSUBWrr, VPSUBWZ128rr,
2556 VPSUBBYrr, VPSUBBZ256rr,
2557 VPSUBDYrr, VPSUBDZ256rr,
2558 VPSUBQYrr, VPSUBQZ256rr,
2559 VPSUBWYrr, VPSUBWZ256rr,
2560 VPSUBBZrr,
2561 VPSUBDZrr,
2562 VPSUBQZrr,
2563 VPSUBWZrr)>;
2564 def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> {
2565 let Latency = 3;
2566 let NumMicroOps = 1;
2567 let ResourceCycles = [1];
2568 }
2570 def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
2571 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>,
2572 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]>
2573 ]>;
2574 def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
2575 VPCMPGTQYrr)>;
2578 // CMOVs that use both Z and C flag require an extra uop.
2579 def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> {
2580 let Latency = 2;
2581 let ResourceCycles = [2];
2582 let NumMicroOps = 2;
2583 }
2585 def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> {
2586 let Latency = 7;
2587 let ResourceCycles = [1,2];
2588 let NumMicroOps = 3;
2589 }
2591 def SKXCMOVA_CMOVBErr : SchedWriteVariant<[
2592 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>,
2593 SchedVar<NoSchedPred, [WriteCMOV]>
2594 ]>;
2596 def SKXCMOVA_CMOVBErm : SchedWriteVariant<[
2597 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>,
2598 SchedVar<NoSchedPred, [WriteCMOV.Folded]>
2599 ]>;
2601 def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
2602 def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
2604 // SETCCs that use both Z and C flag require an extra uop.
2605 def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> {
2606 let Latency = 2;
2607 let ResourceCycles = [2];
2608 let NumMicroOps = 2;
2609 }
2611 def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
2612 let Latency = 3;
2613 let ResourceCycles = [1,1,2];
2614 let NumMicroOps = 4;
2615 }
2617 def SKXSETA_SETBErr : SchedWriteVariant<[
2618 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>,
2619 SchedVar<NoSchedPred, [WriteSETCC]>
2620 ]>;
2622 def SKXSETA_SETBErm : SchedWriteVariant<[
2623 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>,
2624 SchedVar<NoSchedPred, [WriteSETCCStore]>
2625 ]>;
2627 def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>;
2628 def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>;
2630 } // SchedModel