lib/Target/PowerPC/PPCISelLowering.h

   1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that PPC uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  17
  18 #include "PPC.h"
  19 #include "PPCInstrInfo.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineMemOperand.h"
  23 #include "llvm/CodeGen/MachineValueType.h"
  24 #include "llvm/CodeGen/SelectionDAG.h"
  25 #include "llvm/CodeGen/SelectionDAGNodes.h"
  26 #include "llvm/CodeGen/TargetLowering.h"
  27 #include "llvm/CodeGen/ValueTypes.h"
  28 #include "llvm/IR/Attributes.h"
  29 #include "llvm/IR/CallingConv.h"
  30 #include "llvm/IR/Function.h"
  31 #include "llvm/IR/InlineAsm.h"
  32 #include "llvm/IR/Metadata.h"
  33 #include "llvm/IR/Type.h"
  34 #include <utility>
  35
  36 namespace llvm {
  37
  38   namespace PPCISD {
  39
  40     // When adding a NEW PPCISD node please add it to the correct position in
  41     // the enum. The order of elements in this enum matters!
  42     // Values that are added after this entry:
  43     //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
  44     // are considerd memory opcodes and are treated differently than entries
  45     // that come before it. For example, ADD or MUL should be placed before
  46     // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
  47     // after it.
  48     enum NodeType : unsigned {
  49       // Start the numbering where the builtin ops and target ops leave off.
  50       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  51
  52       /// FSEL - Traditional three-operand fsel node.
  53       ///
  54       FSEL,
  55
  56       /// FCFID - The FCFID instruction, taking an f64 operand and producing
  57       /// and f64 value containing the FP representation of the integer that
  58       /// was temporarily in the f64 operand.
  59       FCFID,
  60
  61       /// Newer FCFID[US] integer-to-floating-point conversion instructions for
  62       /// unsigned integers and single-precision outputs.
  63       FCFIDU, FCFIDS, FCFIDUS,
  64
  65       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
  66       /// operand, producing an f64 value containing the integer representation
  67       /// of that FP value.
  68       FCTIDZ, FCTIWZ,
  69
  70       /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
  71       /// unsigned integers with round toward zero.
  72       FCTIDUZ, FCTIWUZ,
  73
  74       /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
  75       /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
  76       VEXTS,
  77
  78       /// SExtVElems, takes an input vector of a smaller type and sign
  79       /// extends to an output vector of a larger type.
  80       SExtVElems,
  81
  82       /// Reciprocal estimate instructions (unary FP ops).
  83       FRE, FRSQRTE,
  84
  85       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
  86       // three v4f32 operands and producing a v4f32 result.
  87       VMADDFP, VNMSUBFP,
  88
  89       /// VPERM - The PPC VPERM Instruction.
  90       ///
  91       VPERM,
  92
  93       /// XXSPLT - The PPC VSX splat instructions
  94       ///
  95       XXSPLT,
  96
  97       /// VECINSERT - The PPC vector insert instruction
  98       ///
  99       VECINSERT,
 100
 101       /// XXREVERSE - The PPC VSX reverse instruction
 102       ///
 103       XXREVERSE,
 104
 105       /// VECSHL - The PPC vector shift left instruction
 106       ///
 107       VECSHL,
 108
 109       /// XXPERMDI - The PPC XXPERMDI instruction
 110       ///
 111       XXPERMDI,
 112
 113       /// The CMPB instruction (takes two operands of i32 or i64).
 114       CMPB,
 115
 116       /// Hi/Lo - These represent the high and low 16-bit parts of a global
 117       /// address respectively.  These nodes have two operands, the first of
 118       /// which must be a TargetGlobalAddress, and the second of which must be a
 119       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
 120       /// though these are usually folded into other nodes.
 121       Hi, Lo,
 122
 123       /// The following two target-specific nodes are used for calls through
 124       /// function pointers in the 64-bit SVR4 ABI.
 125
 126       /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
 127       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 128       /// compute an allocation on the stack.
 129       DYNALLOC,
 130
 131       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 132       /// compute an offset from native SP to the address  of the most recent
 133       /// dynamic alloca.
 134       DYNAREAOFFSET,
 135
 136       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
 137       /// at function entry, used for PIC code.
 138       GlobalBaseReg,
 139
 140       /// These nodes represent PPC shifts.
 141       ///
 142       /// For scalar types, only the last `n + 1` bits of the shift amounts
 143       /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
 144       /// for exact behaviors.
 145       ///
 146       /// For vector types, only the last n bits are used. See vsld.
 147       SRL, SRA, SHL,
 148
 149       /// The combination of sra[wd]i and addze used to implemented signed
 150       /// integer division by a power of 2. The first operand is the dividend,
 151       /// and the second is the constant shift amount (representing the
 152       /// divisor).
 153       SRA_ADDZE,
 154
 155       /// CALL - A direct function call.
 156       /// CALL_NOP is a call with the special NOP which follows 64-bit
 157       /// SVR4 calls.
 158       CALL, CALL_NOP,
 159
 160       /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
 161       /// MTCTR instruction.
 162       MTCTR,
 163
 164       /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
 165       /// BCTRL instruction.
 166       BCTRL,
 167
 168       /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
 169       /// instruction and the TOC reload required on SVR4 PPC64.
 170       BCTRL_LOAD_TOC,
 171
 172       /// Return with a flag operand, matched by 'blr'
 173       RET_FLAG,
 174
 175       /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
 176       /// This copies the bits corresponding to the specified CRREG into the
 177       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
 178       MFOCRF,
 179
 180       /// Direct move from a VSX register to a GPR
 181       MFVSR,
 182
 183       /// Direct move from a GPR to a VSX register (algebraic)
 184       MTVSRA,
 185
 186       /// Direct move from a GPR to a VSX register (zero)
 187       MTVSRZ,
 188
 189       /// Extract a subvector from signed integer vector and convert to FP.
 190       /// It is primarily used to convert a (widened) illegal integer vector
 191       /// type to a legal floating point vector type.
 192       /// For example v2i32 -> widened to v4i32 -> v2f64
 193       SINT_VEC_TO_FP,
 194
 195       /// Extract a subvector from unsigned integer vector and convert to FP.
 196       /// As with SINT_VEC_TO_FP, used for converting illegal types.
 197       UINT_VEC_TO_FP,
 198
 199       // FIXME: Remove these once the ANDI glue bug is fixed:
 200       /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
 201       /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
 202       /// implement truncation of i32 or i64 to i1.
 203       ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
 204
 205       // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
 206       // target (returns (Lo, Hi)). It takes a chain operand.
 207       READ_TIME_BASE,
 208
 209       // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
 210       EH_SJLJ_SETJMP,
 211
 212       // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
 213       EH_SJLJ_LONGJMP,
 214
 215       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
 216       /// instructions.  For lack of better number, we use the opcode number
 217       /// encoding for the OPC field to identify the compare.  For example, 838
 218       /// is VCMPGTSH.
 219       VCMP,
 220
 221       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
 222       /// altivec VCMP*o instructions.  For lack of better number, we use the
 223       /// opcode number encoding for the OPC field to identify the compare.  For
 224       /// example, 838 is VCMPGTSH.
 225       VCMPo,
 226
 227       /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
 228       /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
 229       /// condition register to branch on, OPC is the branch opcode to use (e.g.
 230       /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
 231       /// an optional input flag argument.
 232       COND_BRANCH,
 233
 234       /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
 235       /// loops.
 236       BDNZ, BDZ,
 237
 238       /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
 239       /// towards zero.  Used only as part of the long double-to-int
 240       /// conversion sequence.
 241       FADDRTZ,
 242
 243       /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
 244       MFFS,
 245
 246       /// TC_RETURN - A tail call return.
 247       ///   operand #0 chain
 248       ///   operand #1 callee (register or absolute)
 249       ///   operand #2 stack adjustment
 250       ///   operand #3 optional in flag
 251       TC_RETURN,
 252
 253       /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
 254       CR6SET,
 255       CR6UNSET,
 256
 257       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
 258       /// on PPC32.
 259       PPC32_GOT,
 260
 261       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
 262       /// local dynamic TLS on PPC32.
 263       PPC32_PICGOT,
 264
 265       /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
 266       /// TLS model, produces an ADDIS8 instruction that adds the GOT
 267       /// base to sym\@got\@tprel\@ha.
 268       ADDIS_GOT_TPREL_HA,
 269
 270       /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
 271       /// TLS model, produces a LD instruction with base register G8RReg
 272       /// and offset sym\@got\@tprel\@l.  This completes the addition that
 273       /// finds the offset of "sym" relative to the thread pointer.
 274       LD_GOT_TPREL_L,
 275
 276       /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
 277       /// model, produces an ADD instruction that adds the contents of
 278       /// G8RReg to the thread pointer.  Symbol contains a relocation
 279       /// sym\@tls which is to be replaced by the thread pointer and
 280       /// identifies to the linker that the instruction is part of a
 281       /// TLS sequence.
 282       ADD_TLS,
 283
 284       /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
 285       /// model, produces an ADDIS8 instruction that adds the GOT base
 286       /// register to sym\@got\@tlsgd\@ha.
 287       ADDIS_TLSGD_HA,
 288
 289       /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
 290       /// model, produces an ADDI8 instruction that adds G8RReg to
 291       /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
 292       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 293       ADDI_TLSGD_L,
 294
 295       /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
 296       /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
 297       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 298       GET_TLS_ADDR,
 299
 300       /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
 301       /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
 302       /// register assignment.
 303       ADDI_TLSGD_L_ADDR,
 304
 305       /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
 306       /// model, produces an ADDIS8 instruction that adds the GOT base
 307       /// register to sym\@got\@tlsld\@ha.
 308       ADDIS_TLSLD_HA,
 309
 310       /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
 311       /// model, produces an ADDI8 instruction that adds G8RReg to
 312       /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
 313       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 314       ADDI_TLSLD_L,
 315
 316       /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
 317       /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
 318       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 319       GET_TLSLD_ADDR,
 320
 321       /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
 322       /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
 323       /// following register assignment.
 324       ADDI_TLSLD_L_ADDR,
 325
 326       /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
 327       /// model, produces an ADDIS8 instruction that adds X3 to
 328       /// sym\@dtprel\@ha.
 329       ADDIS_DTPREL_HA,
 330
 331       /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
 332       /// model, produces an ADDI8 instruction that adds G8RReg to
 333       /// sym\@got\@dtprel\@l.
 334       ADDI_DTPREL_L,
 335
 336       /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
 337       /// during instruction selection to optimize a BUILD_VECTOR into
 338       /// operations on splats.  This is necessary to avoid losing these
 339       /// optimizations due to constant folding.
 340       VADD_SPLAT,
 341
 342       /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
 343       /// operand identifies the operating system entry point.
 344       SC,
 345
 346       /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
 347       CLRBHRB,
 348
 349       /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
 350       /// history rolling buffer entry.
 351       MFBHRBE,
 352
 353       /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
 354       RFEBB,
 355
 356       /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
 357       /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
 358       /// or stxvd2x instruction.  The chain is necessary because the
 359       /// sequence replaces a load and needs to provide the same number
 360       /// of outputs.
 361       XXSWAPD,
 362
 363       /// An SDNode for swaps that are not associated with any loads/stores
 364       /// and thereby have no chain.
 365       SWAP_NO_CHAIN,
 366
 367       /// QVFPERM = This corresponds to the QPX qvfperm instruction.
 368       QVFPERM,
 369
 370       /// QVGPCI = This corresponds to the QPX qvgpci instruction.
 371       QVGPCI,
 372
 373       /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
 374       QVALIGNI,
 375
 376       /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
 377       QVESPLATI,
 378
 379       /// QBFLT = Access the underlying QPX floating-point boolean
 380       /// representation.
 381       QBFLT,
 382
 383       /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
 384       /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
 385       /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
 386       /// i32.
 387       STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 388
 389       /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
 390       /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
 391       /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
 392       /// or i32.
 393       LBRX,
 394
 395       /// STFIWX - The STFIWX instruction.  The first operand is an input token
 396       /// chain, then an f64 value to store, then an address to store it to.
 397       STFIWX,
 398
 399       /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
 400       /// load which sign-extends from a 32-bit integer value into the
 401       /// destination 64-bit register.
 402       LFIWAX,
 403
 404       /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
 405       /// load which zero-extends from a 32-bit integer value into the
 406       /// destination 64-bit register.
 407       LFIWZX,
 408
 409       /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
 410       /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
 411       /// This can be used for converting loaded integers to floating point.
 412       LXSIZX,
 413
 414       /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
 415       /// chain, then an f64 value to store, then an address to store it to,
 416       /// followed by a byte-width for the store.
 417       STXSIX,
 418
 419       /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
 420       /// Maps directly to an lxvd2x instruction that will be followed by
 421       /// an xxswapd.
 422       LXVD2X,
 423
 424       /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
 425       /// Maps directly to an stxvd2x instruction that will be preceded by
 426       /// an xxswapd.
 427       STXVD2X,
 428
 429       /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
 430       /// The 4xf32 load used for v4i1 constants.
 431       QVLFSb,
 432
 433       /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
 434       /// except they ensure that the compare input is zero-extended for
 435       /// sub-word versions because the atomic loads zero-extend.
 436       ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
 437
 438       /// GPRC = TOC_ENTRY GA, TOC
 439       /// Loads the entry for GA from the TOC, where the TOC base is given by
 440       /// the last operand.
 441       TOC_ENTRY
 442     };
 443
 444   } // end namespace PPCISD
 445
 446   /// Define some predicates that are used for node matching.
 447   namespace PPC {
 448
 449     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
 450     /// VPKUHUM instruction.
 451     bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 452                               SelectionDAG &DAG);
 453
 454     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
 455     /// VPKUWUM instruction.
 456     bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 457                               SelectionDAG &DAG);
 458
 459     /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
 460     /// VPKUDUM instruction.
 461     bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 462                               SelectionDAG &DAG);
 463
 464     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
 465     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
 466     bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 467                             unsigned ShuffleKind, SelectionDAG &DAG);
 468
 469     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
 470     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
 471     bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 472                             unsigned ShuffleKind, SelectionDAG &DAG);
 473
 474     /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
 475     /// a VMRGEW or VMRGOW instruction
 476     bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
 477                              unsigned ShuffleKind, SelectionDAG &DAG);
 478     /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
 479     /// for a XXSLDWI instruction.
 480     bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 481                               bool &Swap, bool IsLE);
 482
 483     /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
 484     /// for a XXBRH instruction.
 485     bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
 486
 487     /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
 488     /// for a XXBRW instruction.
 489     bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
 490
 491     /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
 492     /// for a XXBRD instruction.
 493     bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
 494
 495     /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
 496     /// for a XXBRQ instruction.
 497     bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
 498
 499     /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
 500     /// for a XXPERMDI instruction.
 501     bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 502                               bool &Swap, bool IsLE);
 503
 504     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
 505     /// shift amount, otherwise return -1.
 506     int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
 507                             SelectionDAG &DAG);
 508
 509     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 510     /// specifies a splat of a single element that is suitable for input to
 511     /// VSPLTB/VSPLTH/VSPLTW.
 512     bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
 513
 514     /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
 515     /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
 516     /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
 517     /// vector into the other. This function will also set a couple of
 518     /// output parameters for how much the source vector needs to be shifted and
 519     /// what byte number needs to be specified for the instruction to put the
 520     /// element in the desired location of the target vector.
 521     bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 522                          unsigned &InsertAtByte, bool &Swap, bool IsLE);
 523
 524     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 525     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
 526     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
 527
 528     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
 529     /// formed by using a vspltis[bhw] instruction of the specified element
 530     /// size, return the constant being splatted.  The ByteSize field indicates
 531     /// the number of bytes of each element [124] -> [bhw].
 532     SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
 533
 534     /// If this is a qvaligni shuffle mask, return the shift
 535     /// amount, otherwise return -1.
 536     int isQVALIGNIShuffleMask(SDNode *N);
 537
 538   } // end namespace PPC
 539
 540   class PPCTargetLowering : public TargetLowering {
 541     const PPCSubtarget &Subtarget;
 542
 543   public:
 544     explicit PPCTargetLowering(const PPCTargetMachine &TM,
 545                                const PPCSubtarget &STI);
 546
 547     /// getTargetNodeName() - This method returns the name of a target specific
 548     /// DAG node.
 549     const char *getTargetNodeName(unsigned Opcode) const override;
 550
 551     /// getPreferredVectorAction - The code we generate when vector types are
 552     /// legalized by promoting the integer element type is often much worse
 553     /// than code we generate if we widen the type for applicable vector types.
 554     /// The issue with promoting is that the vector is scalaraized, individual
 555     /// elements promoted and then the vector is rebuilt. So say we load a pair
 556     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
 557     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
 558     /// then the VPERM for the shuffle. All in all a very slow sequence.
 559     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
 560       const override {
 561       if (VT.getScalarSizeInBits() % 8 == 0)
 562         return TypeWidenVector;
 563       return TargetLoweringBase::getPreferredVectorAction(VT);
 564     }
 565
 566     bool useSoftFloat() const override;
 567
 568     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
 569       return MVT::i32;
 570     }
 571
 572     bool isCheapToSpeculateCttz() const override {
 573       return true;
 574     }
 575
 576     bool isCheapToSpeculateCtlz() const override {
 577       return true;
 578     }
 579
 580     bool isCtlzFast() const override {
 581       return true;
 582     }
 583
 584     bool hasAndNotCompare(SDValue) const override {
 585       return true;
 586     }
 587
 588     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 589       return VT.isScalarInteger();
 590     }
 591
 592     bool supportSplitCSR(MachineFunction *MF) const override {
 593       return
 594         MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 595         MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 596     }
 597
 598     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 599
 600     void insertCopiesSplitCSR(
 601       MachineBasicBlock *Entry,
 602       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 603
 604     /// getSetCCResultType - Return the ISD::SETCC ValueType
 605     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 606                            EVT VT) const override;
 607
 608     /// Return true if target always beneficiates from combining into FMA for a
 609     /// given value type. This must typically return false on targets where FMA
 610     /// takes more cycles to execute than FADD.
 611     bool enableAggressiveFMAFusion(EVT VT) const override;
 612
 613     /// getPreIndexedAddressParts - returns true by value, base pointer and
 614     /// offset pointer and addressing mode by reference if the node's address
 615     /// can be legally represented as pre-indexed load / store address.
 616     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
 617                                    SDValue &Offset,
 618                                    ISD::MemIndexedMode &AM,
 619                                    SelectionDAG &DAG) const override;
 620
 621     /// SelectAddressRegReg - Given the specified addressed, check to see if it
 622     /// can be represented as an indexed [r+r] operation.  Returns false if it
 623     /// can be more efficiently represented with [r+imm].
 624     bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
 625                              SelectionDAG &DAG) const;
 626
 627     /// SelectAddressRegImm - Returns true if the address N can be represented
 628     /// by a base register plus a signed 16-bit displacement [r+imm], and if it
 629     /// is not better represented as reg+reg.  If Aligned is true, only accept
 630     /// displacements suitable for STD and friends, i.e. multiples of 4.
 631     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
 632                              SelectionDAG &DAG, unsigned Alignment) const;
 633
 634     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
 635     /// represented as an indexed [r+r] operation.
 636     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
 637                                  SelectionDAG &DAG) const;
 638
 639     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 640
 641     /// LowerOperation - Provide custom lowering hooks for some operations.
 642     ///
 643     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 644
 645     /// ReplaceNodeResults - Replace the results of node with an illegal result
 646     /// type with new values built out of custom code.
 647     ///
 648     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 649                             SelectionDAG &DAG) const override;
 650
 651     SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 652     SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 653
 654     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 655
 656     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 657                           std::vector<SDNode *> *Created) const override;
 658
 659     unsigned getRegisterByName(const char* RegName, EVT VT,
 660                                SelectionDAG &DAG) const override;
 661
 662     void computeKnownBitsForTargetNode(const SDValue Op,
 663                                        KnownBits &Known,
 664                                        const APInt &DemandedElts,
 665                                        const SelectionDAG &DAG,
 666                                        unsigned Depth = 0) const override;
 667
 668     unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
 669
 670     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 671       return true;
 672     }
 673
 674     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 675                                   AtomicOrdering Ord) const override;
 676     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 677                                    AtomicOrdering Ord) const override;
 678
 679     MachineBasicBlock *
 680     EmitInstrWithCustomInserter(MachineInstr &MI,
 681                                 MachineBasicBlock *MBB) const override;
 682     MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
 683                                         MachineBasicBlock *MBB,
 684                                         unsigned AtomicSize,
 685                                         unsigned BinOpcode,
 686                                         unsigned CmpOpcode = 0,
 687                                         unsigned CmpPred = 0) const;
 688     MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
 689                                                 MachineBasicBlock *MBB,
 690                                                 bool is8bit,
 691                                                 unsigned Opcode,
 692                                                 unsigned CmpOpcode = 0,
 693                                                 unsigned CmpPred = 0) const;
 694
 695     MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
 696                                         MachineBasicBlock *MBB) const;
 697
 698     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
 699                                          MachineBasicBlock *MBB) const;
 700
 701     ConstraintType getConstraintType(StringRef Constraint) const override;
 702
 703     /// Examine constraint string and operand type and determine a weight value.
 704     /// The operand object must already have been set up with the operand type.
 705     ConstraintWeight getSingleConstraintMatchWeight(
 706       AsmOperandInfo &info, const char *constraint) const override;
 707
 708     std::pair<unsigned, const TargetRegisterClass *>
 709     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 710                                  StringRef Constraint, MVT VT) const override;
 711
 712     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 713     /// function arguments in the caller parameter area.  This is the actual
 714     /// alignment, not its logarithm.
 715     unsigned getByValTypeAlignment(Type *Ty,
 716                                    const DataLayout &DL) const override;
 717
 718     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 719     /// vector.  If it is invalid, don't add anything to Ops.
 720     void LowerAsmOperandForConstraint(SDValue Op,
 721                                       std::string &Constraint,
 722                                       std::vector<SDValue> &Ops,
 723                                       SelectionDAG &DAG) const override;
 724
 725     unsigned
 726     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 727       if (ConstraintCode == "es")
 728         return InlineAsm::Constraint_es;
 729       else if (ConstraintCode == "o")
 730         return InlineAsm::Constraint_o;
 731       else if (ConstraintCode == "Q")
 732         return InlineAsm::Constraint_Q;
 733       else if (ConstraintCode == "Z")
 734         return InlineAsm::Constraint_Z;
 735       else if (ConstraintCode == "Zy")
 736         return InlineAsm::Constraint_Zy;
 737       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 738     }
 739
 740     /// isLegalAddressingMode - Return true if the addressing mode represented
 741     /// by AM is legal for this target, for a load/store of the specified type.
 742     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 743                                Type *Ty, unsigned AS,
 744                                Instruction *I = nullptr) const override;
 745
 746     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 747     /// icmp immediate, that is the target has icmp instructions which can
 748     /// compare a register against the immediate without having to materialize
 749     /// the immediate into a register.
 750     bool isLegalICmpImmediate(int64_t Imm) const override;
 751
 752     /// isLegalAddImmediate - Return true if the specified immediate is legal
 753     /// add immediate, that is the target has add instructions which can
 754     /// add a register and the immediate without having to materialize
 755     /// the immediate into a register.
 756     bool isLegalAddImmediate(int64_t Imm) const override;
 757
 758     /// isTruncateFree - Return true if it's free to truncate a value of
 759     /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
 760     /// register X1 to i32 by referencing its sub-register R1.
 761     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 762     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 763
 764     bool isZExtFree(SDValue Val, EVT VT2) const override;
 765
 766     bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
 767
 768     /// \brief Returns true if it is beneficial to convert a load of a constant
 769     /// to just the constant itself.
 770     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 771                                            Type *Ty) const override;
 772
 773     bool convertSelectOfConstantsToMath(EVT VT) const override {
 774       return true;
 775     }
 776
 777     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 778
 779     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 780                             const CallInst &I,
 781                             MachineFunction &MF,
 782                             unsigned Intrinsic) const override;
 783
 784     /// getOptimalMemOpType - Returns the target specific optimal type for load
 785     /// and store operations as a result of memset, memcpy, and memmove
 786     /// lowering. If DstAlign is zero that means it's safe to destination
 787     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 788     /// means there isn't a need to check it against alignment requirement,
 789     /// probably because the source does not need to be loaded. If 'IsMemset' is
 790     /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
 791     /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
 792     /// source is constant so it does not need to be loaded.
 793     /// It returns EVT::Other if the type should be determined using generic
 794     /// target-independent logic.
 795     EVT
 796     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
 797                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
 798                         MachineFunction &MF) const override;
 799
 800     /// Is unaligned memory access allowed for the given type, and is it fast
 801     /// relative to software emulation.
 802     bool allowsMisalignedMemoryAccesses(EVT VT,
 803                                         unsigned AddrSpace,
 804                                         unsigned Align = 1,
 805                                         bool *Fast = nullptr) const override;
 806
 807     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 808     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 809     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 810     /// expanded to fmul + fadd.
 811     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 812
 813     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 814
 815     // Should we expand the build vector with shuffles?
 816     bool
 817     shouldExpandBuildVectorWithShuffles(EVT VT,
 818                                         unsigned DefinedValues) const override;
 819
 820     /// createFastISel - This method returns a target-specific FastISel object,
 821     /// or null if the target does not support "fast" instruction selection.
 822     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
 823                              const TargetLibraryInfo *LibInfo) const override;
 824
 825     /// \brief Returns true if an argument of type Ty needs to be passed in a
 826     /// contiguous block of registers in calling convention CallConv.
 827     bool functionArgumentNeedsConsecutiveRegisters(
 828       Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
 829       // We support any array type as "consecutive" block in the parameter
 830       // save area.  The element type defines the alignment requirement and
 831       // whether the argument should go in GPRs, FPRs, or VRs if available.
 832       //
 833       // Note that clang uses this capability both to implement the ELFv2
 834       // homogeneous float/vector aggregate ABI, and to avoid having to use
 835       // "byval" when passing aggregates that might fully fit in registers.
 836       return Ty->isArrayTy();
 837     }
 838
 839     /// If a physical register, this returns the register that receives the
 840     /// exception address on entry to an EH pad.
 841     unsigned
 842     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 843
 844     /// If a physical register, this returns the register that receives the
 845     /// exception typeid on entry to a landing pad.
 846     unsigned
 847     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 848
 849     /// Override to support customized stack guard loading.
 850     bool useLoadStackGuardNode() const override;
 851     void insertSSPDeclarations(Module &M) const override;
 852
 853     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 854
 855     unsigned getJumpTableEncoding() const override;
 856     bool isJumpTableRelative() const override;
 857     SDValue getPICJumpTableRelocBase(SDValue Table,
 858                                      SelectionDAG &DAG) const override;
 859     const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
 860                                                unsigned JTI,
 861                                                MCContext &Ctx) const override;
 862
 863   private:
 864     struct ReuseLoadInfo {
 865       SDValue Ptr;
 866       SDValue Chain;
 867       SDValue ResChain;
 868       MachinePointerInfo MPI;
 869       bool IsDereferenceable = false;
 870       bool IsInvariant = false;
 871       unsigned Alignment = 0;
 872       AAMDNodes AAInfo;
 873       const MDNode *Ranges = nullptr;
 874
 875       ReuseLoadInfo() = default;
 876
 877       MachineMemOperand::Flags MMOFlags() const {
 878         MachineMemOperand::Flags F = MachineMemOperand::MONone;
 879         if (IsDereferenceable)
 880           F |= MachineMemOperand::MODereferenceable;
 881         if (IsInvariant)
 882           F |= MachineMemOperand::MOInvariant;
 883         return F;
 884       }
 885     };
 886
 887     bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
 888                              SelectionDAG &DAG,
 889                              ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
 890     void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
 891                          SelectionDAG &DAG) const;
 892
 893     void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
 894                                 SelectionDAG &DAG, const SDLoc &dl) const;
 895     SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
 896                                      const SDLoc &dl) const;
 897
 898     bool directMoveIsProfitable(const SDValue &Op) const;
 899     SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
 900                                      const SDLoc &dl) const;
 901
 902     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
 903     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
 904
 905     bool
 906     IsEligibleForTailCallOptimization(SDValue Callee,
 907                                       CallingConv::ID CalleeCC,
 908                                       bool isVarArg,
 909                                       const SmallVectorImpl<ISD::InputArg> &Ins,
 910                                       SelectionDAG& DAG) const;
 911
 912     bool
 913     IsEligibleForTailCallOptimization_64SVR4(
 914                                     SDValue Callee,
 915                                     CallingConv::ID CalleeCC,
 916                                     ImmutableCallSite CS,
 917                                     bool isVarArg,
 918                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 919                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 920                                     SelectionDAG& DAG) const;
 921
 922     SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
 923                                          SDValue Chain, SDValue &LROpOut,
 924                                          SDValue &FPOpOut,
 925                                          const SDLoc &dl) const;
 926
 927     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 928     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 929     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 930     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 931     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 932     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 933     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 934     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 935     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 936     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 937     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 938     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 939     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
 940     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
 941     SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
 942     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 943     SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
 944     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
 945     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 946     SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
 947     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 948     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
 949                            const SDLoc &dl) const;
 950     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 951     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 952     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
 953     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
 954     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
 955     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 956     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 957     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 958     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 959     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 960     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
 961     SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
 962     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
 963     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
 964     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 965     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 966     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
 967
 968     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
 969     SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
 970
 971     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 972                             CallingConv::ID CallConv, bool isVarArg,
 973                             const SmallVectorImpl<ISD::InputArg> &Ins,
 974                             const SDLoc &dl, SelectionDAG &DAG,
 975                             SmallVectorImpl<SDValue> &InVals) const;
 976     SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
 977                        bool isTailCall, bool isVarArg, bool isPatchPoint,
 978                        bool hasNest, SelectionDAG &DAG,
 979                        SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
 980                        SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
 981                        SDValue &Callee, int SPDiff, unsigned NumBytes,
 982                        const SmallVectorImpl<ISD::InputArg> &Ins,
 983                        SmallVectorImpl<SDValue> &InVals,
 984                        ImmutableCallSite CS) const;
 985
 986     SDValue
 987     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 988                          const SmallVectorImpl<ISD::InputArg> &Ins,
 989                          const SDLoc &dl, SelectionDAG &DAG,
 990                          SmallVectorImpl<SDValue> &InVals) const override;
 991
 992     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 993                       SmallVectorImpl<SDValue> &InVals) const override;
 994
 995     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
 996                         bool isVarArg,
 997                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 998                         LLVMContext &Context) const override;
 999
1000     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1001                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1002                         const SmallVectorImpl<SDValue> &OutVals,
1003                         const SDLoc &dl, SelectionDAG &DAG) const override;
1004
1005     SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1006                               SelectionDAG &DAG, SDValue ArgVal,
1007                               const SDLoc &dl) const;
1008
1009     SDValue LowerFormalArguments_Darwin(
1010         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1011         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1012         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1013     SDValue LowerFormalArguments_64SVR4(
1014         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1015         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1016         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1017     SDValue LowerFormalArguments_32SVR4(
1018         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1019         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1020         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1021
1022     SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1023                                        SDValue CallSeqStart,
1024                                        ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1025                                        const SDLoc &dl) const;
1026
1027     SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1028                              CallingConv::ID CallConv, bool isVarArg,
1029                              bool isTailCall, bool isPatchPoint,
1030                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1031                              const SmallVectorImpl<SDValue> &OutVals,
1032                              const SmallVectorImpl<ISD::InputArg> &Ins,
1033                              const SDLoc &dl, SelectionDAG &DAG,
1034                              SmallVectorImpl<SDValue> &InVals,
1035                              ImmutableCallSite CS) const;
1036     SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1037                              CallingConv::ID CallConv, bool isVarArg,
1038                              bool isTailCall, bool isPatchPoint,
1039                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1040                              const SmallVectorImpl<SDValue> &OutVals,
1041                              const SmallVectorImpl<ISD::InputArg> &Ins,
1042                              const SDLoc &dl, SelectionDAG &DAG,
1043                              SmallVectorImpl<SDValue> &InVals,
1044                              ImmutableCallSite CS) const;
1045     SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1046                              CallingConv::ID CallConv, bool isVarArg,
1047                              bool isTailCall, bool isPatchPoint,
1048                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1049                              const SmallVectorImpl<SDValue> &OutVals,
1050                              const SmallVectorImpl<ISD::InputArg> &Ins,
1051                              const SDLoc &dl, SelectionDAG &DAG,
1052                              SmallVectorImpl<SDValue> &InVals,
1053                              ImmutableCallSite CS) const;
1054
1055     SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1056     SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1057
1058     SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1059     SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1060     SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1061     SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1062     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1063     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1064     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1065
1066     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1067     /// SETCC with integer subtraction when (1) there is a legal way of doing it
1068     /// (2) keeping the result of comparison in GPR has performance benefit.
1069     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1070
1071     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1072                             int &RefinementSteps, bool &UseOneConstNR,
1073                             bool Reciprocal) const override;
1074     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1075                              int &RefinementSteps) const override;
1076     unsigned combineRepeatedFPDivisors() const override;
1077
1078     CCAssignFn *useFastISelCCs(unsigned Flag) const;
1079
1080     SDValue
1081     combineElementTruncationToVectorTruncation(SDNode *N,
1082                                                DAGCombinerInfo &DCI) const;
1083
1084     /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1085     /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1086     /// essentially any shuffle of v8i16 vectors that just inserts one element
1087     /// from one vector into the other.
1088     SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1089
1090     /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1091     /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1092     /// essentially v16i8 vector version of VINSERTH.
1093     SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1094
1095     // Return whether the call instruction can potentially be optimized to a
1096     // tail call. This will cause the optimizers to attempt to move, or
1097     // duplicate return instructions to help enable tail call optimizations.
1098     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1099   }; // end class PPCTargetLowering
1100
1101   namespace PPC {
1102
1103     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1104                              const TargetLibraryInfo *LibInfo);
1105
1106   } // end namespace PPC
1107
1108   bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1109                                   CCValAssign::LocInfo &LocInfo,
1110                                   ISD::ArgFlagsTy &ArgFlags,
1111                                   CCState &State);
1112
1113   bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1114                                          MVT &LocVT,
1115                                          CCValAssign::LocInfo &LocInfo,
1116                                          ISD::ArgFlagsTy &ArgFlags,
1117                                          CCState &State);
1118
1119   bool
1120   CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
1121                                                  MVT &LocVT,
1122                                                  CCValAssign::LocInfo &LocInfo,
1123                                                  ISD::ArgFlagsTy &ArgFlags,
1124                                                  CCState &State);
1125
1126   bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1127                                            MVT &LocVT,
1128                                            CCValAssign::LocInfo &LocInfo,
1129                                            ISD::ArgFlagsTy &ArgFlags,
1130                                            CCState &State);
1131
1132   bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1133   bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1134
1135 } // end namespace llvm
1136
1137 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H