[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / fcvtzs-diagnostics.s
blobd0c50c61b0460982326ed2ce6ea7cd3e2466ace4
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 fcvtzs z0.h, p0/m, z0.s
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
5 // CHECK-NEXT: fcvtzs z0.h, p0/m, z0.s
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 fcvtzs z0.h, p0/m, z0.d
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
10 // CHECK-NEXT: fcvtzs z0.h, p0/m, z0.d
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14 // --------------------------------------------------------------------------//
15 // error: invalid restricted predicate register, expected p0..p7 (without element suffix)
17 fcvtzs z0.h, p8/m, z0.h
18 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
19 // CHECK-NEXT: fcvtzs z0.h, p8/m, z0.h
20 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: