[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / ldff1w.s
blob019974316260b768ea7976159835f282267319bd
1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
2 // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4 // RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
6 // RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
8 // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
10 ldff1w { z31.d }, p7/z, [sp]
11 // CHECK-INST: ldff1w { z31.d }, p7/z, [sp]
12 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5]
13 // CHECK-ERROR: instruction requires: sve
14 // CHECK-UNKNOWN: ff 7f 7f a5 <unknown>
16 ldff1w { z31.s }, p7/z, [sp]
17 // CHECK-INST: ldff1w { z31.s }, p7/z, [sp]
18 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5]
19 // CHECK-ERROR: instruction requires: sve
20 // CHECK-UNKNOWN: ff 7f 5f a5 <unknown>
22 ldff1w { z31.d }, p7/z, [sp, xzr, lsl #2]
23 // CHECK-INST: ldff1w { z31.d }, p7/z, [sp]
24 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5]
25 // CHECK-ERROR: instruction requires: sve
26 // CHECK-UNKNOWN: ff 7f 7f a5 <unknown>
28 ldff1w { z31.s }, p7/z, [sp, xzr, lsl #2]
29 // CHECK-INST: ldff1w { z31.s }, p7/z, [sp]
30 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5]
31 // CHECK-ERROR: instruction requires: sve
32 // CHECK-UNKNOWN: ff 7f 5f a5 <unknown>
34 ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]
35 // CHECK-INST: ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]
36 // CHECK-ENCODING: [0x00,0x60,0x40,0xa5]
37 // CHECK-ERROR: instruction requires: sve
38 // CHECK-UNKNOWN: 00 60 40 a5 <unknown>
40 ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
41 // CHECK-INST: ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
42 // CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
43 // CHECK-ERROR: instruction requires: sve
44 // CHECK-UNKNOWN: 00 60 60 a5 <unknown>
46 ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
47 // CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
48 // CHECK-ENCODING: [0x00,0x60,0x00,0x85]
49 // CHECK-ERROR: instruction requires: sve
50 // CHECK-UNKNOWN: 00 60 00 85 <unknown>
52 ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
53 // CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
54 // CHECK-ENCODING: [0x00,0x60,0x40,0x85]
55 // CHECK-ERROR: instruction requires: sve
56 // CHECK-UNKNOWN: 00 60 40 85 <unknown>
58 ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
59 // CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
60 // CHECK-ENCODING: [0xff,0x7f,0x3f,0x85]
61 // CHECK-ERROR: instruction requires: sve
62 // CHECK-UNKNOWN: ff 7f 3f 85 <unknown>
64 ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
65 // CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
66 // CHECK-ENCODING: [0xff,0x7f,0x7f,0x85]
67 // CHECK-ERROR: instruction requires: sve
68 // CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
70 ldff1w { z31.d }, p7/z, [sp, z31.d]
71 // CHECK-INST: ldff1w { z31.d }, p7/z, [sp, z31.d]
72 // CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
73 // CHECK-ERROR: instruction requires: sve
74 // CHECK-UNKNOWN: ff ff 5f c5 <unknown>
76 ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
77 // CHECK-INST: ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
78 // CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
79 // CHECK-ERROR: instruction requires: sve
80 // CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
82 ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
83 // CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
84 // CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
85 // CHECK-ERROR: instruction requires: sve
86 // CHECK-UNKNOWN: 55 75 15 c5 <unknown>
88 ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
89 // CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
90 // CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
91 // CHECK-ERROR: instruction requires: sve
92 // CHECK-UNKNOWN: 55 75 55 c5 <unknown>
94 ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
95 // CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
96 // CHECK-ENCODING: [0x00,0x60,0x20,0xc5]
97 // CHECK-ERROR: instruction requires: sve
98 // CHECK-UNKNOWN: 00 60 20 c5 <unknown>
100 ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
101 // CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
102 // CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
103 // CHECK-ERROR: instruction requires: sve
104 // CHECK-UNKNOWN: 00 60 60 c5 <unknown>
106 ldff1w { z31.s }, p7/z, [z31.s, #124]
107 // CHECK-INST: ldff1w { z31.s }, p7/z, [z31.s, #124]
108 // CHECK-ENCODING: [0xff,0xff,0x3f,0x85]
109 // CHECK-ERROR: instruction requires: sve
110 // CHECK-UNKNOWN: ff ff 3f 85 <unknown>
112 ldff1w { z0.s }, p0/z, [z0.s]
113 // CHECK-INST: ldff1w { z0.s }, p0/z, [z0.s]
114 // CHECK-ENCODING: [0x00,0xe0,0x20,0x85]
115 // CHECK-ERROR: instruction requires: sve
116 // CHECK-UNKNOWN: 00 e0 20 85 <unknown>
118 ldff1w { z31.d }, p7/z, [z31.d, #124]
119 // CHECK-INST: ldff1w { z31.d }, p7/z, [z31.d, #124]
120 // CHECK-ENCODING: [0xff,0xff,0x3f,0xc5]
121 // CHECK-ERROR: instruction requires: sve
122 // CHECK-UNKNOWN: ff ff 3f c5 <unknown>
124 ldff1w { z0.d }, p0/z, [z0.d]
125 // CHECK-INST: ldff1w { z0.d }, p0/z, [z0.d]
126 // CHECK-ENCODING: [0x00,0xe0,0x20,0xc5]
127 // CHECK-ERROR: instruction requires: sve
128 // CHECK-UNKNOWN: 00 e0 20 c5 <unknown>