[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / lslr-diagnostics.s
blob0b6037b1a6785665c3b0e1f39a8b8510e1396f87
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 lslr z0.b, p8/m, z0.b, z0.b
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
5 // CHECK-NEXT: lslr z0.b, p8/m, z0.b, z0.b
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 lslr z0.b, p0/m, z0.b, z0.d
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
10 // CHECK-NEXT: lslr z0.b, p0/m, z0.b, z0.d
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 lslr z0.h, p0/m, z0.h, z0.d
14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
15 // CHECK-NEXT: lslr z0.h, p0/m, z0.h, z0.d
16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 lslr z0.s, p0/m, z0.s, z0.d
19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
20 // CHECK-NEXT: lslr z0.s, p0/m, z0.s, z0.d
21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: