[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / mul-diagnostics.s
blob8254bbd7b3a624d2053ed5ce2619da5f545d891c
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
4 // ------------------------------------------------------------------------- //
5 // Invalid immediate range
7 mul z0.b, z0.b, #-129
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
9 // CHECK-NEXT: mul z0.b, z0.b, #-129
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
12 mul z0.b, z0.b, #128
13 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-128, 127].
14 // CHECK-NEXT: mul z0.b, z0.b, #128
15 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18 // ------------------------------------------------------------------------- //
19 // Tied operands must match
21 mul z0.b, z1.b, #0
22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
23 // CHECK-NEXT: mul z0.b, z1.b, #0
24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26 mul z0.b, p7/m, z1.b, z2.b
27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
28 // CHECK-NEXT: mul z0.b, p7/m, z1.b, z2.b
29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32 // ------------------------------------------------------------------------- //
33 // Invalid predicate
35 mul z0.b, p8/m, z0.b, z1.b
36 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
37 // CHECK-NEXT: mul z0.b, p8/m, z0.b, z1.b
38 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
41 // --------------------------------------------------------------------------//
42 // Negative tests for instructions that are incompatible with movprfx
44 movprfx z31.d, p0/z, z6.d
45 mul z31.d, z31.d, #127
46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
47 // CHECK-NEXT: mul z31.d, z31.d, #127
48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: