[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / rdffr-diagnostics.s
blobc5d80fee703f6d17841a9017ef2953afc0d3b356
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Invalid element widths
6 rdffr p0.h
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
8 // CHECK: rdffr p0.h
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 rdffr p0.s
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
13 // CHECK: rdffr p0.s
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 rdffr p0.d
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
18 // CHECK: rdffr p0.d
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: