[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE / uqdecp-diagnostics.s
blob7ee47a5efa789af039c566acd22c314091aaec78
1 // RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
3 uqdecp z0.d, p0.b
4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
5 // CHECK-NEXT: uqdecp z0.d, p0.b
6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
8 uqdecp z0.d, p0.q
9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
10 // CHECK-NEXT: uqdecp z0.d, p0.q
11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
14 // --------------------------------------------------------------------------//
15 // Negative tests for instructions that are incompatible with movprfx
17 movprfx z0.d, p0/z, z7.d
18 uqdecp z0.d, p0
19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
20 // CHECK-NEXT: uqdecp z0.d, p0
21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: