[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / flogb-diagnostics.s
blobddb8c4ff35b6a31cd21279fbb80f51bda2777900
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
4 // --------------------------------------------------------------------------//
5 // Invalid element width
7 flogb z0.b, p0/m, z0.b
8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
9 // CHECK-NEXT: flogb z0.b, p0/m, z0.b
10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
13 // --------------------------------------------------------------------------//
14 // Invalid predicate operation
16 flogb z0.s, p0/z, z0.s
17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
18 // CHECK-NEXT: flogb z0.s, p0/z, z0.s
19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
22 // --------------------------------------------------------------------------//
23 // Predicate not in restricted predicate range
25 flogb z0.s, p8/m, z0.s
26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
27 // CHECK-NEXT: flogb z0.s, p8/m, z0.s
28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: