[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / AArch64 / SVE2 / urecpe-diagnostics.s
blobf04538494cd6f05887685bdb36dbc1b8c44699e3
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
3 // ------------------------------------------------------------------------- //
4 // Invalid predicate
6 urecpe z0.s, p0/z, z1.s
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8 // CHECK-NEXT: urecpe z0.s, p0/z, z1.s
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 urecpe z0.s, p8/m, z1.s
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
13 // CHECK-NEXT: urecpe z0.s, p8/m, z1.s
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
17 // ------------------------------------------------------------------------- //
18 // Invalid element width
20 urecpe z0.b, p7/m, z1.b
21 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
22 // CHECK-NEXT: urecpe z0.b, p7/m, z1.b
23 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25 urecpe z0.h, p7/m, z1.h
26 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
27 // CHECK-NEXT: urecpe z0.h, p7/m, z1.h
28 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30 urecpe z0.d, p7/m, z1.d
31 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
32 // CHECK-NEXT: urecpe z0.d, p7/m, z1.d
33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: