[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / Mips / macro-sgt64.s
blobe878561b846053c1b773f7df134c1ca69b093f46
1 # RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
2 # RUN: | FileCheck --check-prefix=MIPS32 %s
3 # RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
4 # RUN: | FileCheck --check-prefix=MIPS64 %s
6 sgt $4, $5, 0x100000000
7 # MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
8 # MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
9 # MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
10 # MIPS64: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
11 sgtu $4, $5, 0x100000000
12 # MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 # MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
14 # MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
15 # MIPS64: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
16 sgt $4, 0x100000000
17 # MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 # MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
19 # MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
20 # MIPS64: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
21 sgtu $4, 0x100000000
22 # MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 # MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
24 # MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
25 # MIPS64: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]