[ARM] Better OR's for MVE compares
[llvm-core.git] / test / MC / Mips / micromips-dspr2 / invalid.s
blobe98e5ff2436f483e9bb1b18c792edc5e85fa965e
1 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1
2 # RUN: FileCheck %s < %t1
4 balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
5 balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
6 shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
7 shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
8 shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
9 shra_r.qb $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
10 shrl.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
11 shrl.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate
12 append $3, $4, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
13 append $3, $4, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate
14 mulsa.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
15 mulsa.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
16 mulsaq_s.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
17 mulsaq_s.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
18 # bposge32 is microMIPS DSP instruction but it is removed in Release 6
19 bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled