utils/TableGen/PseudoLoweringEmitter.cpp

   1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "CodeGenInstruction.h"
  11 #include "CodeGenTarget.h"
  12 #include "llvm/ADT/IndexedMap.h"
  13 #include "llvm/ADT/SmallVector.h"
  14 #include "llvm/ADT/StringMap.h"
  15 #include "llvm/Support/Debug.h"
  16 #include "llvm/Support/ErrorHandling.h"
  17 #include "llvm/TableGen/Error.h"
  18 #include "llvm/TableGen/Record.h"
  19 #include "llvm/TableGen/TableGenBackend.h"
  20 #include <vector>
  21 using namespace llvm;
  22
  23 #define DEBUG_TYPE "pseudo-lowering"
  24
  25 namespace {
  26 class PseudoLoweringEmitter {
  27   struct OpData {
  28     enum MapKind { Operand, Imm, Reg };
  29     MapKind Kind;
  30     union {
  31       unsigned Operand;   // Operand number mapped to.
  32       uint64_t Imm;       // Integer immedate value.
  33       Record *Reg;        // Physical register.
  34     } Data;
  35   };
  36   struct PseudoExpansion {
  37     CodeGenInstruction Source;  // The source pseudo instruction definition.
  38     CodeGenInstruction Dest;    // The destination instruction to lower to.
  39     IndexedMap<OpData> OperandMap;
  40
  41     PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
  42                     IndexedMap<OpData> &m) :
  43       Source(s), Dest(d), OperandMap(m) {}
  44   };
  45
  46   RecordKeeper &Records;
  47
  48   // It's overkill to have an instance of the full CodeGenTarget object,
  49   // but it loads everything on demand, not in the constructor, so it's
  50   // lightweight in performance, so it works out OK.
  51   CodeGenTarget Target;
  52
  53   SmallVector<PseudoExpansion, 64> Expansions;
  54
  55   unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
  56                                 CodeGenInstruction &Insn,
  57                                 IndexedMap<OpData> &OperandMap,
  58                                 unsigned BaseIdx);
  59   void evaluateExpansion(Record *Pseudo);
  60   void emitLoweringEmitter(raw_ostream &o);
  61 public:
  62   PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
  63
  64   /// run - Output the pseudo-lowerings.
  65   void run(raw_ostream &o);
  66 };
  67 } // End anonymous namespace
  68
  69 // FIXME: This pass currently can only expand a pseudo to a single instruction.
  70 //        The pseudo expansion really should take a list of dags, not just
  71 //        a single dag, so we can do fancier things.
  72
  73 unsigned PseudoLoweringEmitter::
  74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
  75                      IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
  76   unsigned OpsAdded = 0;
  77   for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
  78     if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
  79       // Physical register reference. Explicit check for the special case
  80       // "zero_reg" definition.
  81       if (DI->getDef()->isSubClassOf("Register") ||
  82           DI->getDef()->getName() == "zero_reg") {
  83         OperandMap[BaseIdx + i].Kind = OpData::Reg;
  84         OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
  85         ++OpsAdded;
  86         continue;
  87       }
  88
  89       // Normal operands should always have the same type, or we have a
  90       // problem.
  91       // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
  92       assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
  93       if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
  94         PrintFatalError(Rec->getLoc(),
  95                       "Pseudo operand type '" + DI->getDef()->getName() +
  96                       "' does not match expansion operand type '" +
  97                       Insn.Operands[BaseIdx + i].Rec->getName() + "'");
  98       // Source operand maps to destination operand. The Data element
  99       // will be filled in later, just set the Kind for now. Do it
 100       // for each corresponding MachineInstr operand, not just the first.
 101       for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
 102         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
 103       OpsAdded += Insn.Operands[i].MINumOperands;
 104     } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
 105       OperandMap[BaseIdx + i].Kind = OpData::Imm;
 106       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
 107       ++OpsAdded;
 108     } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
 109       // Just add the operands recursively. This is almost certainly
 110       // a constant value for a complex operand (> 1 MI operand).
 111       unsigned NewOps =
 112         addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
 113       OpsAdded += NewOps;
 114       // Since we added more than one, we also need to adjust the base.
 115       BaseIdx += NewOps - 1;
 116     } else
 117       llvm_unreachable("Unhandled pseudo-expansion argument type!");
 118   }
 119   return OpsAdded;
 120 }
 121
 122 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
 123   LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
 124
 125   // Validate that the result pattern has the corrent number and types
 126   // of arguments for the instruction it references.
 127   DagInit *Dag = Rec->getValueAsDag("ResultInst");
 128   assert(Dag && "Missing result instruction in pseudo expansion!");
 129   LLVM_DEBUG(dbgs() << "  Result: " << *Dag << "\n");
 130
 131   DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
 132   if (!OpDef)
 133     PrintFatalError(Rec->getLoc(), Rec->getName() +
 134                   " has unexpected operator type!");
 135   Record *Operator = OpDef->getDef();
 136   if (!Operator->isSubClassOf("Instruction"))
 137     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
 138                     "' is not an instruction!");
 139
 140   CodeGenInstruction Insn(Operator);
 141
 142   if (Insn.isCodeGenOnly || Insn.isPseudo)
 143     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
 144                     "' cannot be another pseudo instruction!");
 145
 146   if (Insn.Operands.size() != Dag->getNumArgs())
 147     PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
 148                     "' operand count mismatch");
 149
 150   unsigned NumMIOperands = 0;
 151   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
 152     NumMIOperands += Insn.Operands[i].MINumOperands;
 153   IndexedMap<OpData> OperandMap;
 154   OperandMap.grow(NumMIOperands);
 155
 156   addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
 157
 158   // If there are more operands that weren't in the DAG, they have to
 159   // be operands that have default values, or we have an error. Currently,
 160   // Operands that are a subclass of OperandWithDefaultOp have default values.
 161
 162   // Validate that each result pattern argument has a matching (by name)
 163   // argument in the source instruction, in either the (outs) or (ins) list.
 164   // Also check that the type of the arguments match.
 165   //
 166   // Record the mapping of the source to result arguments for use by
 167   // the lowering emitter.
 168   CodeGenInstruction SourceInsn(Rec);
 169   StringMap<unsigned> SourceOperands;
 170   for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
 171     SourceOperands[SourceInsn.Operands[i].Name] = i;
 172
 173   LLVM_DEBUG(dbgs() << "  Operand mapping:\n");
 174   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
 175     // We've already handled constant values. Just map instruction operands
 176     // here.
 177     if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
 178       continue;
 179     StringMap<unsigned>::iterator SourceOp =
 180       SourceOperands.find(Dag->getArgNameStr(i));
 181     if (SourceOp == SourceOperands.end())
 182       PrintFatalError(Rec->getLoc(),
 183                       "Pseudo output operand '" + Dag->getArgNameStr(i) +
 184                       "' has no matching source operand.");
 185     // Map the source operand to the destination operand index for each
 186     // MachineInstr operand.
 187     for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
 188       OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
 189         SourceOp->getValue();
 190
 191     LLVM_DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i
 192                       << "\n");
 193   }
 194
 195   Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
 196 }
 197
 198 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
 199   // Emit file header.
 200   emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
 201
 202   o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
 203     << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
 204     << "                            const MachineInstr *MI) {\n";
 205
 206   if (!Expansions.empty()) {
 207     o << "  switch (MI->getOpcode()) {\n"
 208       << "    default: return false;\n";
 209     for (auto &Expansion : Expansions) {
 210       CodeGenInstruction &Source = Expansion.Source;
 211       CodeGenInstruction &Dest = Expansion.Dest;
 212       o << "    case " << Source.Namespace << "::"
 213         << Source.TheDef->getName() << ": {\n"
 214         << "      MCInst TmpInst;\n"
 215         << "      MCOperand MCOp;\n"
 216         << "      TmpInst.setOpcode(" << Dest.Namespace << "::"
 217         << Dest.TheDef->getName() << ");\n";
 218
 219       // Copy the operands from the source instruction.
 220       // FIXME: Instruction operands with defaults values (predicates and cc_out
 221       //        in ARM, for example shouldn't need explicit values in the
 222       //        expansion DAG.
 223       unsigned MIOpNo = 0;
 224       for (const auto &DestOperand : Dest.Operands) {
 225         o << "      // Operand: " << DestOperand.Name << "\n";
 226         for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
 227           switch (Expansion.OperandMap[MIOpNo + i].Kind) {
 228             case OpData::Operand:
 229             o << "      lowerOperand(MI->getOperand("
 230               << Source.Operands[Expansion.OperandMap[MIOpNo].Data
 231               .Operand].MIOperandNo + i
 232               << "), MCOp);\n"
 233               << "      TmpInst.addOperand(MCOp);\n";
 234             break;
 235             case OpData::Imm:
 236             o << "      TmpInst.addOperand(MCOperand::createImm("
 237               << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
 238             break;
 239             case OpData::Reg: {
 240               Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
 241               o << "      TmpInst.addOperand(MCOperand::createReg(";
 242               // "zero_reg" is special.
 243               if (Reg->getName() == "zero_reg")
 244                 o << "0";
 245               else
 246                 o << Reg->getValueAsString("Namespace") << "::"
 247                   << Reg->getName();
 248               o << "));\n";
 249               break;
 250             }
 251           }
 252         }
 253         MIOpNo += DestOperand.MINumOperands;
 254       }
 255       if (Dest.Operands.isVariadic) {
 256         MIOpNo = Source.Operands.size() + 1;
 257         o << "      // variable_ops\n";
 258         o << "      for (unsigned i = " << MIOpNo
 259           << ", e = MI->getNumOperands(); i != e; ++i)\n"
 260           << "        if (lowerOperand(MI->getOperand(i), MCOp))\n"
 261           << "          TmpInst.addOperand(MCOp);\n";
 262       }
 263       o << "      EmitToStreamer(OutStreamer, TmpInst);\n"
 264         << "      break;\n"
 265         << "    }\n";
 266     }
 267     o << "  }\n  return true;";
 268   } else
 269     o << "  return false;";
 270
 271   o << "\n}\n\n";
 272 }
 273
 274 void PseudoLoweringEmitter::run(raw_ostream &o) {
 275   Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
 276   Record *InstructionClass = Records.getClass("Instruction");
 277   assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
 278   assert(InstructionClass && "Instruction class definition missing!");
 279
 280   std::vector<Record*> Insts;
 281   for (const auto &D : Records.getDefs()) {
 282     if (D.second->isSubClassOf(ExpansionClass) &&
 283         D.second->isSubClassOf(InstructionClass))
 284       Insts.push_back(D.second.get());
 285   }
 286
 287   // Process the pseudo expansion definitions, validating them as we do so.
 288   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
 289     evaluateExpansion(Insts[i]);
 290
 291   // Generate expansion code to lower the pseudo to an MCInst of the real
 292   // instruction.
 293   emitLoweringEmitter(o);
 294 }
 295
 296 namespace llvm {
 297
 298 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
 299   PseudoLoweringEmitter(RK).run(OS);
 300 }
 301
 302 } // End llvm namespace