?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[llvm-exegesis] Fix wrong index type.
[llvm-core.git] / utils / TableGen / X86RecognizableInstr.cpp
blob2f9b428b8cfe8bddee7845811798fbd735f29fda
1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisassemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22
23 using namespace llvm;
24 using namespace X86Disassembler;
25
26 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
27 /// Useful for switch statements and the like.
28 ///
29 /// @param init - A reference to the BitsInit to be decoded.
30 /// @return - The field, with the first bit in the BitsInit as the lowest
31 /// order bit.
32 static uint8_t byteFromBitsInit(BitsInit &init) {
33 int width = init.getNumBits();
34
35 assert(width <= 8 && "Field is too large for uint8_t!");
36
37 int index;
38 uint8_t mask = 0x01;
39
40 uint8_t ret = 0;
41
42 for (index = 0; index < width; index++) {
43 if (cast<BitInit>(init.getBit(index))->getValue())
44 ret |= mask;
45
46 mask <<= 1;
47 }
48
49 return ret;
50 }
51
52 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
53 /// name of the field.
54 ///
55 /// @param rec - The record from which to extract the value.
56 /// @param name - The name of the field in the record.
57 /// @return - The field, as translated by byteFromBitsInit().
58 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
59 BitsInit* bits = rec->getValueAsBitsInit(name);
60 return byteFromBitsInit(*bits);
61 }
62
63 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
64 const CodeGenInstruction &insn,
65 InstrUID uid) {
66 UID = uid;
67
68 Rec = insn.TheDef;
69 Name = Rec->getName();
70 Spec = &tables.specForUID(UID);
71
72 if (!Rec->isSubClassOf("X86Inst")) {
73 ShouldBeEmitted = false;
74 return;
75 }
76
77 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
78 OpMap = byteFromRec(Rec, "OpMapBits");
79 Opcode = byteFromRec(Rec, "Opcode");
80 Form = byteFromRec(Rec, "FormBits");
81 Encoding = byteFromRec(Rec, "OpEncBits");
82
83 OpSize = byteFromRec(Rec, "OpSizeBits");
84 AdSize = byteFromRec(Rec, "AdSizeBits");
85 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
86 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
87 VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix");
88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
95 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
96
97 Name = Rec->getName();
98
99 Operands = &insn.Operands.OperandList;
100
101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
102
103 EncodeRC = HasEVEX_B &&
104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
105
106 // Check for 64-bit inst which does not require REX
107 Is32Bit = false;
108 Is64Bit = false;
109 // FIXME: Is there some better way to check for In64BitMode?
110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
113 Predicates[i]->getName().find("In32Bit") != Name.npos) {
114 Is32Bit = true;
115 break;
116 }
117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
118 Is64Bit = true;
119 break;
120 }
121 }
122
123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
124 ShouldBeEmitted = false;
125 return;
126 }
127
128 // Special case since there is no attribute class for 64-bit and VEX
129 if (Name == "VMASKMOVDQU64") {
130 ShouldBeEmitted = false;
131 return;
132 }
133
134 ShouldBeEmitted = true;
135 }
136
137 void RecognizableInstr::processInstr(DisassemblerTables &tables,
138 const CodeGenInstruction &insn,
139 InstrUID uid)
140 {
141 // Ignore "asm parser only" instructions.
142 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
143 return;
144
145 RecognizableInstr recogInstr(tables, insn, uid);
146
147 if (recogInstr.shouldBeEmitted()) {
148 recogInstr.emitInstructionSpecifier();
149 recogInstr.emitDecodePath(tables);
150 }
151 }
152
153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
155 (HasEVEX_KZ ? n##_KZ : \
156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
157
158 InstructionContext RecognizableInstr::insnContext() const {
159 InstructionContext insnContext;
160
161 if (Encoding == X86Local::EVEX) {
162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
165 }
166 // VEX_L & VEX_W
167 if (!EncodeRC && HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 ||
168 VEX_WPrefix == X86Local::VEX_W1X)) {
169 if (OpPrefix == X86Local::PD)
170 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
171 else if (OpPrefix == X86Local::XS)
172 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
173 else if (OpPrefix == X86Local::XD)
174 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
175 else if (OpPrefix == X86Local::PS)
176 insnContext = EVEX_KB(IC_EVEX_L_W);
177 else {
178 errs() << "Instruction does not use a prefix: " << Name << "\n";
179 llvm_unreachable("Invalid prefix");
180 }
181 } else if (!EncodeRC && HasVEX_LPrefix) {
182 // VEX_L
183 if (OpPrefix == X86Local::PD)
184 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
185 else if (OpPrefix == X86Local::XS)
186 insnContext = EVEX_KB(IC_EVEX_L_XS);
187 else if (OpPrefix == X86Local::XD)
188 insnContext = EVEX_KB(IC_EVEX_L_XD);
189 else if (OpPrefix == X86Local::PS)
190 insnContext = EVEX_KB(IC_EVEX_L);
191 else {
192 errs() << "Instruction does not use a prefix: " << Name << "\n";
193 llvm_unreachable("Invalid prefix");
194 }
195 } else if (!EncodeRC && HasEVEX_L2Prefix &&
196 (VEX_WPrefix == X86Local::VEX_W1 ||
197 VEX_WPrefix == X86Local::VEX_W1X)) {
198 // EVEX_L2 & VEX_W
199 if (OpPrefix == X86Local::PD)
200 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
201 else if (OpPrefix == X86Local::XS)
202 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
203 else if (OpPrefix == X86Local::XD)
204 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
205 else if (OpPrefix == X86Local::PS)
206 insnContext = EVEX_KB(IC_EVEX_L2_W);
207 else {
208 errs() << "Instruction does not use a prefix: " << Name << "\n";
209 llvm_unreachable("Invalid prefix");
210 }
211 } else if (!EncodeRC && HasEVEX_L2Prefix) {
212 // EVEX_L2
213 if (OpPrefix == X86Local::PD)
214 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
215 else if (OpPrefix == X86Local::XD)
216 insnContext = EVEX_KB(IC_EVEX_L2_XD);
217 else if (OpPrefix == X86Local::XS)
218 insnContext = EVEX_KB(IC_EVEX_L2_XS);
219 else if (OpPrefix == X86Local::PS)
220 insnContext = EVEX_KB(IC_EVEX_L2);
221 else {
222 errs() << "Instruction does not use a prefix: " << Name << "\n";
223 llvm_unreachable("Invalid prefix");
224 }
225 }
226 else if (VEX_WPrefix == X86Local::VEX_W1 ||
227 VEX_WPrefix == X86Local::VEX_W1X) {
228 // VEX_W
229 if (OpPrefix == X86Local::PD)
230 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
231 else if (OpPrefix == X86Local::XS)
232 insnContext = EVEX_KB(IC_EVEX_W_XS);
233 else if (OpPrefix == X86Local::XD)
234 insnContext = EVEX_KB(IC_EVEX_W_XD);
235 else if (OpPrefix == X86Local::PS)
236 insnContext = EVEX_KB(IC_EVEX_W);
237 else {
238 errs() << "Instruction does not use a prefix: " << Name << "\n";
239 llvm_unreachable("Invalid prefix");
240 }
241 }
242 // No L, no W
243 else if (OpPrefix == X86Local::PD)
244 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
245 else if (OpPrefix == X86Local::XD)
246 insnContext = EVEX_KB(IC_EVEX_XD);
247 else if (OpPrefix == X86Local::XS)
248 insnContext = EVEX_KB(IC_EVEX_XS);
249 else if (OpPrefix == X86Local::PS)
250 insnContext = EVEX_KB(IC_EVEX);
251 else {
252 errs() << "Instruction does not use a prefix: " << Name << "\n";
253 llvm_unreachable("Invalid prefix");
254 }
255 /// eof EVEX
256 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
257 if (HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 ||
258 VEX_WPrefix == X86Local::VEX_W1X)) {
259 if (OpPrefix == X86Local::PD)
260 insnContext = IC_VEX_L_W_OPSIZE;
261 else if (OpPrefix == X86Local::XS)
262 insnContext = IC_VEX_L_W_XS;
263 else if (OpPrefix == X86Local::XD)
264 insnContext = IC_VEX_L_W_XD;
265 else if (OpPrefix == X86Local::PS)
266 insnContext = IC_VEX_L_W;
267 else {
268 errs() << "Instruction does not use a prefix: " << Name << "\n";
269 llvm_unreachable("Invalid prefix");
270 }
271 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
272 insnContext = IC_VEX_L_OPSIZE;
273 else if (OpPrefix == X86Local::PD && (VEX_WPrefix == X86Local::VEX_W1 ||
274 VEX_WPrefix == X86Local::VEX_W1X))
275 insnContext = IC_VEX_W_OPSIZE;
276 else if (OpPrefix == X86Local::PD)
277 insnContext = IC_VEX_OPSIZE;
278 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
279 insnContext = IC_VEX_L_XS;
280 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
281 insnContext = IC_VEX_L_XD;
282 else if ((VEX_WPrefix == X86Local::VEX_W1 ||
283 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XS)
284 insnContext = IC_VEX_W_XS;
285 else if ((VEX_WPrefix == X86Local::VEX_W1 ||
286 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XD)
287 insnContext = IC_VEX_W_XD;
288 else if ((VEX_WPrefix == X86Local::VEX_W1 ||
289 VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::PS)
290 insnContext = IC_VEX_W;
291 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
292 insnContext = IC_VEX_L;
293 else if (OpPrefix == X86Local::XD)
294 insnContext = IC_VEX_XD;
295 else if (OpPrefix == X86Local::XS)
296 insnContext = IC_VEX_XS;
297 else if (OpPrefix == X86Local::PS)
298 insnContext = IC_VEX;
299 else {
300 errs() << "Instruction does not use a prefix: " << Name << "\n";
301 llvm_unreachable("Invalid prefix");
302 }
303 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
304 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
305 insnContext = IC_64BIT_REXW_OPSIZE;
306 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
307 insnContext = IC_64BIT_REXW_ADSIZE;
308 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
309 insnContext = IC_64BIT_XD_OPSIZE;
310 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
311 insnContext = IC_64BIT_XS_OPSIZE;
312 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
313 insnContext = IC_64BIT_OPSIZE_ADSIZE;
314 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
315 insnContext = IC_64BIT_OPSIZE_ADSIZE;
316 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
317 insnContext = IC_64BIT_OPSIZE;
318 else if (AdSize == X86Local::AdSize32)
319 insnContext = IC_64BIT_ADSIZE;
320 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
321 insnContext = IC_64BIT_REXW_XS;
322 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
323 insnContext = IC_64BIT_REXW_XD;
324 else if (OpPrefix == X86Local::XD)
325 insnContext = IC_64BIT_XD;
326 else if (OpPrefix == X86Local::XS)
327 insnContext = IC_64BIT_XS;
328 else if (HasREX_WPrefix)
329 insnContext = IC_64BIT_REXW;
330 else
331 insnContext = IC_64BIT;
332 } else {
333 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
334 insnContext = IC_XD_OPSIZE;
335 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
336 insnContext = IC_XS_OPSIZE;
337 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
338 insnContext = IC_XD_ADSIZE;
339 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
340 insnContext = IC_XS_ADSIZE;
341 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
342 insnContext = IC_OPSIZE_ADSIZE;
343 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
344 insnContext = IC_OPSIZE_ADSIZE;
345 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
346 insnContext = IC_OPSIZE;
347 else if (AdSize == X86Local::AdSize16)
348 insnContext = IC_ADSIZE;
349 else if (OpPrefix == X86Local::XD)
350 insnContext = IC_XD;
351 else if (OpPrefix == X86Local::XS)
352 insnContext = IC_XS;
353 else
354 insnContext = IC;
355 }
356
357 return insnContext;
358 }
359
360 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
361 // The scaling factor for AVX512 compressed displacement encoding is an
362 // instruction attribute. Adjust the ModRM encoding type to include the
363 // scale for compressed displacement.
364 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0)
365 return;
366 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
367 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
368 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
369 "Invalid CDisp scaling");
370 }
371
372 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
373 unsigned &physicalOperandIndex,
374 unsigned numPhysicalOperands,
375 const unsigned *operandMapping,
376 OperandEncoding (*encodingFromString)
377 (const std::string&,
378 uint8_t OpSize)) {
379 if (optional) {
380 if (physicalOperandIndex >= numPhysicalOperands)
381 return;
382 } else {
383 assert(physicalOperandIndex < numPhysicalOperands);
384 }
385
386 while (operandMapping[operandIndex] != operandIndex) {
387 Spec->operands[operandIndex].encoding = ENCODING_DUP;
388 Spec->operands[operandIndex].type =
389 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
390 ++operandIndex;
391 }
392
393 StringRef typeName = (*Operands)[operandIndex].Rec->getName();
394
395 OperandEncoding encoding = encodingFromString(typeName, OpSize);
396 // Adjust the encoding type for an operand based on the instruction.
397 adjustOperandEncoding(encoding);
398 Spec->operands[operandIndex].encoding = encoding;
399 Spec->operands[operandIndex].type = typeFromString(typeName,
400 HasREX_WPrefix, OpSize);
401
402 ++operandIndex;
403 ++physicalOperandIndex;
404 }
405
406 void RecognizableInstr::emitInstructionSpecifier() {
407 Spec->name = Name;
408
409 Spec->insnContext = insnContext();
410
411 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
412
413 unsigned numOperands = OperandList.size();
414 unsigned numPhysicalOperands = 0;
415
416 // operandMapping maps from operands in OperandList to their originals.
417 // If operandMapping[i] != i, then the entry is a duplicate.
418 unsigned operandMapping[X86_MAX_OPERANDS];
419 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
420
421 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
422 if (!OperandList[operandIndex].Constraints.empty()) {
423 const CGIOperandList::ConstraintInfo &Constraint =
424 OperandList[operandIndex].Constraints[0];
425 if (Constraint.isTied()) {
426 operandMapping[operandIndex] = operandIndex;
427 operandMapping[Constraint.getTiedOperand()] = operandIndex;
428 } else {
429 ++numPhysicalOperands;
430 operandMapping[operandIndex] = operandIndex;
431 }
432 } else {
433 ++numPhysicalOperands;
434 operandMapping[operandIndex] = operandIndex;
435 }
436 }
437
438 #define HANDLE_OPERAND(class) \
439 handleOperand(false, \
440 operandIndex, \
441 physicalOperandIndex, \
442 numPhysicalOperands, \
443 operandMapping, \
444 class##EncodingFromString);
445
446 #define HANDLE_OPTIONAL(class) \
447 handleOperand(true, \
448 operandIndex, \
449 physicalOperandIndex, \
450 numPhysicalOperands, \
451 operandMapping, \
452 class##EncodingFromString);
453
454 // operandIndex should always be < numOperands
455 unsigned operandIndex = 0;
456 // physicalOperandIndex should always be < numPhysicalOperands
457 unsigned physicalOperandIndex = 0;
458
459 #ifndef NDEBUG
460 // Given the set of prefix bits, how many additional operands does the
461 // instruction have?
462 unsigned additionalOperands = 0;
463 if (HasVEX_4V)
464 ++additionalOperands;
465 if (HasEVEX_K)
466 ++additionalOperands;
467 #endif
468
469 switch (Form) {
470 default: llvm_unreachable("Unhandled form");
471 case X86Local::RawFrmSrc:
472 HANDLE_OPERAND(relocation);
473 return;
474 case X86Local::RawFrmDst:
475 HANDLE_OPERAND(relocation);
476 return;
477 case X86Local::RawFrmDstSrc:
478 HANDLE_OPERAND(relocation);
479 HANDLE_OPERAND(relocation);
480 return;
481 case X86Local::RawFrm:
482 // Operand 1 (optional) is an address or immediate.
483 assert(numPhysicalOperands <= 1 &&
484 "Unexpected number of operands for RawFrm");
485 HANDLE_OPTIONAL(relocation)
486 break;
487 case X86Local::RawFrmMemOffs:
488 // Operand 1 is an address.
489 HANDLE_OPERAND(relocation);
490 break;
491 case X86Local::AddRegFrm:
492 // Operand 1 is added to the opcode.
493 // Operand 2 (optional) is an address.
494 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
495 "Unexpected number of operands for AddRegFrm");
496 HANDLE_OPERAND(opcodeModifier)
497 HANDLE_OPTIONAL(relocation)
498 break;
499 case X86Local::MRMDestReg:
500 // Operand 1 is a register operand in the R/M field.
501 // - In AVX512 there may be a mask operand here -
502 // Operand 2 is a register operand in the Reg/Opcode field.
503 // - In AVX, there is a register operand in the VEX.vvvv field here -
504 // Operand 3 (optional) is an immediate.
505 assert(numPhysicalOperands >= 2 + additionalOperands &&
506 numPhysicalOperands <= 3 + additionalOperands &&
507 "Unexpected number of operands for MRMDestRegFrm");
508
509 HANDLE_OPERAND(rmRegister)
510 if (HasEVEX_K)
511 HANDLE_OPERAND(writemaskRegister)
512
513 if (HasVEX_4V)
514 // FIXME: In AVX, the register below becomes the one encoded
515 // in ModRMVEX and the one above the one in the VEX.VVVV field
516 HANDLE_OPERAND(vvvvRegister)
517
518 HANDLE_OPERAND(roRegister)
519 HANDLE_OPTIONAL(immediate)
520 break;
521 case X86Local::MRMDestMem:
522 // Operand 1 is a memory operand (possibly SIB-extended)
523 // Operand 2 is a register operand in the Reg/Opcode field.
524 // - In AVX, there is a register operand in the VEX.vvvv field here -
525 // Operand 3 (optional) is an immediate.
526 assert(numPhysicalOperands >= 2 + additionalOperands &&
527 numPhysicalOperands <= 3 + additionalOperands &&
528 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
529
530 HANDLE_OPERAND(memory)
531
532 if (HasEVEX_K)
533 HANDLE_OPERAND(writemaskRegister)
534
535 if (HasVEX_4V)
536 // FIXME: In AVX, the register below becomes the one encoded
537 // in ModRMVEX and the one above the one in the VEX.VVVV field
538 HANDLE_OPERAND(vvvvRegister)
539
540 HANDLE_OPERAND(roRegister)
541 HANDLE_OPTIONAL(immediate)
542 break;
543 case X86Local::MRMSrcReg:
544 // Operand 1 is a register operand in the Reg/Opcode field.
545 // Operand 2 is a register operand in the R/M field.
546 // - In AVX, there is a register operand in the VEX.vvvv field here -
547 // Operand 3 (optional) is an immediate.
548 // Operand 4 (optional) is an immediate.
549
550 assert(numPhysicalOperands >= 2 + additionalOperands &&
551 numPhysicalOperands <= 4 + additionalOperands &&
552 "Unexpected number of operands for MRMSrcRegFrm");
553
554 HANDLE_OPERAND(roRegister)
555
556 if (HasEVEX_K)
557 HANDLE_OPERAND(writemaskRegister)
558
559 if (HasVEX_4V)
560 // FIXME: In AVX, the register below becomes the one encoded
561 // in ModRMVEX and the one above the one in the VEX.VVVV field
562 HANDLE_OPERAND(vvvvRegister)
563
564 HANDLE_OPERAND(rmRegister)
565 HANDLE_OPTIONAL(immediate)
566 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
567 break;
568 case X86Local::MRMSrcReg4VOp3:
569 assert(numPhysicalOperands == 3 &&
570 "Unexpected number of operands for MRMSrcReg4VOp3Frm");
571 HANDLE_OPERAND(roRegister)
572 HANDLE_OPERAND(rmRegister)
573 HANDLE_OPERAND(vvvvRegister)
574 break;
575 case X86Local::MRMSrcRegOp4:
576 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
577 "Unexpected number of operands for MRMSrcRegOp4Frm");
578 HANDLE_OPERAND(roRegister)
579 HANDLE_OPERAND(vvvvRegister)
580 HANDLE_OPERAND(immediate) // Register in imm[7:4]
581 HANDLE_OPERAND(rmRegister)
582 HANDLE_OPTIONAL(immediate)
583 break;
584 case X86Local::MRMSrcMem:
585 // Operand 1 is a register operand in the Reg/Opcode field.
586 // Operand 2 is a memory operand (possibly SIB-extended)
587 // - In AVX, there is a register operand in the VEX.vvvv field here -
588 // Operand 3 (optional) is an immediate.
589
590 assert(numPhysicalOperands >= 2 + additionalOperands &&
591 numPhysicalOperands <= 4 + additionalOperands &&
592 "Unexpected number of operands for MRMSrcMemFrm");
593
594 HANDLE_OPERAND(roRegister)
595
596 if (HasEVEX_K)
597 HANDLE_OPERAND(writemaskRegister)
598
599 if (HasVEX_4V)
600 // FIXME: In AVX, the register below becomes the one encoded
601 // in ModRMVEX and the one above the one in the VEX.VVVV field
602 HANDLE_OPERAND(vvvvRegister)
603
604 HANDLE_OPERAND(memory)
605 HANDLE_OPTIONAL(immediate)
606 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
607 break;
608 case X86Local::MRMSrcMem4VOp3:
609 assert(numPhysicalOperands == 3 &&
610 "Unexpected number of operands for MRMSrcMem4VOp3Frm");
611 HANDLE_OPERAND(roRegister)
612 HANDLE_OPERAND(memory)
613 HANDLE_OPERAND(vvvvRegister)
614 break;
615 case X86Local::MRMSrcMemOp4:
616 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
617 "Unexpected number of operands for MRMSrcMemOp4Frm");
618 HANDLE_OPERAND(roRegister)
619 HANDLE_OPERAND(vvvvRegister)
620 HANDLE_OPERAND(immediate) // Register in imm[7:4]
621 HANDLE_OPERAND(memory)
622 HANDLE_OPTIONAL(immediate)
623 break;
624 case X86Local::MRMXr:
625 case X86Local::MRM0r:
626 case X86Local::MRM1r:
627 case X86Local::MRM2r:
628 case X86Local::MRM3r:
629 case X86Local::MRM4r:
630 case X86Local::MRM5r:
631 case X86Local::MRM6r:
632 case X86Local::MRM7r:
633 // Operand 1 is a register operand in the R/M field.
634 // Operand 2 (optional) is an immediate or relocation.
635 // Operand 3 (optional) is an immediate.
636 assert(numPhysicalOperands >= 0 + additionalOperands &&
637 numPhysicalOperands <= 3 + additionalOperands &&
638 "Unexpected number of operands for MRMnr");
639
640 if (HasVEX_4V)
641 HANDLE_OPERAND(vvvvRegister)
642
643 if (HasEVEX_K)
644 HANDLE_OPERAND(writemaskRegister)
645 HANDLE_OPTIONAL(rmRegister)
646 HANDLE_OPTIONAL(relocation)
647 HANDLE_OPTIONAL(immediate)
648 break;
649 case X86Local::MRMXm:
650 case X86Local::MRM0m:
651 case X86Local::MRM1m:
652 case X86Local::MRM2m:
653 case X86Local::MRM3m:
654 case X86Local::MRM4m:
655 case X86Local::MRM5m:
656 case X86Local::MRM6m:
657 case X86Local::MRM7m:
658 // Operand 1 is a memory operand (possibly SIB-extended)
659 // Operand 2 (optional) is an immediate or relocation.
660 assert(numPhysicalOperands >= 1 + additionalOperands &&
661 numPhysicalOperands <= 2 + additionalOperands &&
662 "Unexpected number of operands for MRMnm");
663
664 if (HasVEX_4V)
665 HANDLE_OPERAND(vvvvRegister)
666 if (HasEVEX_K)
667 HANDLE_OPERAND(writemaskRegister)
668 HANDLE_OPERAND(memory)
669 HANDLE_OPTIONAL(relocation)
670 break;
671 case X86Local::RawFrmImm8:
672 // operand 1 is a 16-bit immediate
673 // operand 2 is an 8-bit immediate
674 assert(numPhysicalOperands == 2 &&
675 "Unexpected number of operands for X86Local::RawFrmImm8");
676 HANDLE_OPERAND(immediate)
677 HANDLE_OPERAND(immediate)
678 break;
679 case X86Local::RawFrmImm16:
680 // operand 1 is a 16-bit immediate
681 // operand 2 is a 16-bit immediate
682 HANDLE_OPERAND(immediate)
683 HANDLE_OPERAND(immediate)
684 break;
685 #define MAP(from, to) case X86Local::MRM_##from:
686 X86_INSTR_MRM_MAPPING
687 #undef MAP
688 HANDLE_OPTIONAL(relocation)
689 break;
690 }
691
692 #undef HANDLE_OPERAND
693 #undef HANDLE_OPTIONAL
694 }
695
696 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
697 // Special cases where the LLVM tables are not complete
698
699 #define MAP(from, to) \
700 case X86Local::MRM_##from:
701
702 llvm::Optional<OpcodeType> opcodeType;
703 switch (OpMap) {
704 default: llvm_unreachable("Invalid map!");
705 case X86Local::OB: opcodeType = ONEBYTE; break;
706 case X86Local::TB: opcodeType = TWOBYTE; break;
707 case X86Local::T8: opcodeType = THREEBYTE_38; break;
708 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
709 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
710 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
711 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
712 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
713 }
714
715 std::unique_ptr<ModRMFilter> filter;
716 switch (Form) {
717 default: llvm_unreachable("Invalid form!");
718 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
719 case X86Local::RawFrm:
720 case X86Local::AddRegFrm:
721 case X86Local::RawFrmMemOffs:
722 case X86Local::RawFrmSrc:
723 case X86Local::RawFrmDst:
724 case X86Local::RawFrmDstSrc:
725 case X86Local::RawFrmImm8:
726 case X86Local::RawFrmImm16:
727 filter = llvm::make_unique<DumbFilter>();
728 break;
729 case X86Local::MRMDestReg:
730 case X86Local::MRMSrcReg:
731 case X86Local::MRMSrcReg4VOp3:
732 case X86Local::MRMSrcRegOp4:
733 case X86Local::MRMXr:
734 filter = llvm::make_unique<ModFilter>(true);
735 break;
736 case X86Local::MRMDestMem:
737 case X86Local::MRMSrcMem:
738 case X86Local::MRMSrcMem4VOp3:
739 case X86Local::MRMSrcMemOp4:
740 case X86Local::MRMXm:
741 filter = llvm::make_unique<ModFilter>(false);
742 break;
743 case X86Local::MRM0r: case X86Local::MRM1r:
744 case X86Local::MRM2r: case X86Local::MRM3r:
745 case X86Local::MRM4r: case X86Local::MRM5r:
746 case X86Local::MRM6r: case X86Local::MRM7r:
747 filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
748 break;
749 case X86Local::MRM0m: case X86Local::MRM1m:
750 case X86Local::MRM2m: case X86Local::MRM3m:
751 case X86Local::MRM4m: case X86Local::MRM5m:
752 case X86Local::MRM6m: case X86Local::MRM7m:
753 filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
754 break;
755 X86_INSTR_MRM_MAPPING
756 filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
757 break;
758 } // switch (Form)
759
760 uint8_t opcodeToSet = Opcode;
761
762 unsigned AddressSize = 0;
763 switch (AdSize) {
764 case X86Local::AdSize16: AddressSize = 16; break;
765 case X86Local::AdSize32: AddressSize = 32; break;
766 case X86Local::AdSize64: AddressSize = 64; break;
767 }
768
769 assert(opcodeType && "Opcode type not set");
770 assert(filter && "Filter not set");
771
772 if (Form == X86Local::AddRegFrm) {
773 assert(((opcodeToSet & 7) == 0) &&
774 "ADDREG_FRM opcode not aligned");
775
776 uint8_t currentOpcode;
777
778 for (currentOpcode = opcodeToSet;
779 currentOpcode < opcodeToSet + 8;
780 ++currentOpcode)
781 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
782 UID, Is32Bit, OpPrefix == 0,
783 IgnoresVEX_L || EncodeRC,
784 VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
785 } else {
786 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
787 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
788 VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
789 }
790
791 #undef MAP
792 }
793
794 #define TYPE(str, type) if (s == str) return type;
795 OperandType RecognizableInstr::typeFromString(const std::string &s,
796 bool hasREX_WPrefix,
797 uint8_t OpSize) {
798 if(hasREX_WPrefix) {
799 // For instructions with a REX_W prefix, a declared 32-bit register encoding
800 // is special.
801 TYPE("GR32", TYPE_R32)
802 }
803 if(OpSize == X86Local::OpSize16) {
804 // For OpSize16 instructions, a declared 16-bit register or
805 // immediate encoding is special.
806 TYPE("GR16", TYPE_Rv)
807 } else if(OpSize == X86Local::OpSize32) {
808 // For OpSize32 instructions, a declared 32-bit register or
809 // immediate encoding is special.
810 TYPE("GR32", TYPE_Rv)
811 }
812 TYPE("i16mem", TYPE_M)
813 TYPE("i16imm", TYPE_IMM)
814 TYPE("i16i8imm", TYPE_IMM)
815 TYPE("GR16", TYPE_R16)
816 TYPE("i32mem", TYPE_M)
817 TYPE("i32imm", TYPE_IMM)
818 TYPE("i32i8imm", TYPE_IMM)
819 TYPE("GR32", TYPE_R32)
820 TYPE("GR32orGR64", TYPE_R32)
821 TYPE("i64mem", TYPE_M)
822 TYPE("i64i32imm", TYPE_IMM)
823 TYPE("i64i8imm", TYPE_IMM)
824 TYPE("GR64", TYPE_R64)
825 TYPE("i8mem", TYPE_M)
826 TYPE("i8imm", TYPE_IMM)
827 TYPE("u8imm", TYPE_UIMM8)
828 TYPE("i32u8imm", TYPE_UIMM8)
829 TYPE("GR8", TYPE_R8)
830 TYPE("VR128", TYPE_XMM)
831 TYPE("VR128X", TYPE_XMM)
832 TYPE("f128mem", TYPE_M)
833 TYPE("f256mem", TYPE_M)
834 TYPE("f512mem", TYPE_M)
835 TYPE("FR128", TYPE_XMM)
836 TYPE("FR64", TYPE_XMM)
837 TYPE("FR64X", TYPE_XMM)
838 TYPE("f64mem", TYPE_M)
839 TYPE("sdmem", TYPE_M)
840 TYPE("FR32", TYPE_XMM)
841 TYPE("FR32X", TYPE_XMM)
842 TYPE("f32mem", TYPE_M)
843 TYPE("ssmem", TYPE_M)
844 TYPE("RST", TYPE_ST)
845 TYPE("i128mem", TYPE_M)
846 TYPE("i256mem", TYPE_M)
847 TYPE("i512mem", TYPE_M)
848 TYPE("i64i32imm_pcrel", TYPE_REL)
849 TYPE("i16imm_pcrel", TYPE_REL)
850 TYPE("i32imm_pcrel", TYPE_REL)
851 TYPE("SSECC", TYPE_IMM3)
852 TYPE("XOPCC", TYPE_IMM3)
853 TYPE("AVXCC", TYPE_IMM5)
854 TYPE("AVX512ICC", TYPE_AVX512ICC)
855 TYPE("AVX512RC", TYPE_IMM)
856 TYPE("brtarget32", TYPE_REL)
857 TYPE("brtarget16", TYPE_REL)
858 TYPE("brtarget8", TYPE_REL)
859 TYPE("f80mem", TYPE_M)
860 TYPE("lea64_32mem", TYPE_M)
861 TYPE("lea64mem", TYPE_M)
862 TYPE("VR64", TYPE_MM64)
863 TYPE("i64imm", TYPE_IMM)
864 TYPE("anymem", TYPE_M)
865 TYPE("opaquemem", TYPE_M)
866 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
867 TYPE("DEBUG_REG", TYPE_DEBUGREG)
868 TYPE("CONTROL_REG", TYPE_CONTROLREG)
869 TYPE("srcidx8", TYPE_SRCIDX)
870 TYPE("srcidx16", TYPE_SRCIDX)
871 TYPE("srcidx32", TYPE_SRCIDX)
872 TYPE("srcidx64", TYPE_SRCIDX)
873 TYPE("dstidx8", TYPE_DSTIDX)
874 TYPE("dstidx16", TYPE_DSTIDX)
875 TYPE("dstidx32", TYPE_DSTIDX)
876 TYPE("dstidx64", TYPE_DSTIDX)
877 TYPE("offset16_8", TYPE_MOFFS)
878 TYPE("offset16_16", TYPE_MOFFS)
879 TYPE("offset16_32", TYPE_MOFFS)
880 TYPE("offset32_8", TYPE_MOFFS)
881 TYPE("offset32_16", TYPE_MOFFS)
882 TYPE("offset32_32", TYPE_MOFFS)
883 TYPE("offset32_64", TYPE_MOFFS)
884 TYPE("offset64_8", TYPE_MOFFS)
885 TYPE("offset64_16", TYPE_MOFFS)
886 TYPE("offset64_32", TYPE_MOFFS)
887 TYPE("offset64_64", TYPE_MOFFS)
888 TYPE("VR256", TYPE_YMM)
889 TYPE("VR256X", TYPE_YMM)
890 TYPE("VR512", TYPE_ZMM)
891 TYPE("VK1", TYPE_VK)
892 TYPE("VK1WM", TYPE_VK)
893 TYPE("VK2", TYPE_VK)
894 TYPE("VK2WM", TYPE_VK)
895 TYPE("VK4", TYPE_VK)
896 TYPE("VK4WM", TYPE_VK)
897 TYPE("VK8", TYPE_VK)
898 TYPE("VK8WM", TYPE_VK)
899 TYPE("VK16", TYPE_VK)
900 TYPE("VK16WM", TYPE_VK)
901 TYPE("VK32", TYPE_VK)
902 TYPE("VK32WM", TYPE_VK)
903 TYPE("VK64", TYPE_VK)
904 TYPE("VK64WM", TYPE_VK)
905 TYPE("vx64mem", TYPE_MVSIBX)
906 TYPE("vx128mem", TYPE_MVSIBX)
907 TYPE("vx256mem", TYPE_MVSIBX)
908 TYPE("vy128mem", TYPE_MVSIBY)
909 TYPE("vy256mem", TYPE_MVSIBY)
910 TYPE("vx64xmem", TYPE_MVSIBX)
911 TYPE("vx128xmem", TYPE_MVSIBX)
912 TYPE("vx256xmem", TYPE_MVSIBX)
913 TYPE("vy128xmem", TYPE_MVSIBY)
914 TYPE("vy256xmem", TYPE_MVSIBY)
915 TYPE("vy512xmem", TYPE_MVSIBY)
916 TYPE("vz256mem", TYPE_MVSIBZ)
917 TYPE("vz512mem", TYPE_MVSIBZ)
918 TYPE("BNDR", TYPE_BNDR)
919 errs() << "Unhandled type string " << s << "\n";
920 llvm_unreachable("Unhandled type string");
921 }
922 #undef TYPE
923
924 #define ENCODING(str, encoding) if (s == str) return encoding;
925 OperandEncoding
926 RecognizableInstr::immediateEncodingFromString(const std::string &s,
927 uint8_t OpSize) {
928 if(OpSize != X86Local::OpSize16) {
929 // For instructions without an OpSize prefix, a declared 16-bit register or
930 // immediate encoding is special.
931 ENCODING("i16imm", ENCODING_IW)
932 }
933 ENCODING("i32i8imm", ENCODING_IB)
934 ENCODING("SSECC", ENCODING_IB)
935 ENCODING("XOPCC", ENCODING_IB)
936 ENCODING("AVXCC", ENCODING_IB)
937 ENCODING("AVX512ICC", ENCODING_IB)
938 ENCODING("AVX512RC", ENCODING_IRC)
939 ENCODING("i16imm", ENCODING_Iv)
940 ENCODING("i16i8imm", ENCODING_IB)
941 ENCODING("i32imm", ENCODING_Iv)
942 ENCODING("i64i32imm", ENCODING_ID)
943 ENCODING("i64i8imm", ENCODING_IB)
944 ENCODING("i8imm", ENCODING_IB)
945 ENCODING("u8imm", ENCODING_IB)
946 ENCODING("i32u8imm", ENCODING_IB)
947 // This is not a typo. Instructions like BLENDVPD put
948 // register IDs in 8-bit immediates nowadays.
949 ENCODING("FR32", ENCODING_IB)
950 ENCODING("FR64", ENCODING_IB)
951 ENCODING("FR128", ENCODING_IB)
952 ENCODING("VR128", ENCODING_IB)
953 ENCODING("VR256", ENCODING_IB)
954 ENCODING("FR32X", ENCODING_IB)
955 ENCODING("FR64X", ENCODING_IB)
956 ENCODING("VR128X", ENCODING_IB)
957 ENCODING("VR256X", ENCODING_IB)
958 ENCODING("VR512", ENCODING_IB)
959 errs() << "Unhandled immediate encoding " << s << "\n";
960 llvm_unreachable("Unhandled immediate encoding");
961 }
962
963 OperandEncoding
964 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
965 uint8_t OpSize) {
966 ENCODING("RST", ENCODING_FP)
967 ENCODING("GR16", ENCODING_RM)
968 ENCODING("GR32", ENCODING_RM)
969 ENCODING("GR32orGR64", ENCODING_RM)
970 ENCODING("GR64", ENCODING_RM)
971 ENCODING("GR8", ENCODING_RM)
972 ENCODING("VR128", ENCODING_RM)
973 ENCODING("VR128X", ENCODING_RM)
974 ENCODING("FR128", ENCODING_RM)
975 ENCODING("FR64", ENCODING_RM)
976 ENCODING("FR32", ENCODING_RM)
977 ENCODING("FR64X", ENCODING_RM)
978 ENCODING("FR32X", ENCODING_RM)
979 ENCODING("VR64", ENCODING_RM)
980 ENCODING("VR256", ENCODING_RM)
981 ENCODING("VR256X", ENCODING_RM)
982 ENCODING("VR512", ENCODING_RM)
983 ENCODING("VK1", ENCODING_RM)
984 ENCODING("VK2", ENCODING_RM)
985 ENCODING("VK4", ENCODING_RM)
986 ENCODING("VK8", ENCODING_RM)
987 ENCODING("VK16", ENCODING_RM)
988 ENCODING("VK32", ENCODING_RM)
989 ENCODING("VK64", ENCODING_RM)
990 ENCODING("BNDR", ENCODING_RM)
991 errs() << "Unhandled R/M register encoding " << s << "\n";
992 llvm_unreachable("Unhandled R/M register encoding");
993 }
994
995 OperandEncoding
996 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
997 uint8_t OpSize) {
998 ENCODING("GR16", ENCODING_REG)
999 ENCODING("GR32", ENCODING_REG)
1000 ENCODING("GR32orGR64", ENCODING_REG)
1001 ENCODING("GR64", ENCODING_REG)
1002 ENCODING("GR8", ENCODING_REG)
1003 ENCODING("VR128", ENCODING_REG)
1004 ENCODING("FR128", ENCODING_REG)
1005 ENCODING("FR64", ENCODING_REG)
1006 ENCODING("FR32", ENCODING_REG)
1007 ENCODING("VR64", ENCODING_REG)
1008 ENCODING("SEGMENT_REG", ENCODING_REG)
1009 ENCODING("DEBUG_REG", ENCODING_REG)
1010 ENCODING("CONTROL_REG", ENCODING_REG)
1011 ENCODING("VR256", ENCODING_REG)
1012 ENCODING("VR256X", ENCODING_REG)
1013 ENCODING("VR128X", ENCODING_REG)
1014 ENCODING("FR64X", ENCODING_REG)
1015 ENCODING("FR32X", ENCODING_REG)
1016 ENCODING("VR512", ENCODING_REG)
1017 ENCODING("VK1", ENCODING_REG)
1018 ENCODING("VK2", ENCODING_REG)
1019 ENCODING("VK4", ENCODING_REG)
1020 ENCODING("VK8", ENCODING_REG)
1021 ENCODING("VK16", ENCODING_REG)
1022 ENCODING("VK32", ENCODING_REG)
1023 ENCODING("VK64", ENCODING_REG)
1024 ENCODING("VK1WM", ENCODING_REG)
1025 ENCODING("VK2WM", ENCODING_REG)
1026 ENCODING("VK4WM", ENCODING_REG)
1027 ENCODING("VK8WM", ENCODING_REG)
1028 ENCODING("VK16WM", ENCODING_REG)
1029 ENCODING("VK32WM", ENCODING_REG)
1030 ENCODING("VK64WM", ENCODING_REG)
1031 ENCODING("BNDR", ENCODING_REG)
1032 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1033 llvm_unreachable("Unhandled reg/opcode register encoding");
1034 }
1035
1036 OperandEncoding
1037 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1038 uint8_t OpSize) {
1039 ENCODING("GR32", ENCODING_VVVV)
1040 ENCODING("GR64", ENCODING_VVVV)
1041 ENCODING("FR32", ENCODING_VVVV)
1042 ENCODING("FR128", ENCODING_VVVV)
1043 ENCODING("FR64", ENCODING_VVVV)
1044 ENCODING("VR128", ENCODING_VVVV)
1045 ENCODING("VR256", ENCODING_VVVV)
1046 ENCODING("FR32X", ENCODING_VVVV)
1047 ENCODING("FR64X", ENCODING_VVVV)
1048 ENCODING("VR128X", ENCODING_VVVV)
1049 ENCODING("VR256X", ENCODING_VVVV)
1050 ENCODING("VR512", ENCODING_VVVV)
1051 ENCODING("VK1", ENCODING_VVVV)
1052 ENCODING("VK2", ENCODING_VVVV)
1053 ENCODING("VK4", ENCODING_VVVV)
1054 ENCODING("VK8", ENCODING_VVVV)
1055 ENCODING("VK16", ENCODING_VVVV)
1056 ENCODING("VK32", ENCODING_VVVV)
1057 ENCODING("VK64", ENCODING_VVVV)
1058 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1059 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1060 }
1061
1062 OperandEncoding
1063 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1064 uint8_t OpSize) {
1065 ENCODING("VK1WM", ENCODING_WRITEMASK)
1066 ENCODING("VK2WM", ENCODING_WRITEMASK)
1067 ENCODING("VK4WM", ENCODING_WRITEMASK)
1068 ENCODING("VK8WM", ENCODING_WRITEMASK)
1069 ENCODING("VK16WM", ENCODING_WRITEMASK)
1070 ENCODING("VK32WM", ENCODING_WRITEMASK)
1071 ENCODING("VK64WM", ENCODING_WRITEMASK)
1072 errs() << "Unhandled mask register encoding " << s << "\n";
1073 llvm_unreachable("Unhandled mask register encoding");
1074 }
1075
1076 OperandEncoding
1077 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1078 uint8_t OpSize) {
1079 ENCODING("i16mem", ENCODING_RM)
1080 ENCODING("i32mem", ENCODING_RM)
1081 ENCODING("i64mem", ENCODING_RM)
1082 ENCODING("i8mem", ENCODING_RM)
1083 ENCODING("ssmem", ENCODING_RM)
1084 ENCODING("sdmem", ENCODING_RM)
1085 ENCODING("f128mem", ENCODING_RM)
1086 ENCODING("f256mem", ENCODING_RM)
1087 ENCODING("f512mem", ENCODING_RM)
1088 ENCODING("f64mem", ENCODING_RM)
1089 ENCODING("f32mem", ENCODING_RM)
1090 ENCODING("i128mem", ENCODING_RM)
1091 ENCODING("i256mem", ENCODING_RM)
1092 ENCODING("i512mem", ENCODING_RM)
1093 ENCODING("f80mem", ENCODING_RM)
1094 ENCODING("lea64_32mem", ENCODING_RM)
1095 ENCODING("lea64mem", ENCODING_RM)
1096 ENCODING("anymem", ENCODING_RM)
1097 ENCODING("opaquemem", ENCODING_RM)
1098 ENCODING("vx64mem", ENCODING_VSIB)
1099 ENCODING("vx128mem", ENCODING_VSIB)
1100 ENCODING("vx256mem", ENCODING_VSIB)
1101 ENCODING("vy128mem", ENCODING_VSIB)
1102 ENCODING("vy256mem", ENCODING_VSIB)
1103 ENCODING("vx64xmem", ENCODING_VSIB)
1104 ENCODING("vx128xmem", ENCODING_VSIB)
1105 ENCODING("vx256xmem", ENCODING_VSIB)
1106 ENCODING("vy128xmem", ENCODING_VSIB)
1107 ENCODING("vy256xmem", ENCODING_VSIB)
1108 ENCODING("vy512xmem", ENCODING_VSIB)
1109 ENCODING("vz256mem", ENCODING_VSIB)
1110 ENCODING("vz512mem", ENCODING_VSIB)
1111 errs() << "Unhandled memory encoding " << s << "\n";
1112 llvm_unreachable("Unhandled memory encoding");
1113 }
1114
1115 OperandEncoding
1116 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1117 uint8_t OpSize) {
1118 if(OpSize != X86Local::OpSize16) {
1119 // For instructions without an OpSize prefix, a declared 16-bit register or
1120 // immediate encoding is special.
1121 ENCODING("i16imm", ENCODING_IW)
1122 }
1123 ENCODING("i16imm", ENCODING_Iv)
1124 ENCODING("i16i8imm", ENCODING_IB)
1125 ENCODING("i32imm", ENCODING_Iv)
1126 ENCODING("i32i8imm", ENCODING_IB)
1127 ENCODING("i64i32imm", ENCODING_ID)
1128 ENCODING("i64i8imm", ENCODING_IB)
1129 ENCODING("i8imm", ENCODING_IB)
1130 ENCODING("u8imm", ENCODING_IB)
1131 ENCODING("i32u8imm", ENCODING_IB)
1132 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1133 ENCODING("i16imm_pcrel", ENCODING_IW)
1134 ENCODING("i32imm_pcrel", ENCODING_ID)
1135 ENCODING("brtarget32", ENCODING_ID)
1136 ENCODING("brtarget16", ENCODING_IW)
1137 ENCODING("brtarget8", ENCODING_IB)
1138 ENCODING("i64imm", ENCODING_IO)
1139 ENCODING("offset16_8", ENCODING_Ia)
1140 ENCODING("offset16_16", ENCODING_Ia)
1141 ENCODING("offset16_32", ENCODING_Ia)
1142 ENCODING("offset32_8", ENCODING_Ia)
1143 ENCODING("offset32_16", ENCODING_Ia)
1144 ENCODING("offset32_32", ENCODING_Ia)
1145 ENCODING("offset32_64", ENCODING_Ia)
1146 ENCODING("offset64_8", ENCODING_Ia)
1147 ENCODING("offset64_16", ENCODING_Ia)
1148 ENCODING("offset64_32", ENCODING_Ia)
1149 ENCODING("offset64_64", ENCODING_Ia)
1150 ENCODING("srcidx8", ENCODING_SI)
1151 ENCODING("srcidx16", ENCODING_SI)
1152 ENCODING("srcidx32", ENCODING_SI)
1153 ENCODING("srcidx64", ENCODING_SI)
1154 ENCODING("dstidx8", ENCODING_DI)
1155 ENCODING("dstidx16", ENCODING_DI)
1156 ENCODING("dstidx32", ENCODING_DI)
1157 ENCODING("dstidx64", ENCODING_DI)
1158 errs() << "Unhandled relocation encoding " << s << "\n";
1159 llvm_unreachable("Unhandled relocation encoding");
1160 }
1161
1162 OperandEncoding
1163 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1164 uint8_t OpSize) {
1165 ENCODING("GR32", ENCODING_Rv)
1166 ENCODING("GR64", ENCODING_RO)
1167 ENCODING("GR16", ENCODING_Rv)
1168 ENCODING("GR8", ENCODING_RB)
1169 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1170 llvm_unreachable("Unhandled opcode modifier encoding");
1171 }
1172 #undef ENCODING
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.