1 //==- SystemZInstrDFP.td - Floating-point SystemZ instructions -*- tblgen-*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // The instructions in this file implement SystemZ decimal floating-point
10 // arithmetic. These instructions are inot currently used for code generation,
11 // are provided for use with the assembler and disassembler only. If LLVM
12 // ever supports decimal floating-point types (_Decimal64 etc.), they can
13 // also be used for code generation for those types.
15 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
22 let Uses = [FPC], Defs = [CC] in {
23 def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
24 def LTXTR : UnaryRRE<"ltxtr", 0xB3DE, null_frag, FP128, FP128>;
28 //===----------------------------------------------------------------------===//
29 // Conversion instructions
30 //===----------------------------------------------------------------------===//
32 // Convert floating-point values to narrower representations. The destination
33 // of LDXTR is a 128-bit value, but only the first register of the pair is used.
35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
36 def LDXTR : TernaryRRFe<"ldxtr", 0xB3DD, FP128, FP128>;
39 // Extend floating-point values to wider representations.
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
42 def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
45 // Convert a signed integer value to a floating-point one.
47 def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
48 def CXGTR : UnaryRRE<"cxgtr", 0xB3F9, null_frag, FP128, GR64>;
49 let Predicates = [FeatureFPExtension] in {
50 def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
51 def CXGTRA : TernaryRRFe<"cxgtra", 0xB3F9, FP128, GR64>;
52 def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
53 def CXFTR : TernaryRRFe<"cxftr", 0xB959, FP128, GR32>;
57 // Convert an unsigned integer value to a floating-point one.
58 let Uses = [FPC], Predicates = [FeatureFPExtension] in {
59 def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
60 def CXLGTR : TernaryRRFe<"cxlgtr", 0xB95A, FP128, GR64>;
61 def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
62 def CXLFTR : TernaryRRFe<"cxlftr", 0xB95B, FP128, GR32>;
65 // Convert a floating-point value to a signed integer value.
66 let Uses = [FPC], Defs = [CC] in {
67 def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
68 def CGXTR : BinaryRRFe<"cgxtr", 0xB3E9, GR64, FP128>;
69 let Predicates = [FeatureFPExtension] in {
70 def CGDTRA : TernaryRRFe<"cgdtra", 0xB3E1, GR64, FP64>;
71 def CGXTRA : TernaryRRFe<"cgxtra", 0xB3E9, GR64, FP128>;
72 def CFDTR : TernaryRRFe<"cfdtr", 0xB941, GR32, FP64>;
73 def CFXTR : TernaryRRFe<"cfxtr", 0xB949, GR32, FP128>;
77 // Convert a floating-point value to an unsigned integer value.
78 let Uses = [FPC], Defs = [CC] in {
79 let Predicates = [FeatureFPExtension] in {
80 def CLGDTR : TernaryRRFe<"clgdtr", 0xB942, GR64, FP64>;
81 def CLGXTR : TernaryRRFe<"clgxtr", 0xB94A, GR64, FP128>;
82 def CLFDTR : TernaryRRFe<"clfdtr", 0xB943, GR32, FP64>;
83 def CLFXTR : TernaryRRFe<"clfxtr", 0xB94B, GR32, FP128>;
87 // Convert a packed value to a floating-point one.
88 def CDSTR : UnaryRRE<"cdstr", 0xB3F3, null_frag, FP64, GR64>;
89 def CXSTR : UnaryRRE<"cxstr", 0xB3FB, null_frag, FP128, GR128>;
90 def CDUTR : UnaryRRE<"cdutr", 0xB3F2, null_frag, FP64, GR64>;
91 def CXUTR : UnaryRRE<"cxutr", 0xB3FA, null_frag, FP128, GR128>;
93 // Convert a floating-point value to a packed value.
94 def CSDTR : BinaryRRFd<"csdtr", 0xB3E3, GR64, FP64>;
95 def CSXTR : BinaryRRFd<"csxtr", 0xB3EB, GR128, FP128>;
96 def CUDTR : UnaryRRE<"cudtr", 0xB3E2, null_frag, GR64, FP64>;
97 def CUXTR : UnaryRRE<"cuxtr", 0xB3EA, null_frag, GR128, FP128>;
99 // Convert from/to memory values in the zoned format.
100 let Predicates = [FeatureDFPZonedConversion] in {
101 def CDZT : BinaryRSL<"cdzt", 0xEDAA, FP64>;
102 def CXZT : BinaryRSL<"cxzt", 0xEDAB, FP128>;
103 def CZDT : StoreBinaryRSL<"czdt", 0xEDA8, FP64>;
104 def CZXT : StoreBinaryRSL<"czxt", 0xEDA9, FP128>;
107 // Convert from/to memory values in the packed format.
108 let Predicates = [FeatureDFPPackedConversion] in {
109 def CDPT : BinaryRSL<"cdpt", 0xEDAE, FP64>;
110 def CXPT : BinaryRSL<"cxpt", 0xEDAF, FP128>;
111 def CPDT : StoreBinaryRSL<"cpdt", 0xEDAC, FP64>;
112 def CPXT : StoreBinaryRSL<"cpxt", 0xEDAD, FP128>;
115 // Perform floating-point operation.
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
117 def PFPO : SideEffectInherentE<"pfpo", 0x010A>;
120 //===----------------------------------------------------------------------===//
122 //===----------------------------------------------------------------------===//
124 // Round to an integer, with the second operand (M3) specifying the rounding
125 // mode. M4 can be set to 4 to suppress detection of inexact conditions.
126 let Uses = [FPC] in {
127 def FIDTR : TernaryRRFe<"fidtr", 0xB3D7, FP64, FP64>;
128 def FIXTR : TernaryRRFe<"fixtr", 0xB3DF, FP128, FP128>;
131 // Extract biased exponent.
132 def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, FP64, FP64>;
133 def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, FP128, FP128>;
135 // Extract significance.
136 def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, FP64, FP64>;
137 def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, FP128, FP128>;
140 //===----------------------------------------------------------------------===//
142 //===----------------------------------------------------------------------===//
145 let Uses = [FPC], Defs = [CC] in {
146 let isCommutable = 1 in {
147 def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;
148 def AXTR : BinaryRRFa<"axtr", 0xB3DA, null_frag, FP128, FP128, FP128>;
150 let Predicates = [FeatureFPExtension] in {
151 def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;
152 def AXTRA : TernaryRRFa<"axtra", 0xB3DA, FP128, FP128, FP128>;
157 let Uses = [FPC], Defs = [CC] in {
158 def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;
159 def SXTR : BinaryRRFa<"sxtr", 0xB3DB, null_frag, FP128, FP128, FP128>;
160 let Predicates = [FeatureFPExtension] in {
161 def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;
162 def SXTRA : TernaryRRFa<"sxtra", 0xB3DB, FP128, FP128, FP128>;
167 let Uses = [FPC] in {
168 let isCommutable = 1 in {
169 def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;
170 def MXTR : BinaryRRFa<"mxtr", 0xB3D8, null_frag, FP128, FP128, FP128>;
172 let Predicates = [FeatureFPExtension] in {
173 def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;
174 def MXTRA : TernaryRRFa<"mxtra", 0xB3D8, FP128, FP128, FP128>;
179 let Uses = [FPC] in {
180 def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;
181 def DXTR : BinaryRRFa<"dxtr", 0xB3D9, null_frag, FP128, FP128, FP128>;
182 let Predicates = [FeatureFPExtension] in {
183 def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;
184 def DXTRA : TernaryRRFa<"dxtra", 0xB3D9, FP128, FP128, FP128>;
189 let Uses = [FPC] in {
190 def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;
191 def QAXTR : TernaryRRFb<"qaxtr", 0xB3FD, FP128, FP128, FP128>;
195 let Uses = [FPC] in {
196 def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
197 def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, FP128, FP128>;
200 // Shift significand left/right.
201 def SLDT : BinaryRXF<"sldt", 0xED40, null_frag, FP64, FP64, null_frag, 0>;
202 def SLXT : BinaryRXF<"slxt", 0xED48, null_frag, FP128, FP128, null_frag, 0>;
203 def SRDT : BinaryRXF<"srdt", 0xED41, null_frag, FP64, FP64, null_frag, 0>;
204 def SRXT : BinaryRXF<"srxt", 0xED49, null_frag, FP128, FP128, null_frag, 0>;
206 // Insert biased exponent.
207 def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, FP64, FP64>;
208 def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, FP128, FP128>;
211 //===----------------------------------------------------------------------===//
213 //===----------------------------------------------------------------------===//
216 let Uses = [FPC], Defs = [CC] in {
217 def CDTR : CompareRRE<"cdtr", 0xB3E4, null_frag, FP64, FP64>;
218 def CXTR : CompareRRE<"cxtr", 0xB3EC, null_frag, FP128, FP128>;
221 // Compare and signal.
222 let Uses = [FPC], Defs = [CC] in {
223 def KDTR : CompareRRE<"kdtr", 0xB3E0, null_frag, FP64, FP64>;
224 def KXTR : CompareRRE<"kxtr", 0xB3E8, null_frag, FP128, FP128>;
227 // Compare biased exponent.
229 def CEDTR : CompareRRE<"cedtr", 0xB3F4, null_frag, FP64, FP64>;
230 def CEXTR : CompareRRE<"cextr", 0xB3FC, null_frag, FP128, FP128>;
235 def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;
236 def TDCDT : TestRXE<"tdcdt", 0xED54, null_frag, FP64>;
237 def TDCXT : TestRXE<"tdcxt", 0xED58, null_frag, FP128>;
242 def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;
243 def TDGDT : TestRXE<"tdgdt", 0xED55, null_frag, FP64>;
244 def TDGXT : TestRXE<"tdgxt", 0xED59, null_frag, FP128>;