lib/Target/AArch64/AArch64AsmPrinter.cpp

   1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains a printer that converts from our internal representation
  11 // of machine-dependent LLVM code to the AArch64 assembly language.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "AArch64.h"
  16 #include "AArch64MCInstLower.h"
  17 #include "AArch64MachineFunctionInfo.h"
  18 #include "AArch64RegisterInfo.h"
  19 #include "AArch64Subtarget.h"
  20 #include "AArch64TargetObjectFile.h"
  21 #include "InstPrinter/AArch64InstPrinter.h"
  22 #include "MCTargetDesc/AArch64AddressingModes.h"
  23 #include "MCTargetDesc/AArch64MCTargetDesc.h"
  24 #include "Utils/AArch64BaseInfo.h"
  25 #include "llvm/ADT/SmallString.h"
  26 #include "llvm/ADT/SmallVector.h"
  27 #include "llvm/ADT/StringRef.h"
  28 #include "llvm/ADT/Triple.h"
  29 #include "llvm/ADT/Twine.h"
  30 #include "llvm/CodeGen/AsmPrinter.h"
  31 #include "llvm/CodeGen/MachineBasicBlock.h"
  32 #include "llvm/CodeGen/MachineFunction.h"
  33 #include "llvm/CodeGen/MachineInstr.h"
  34 #include "llvm/CodeGen/MachineOperand.h"
  35 #include "llvm/CodeGen/StackMaps.h"
  36 #include "llvm/CodeGen/TargetRegisterInfo.h"
  37 #include "llvm/IR/DataLayout.h"
  38 #include "llvm/IR/DebugInfoMetadata.h"
  39 #include "llvm/MC/MCAsmInfo.h"
  40 #include "llvm/MC/MCContext.h"
  41 #include "llvm/MC/MCInst.h"
  42 #include "llvm/MC/MCInstBuilder.h"
  43 #include "llvm/MC/MCStreamer.h"
  44 #include "llvm/MC/MCSymbol.h"
  45 #include "llvm/Support/Casting.h"
  46 #include "llvm/Support/ErrorHandling.h"
  47 #include "llvm/Support/TargetRegistry.h"
  48 #include "llvm/Support/raw_ostream.h"
  49 #include "llvm/Target/TargetMachine.h"
  50 #include <algorithm>
  51 #include <cassert>
  52 #include <cstdint>
  53 #include <map>
  54 #include <memory>
  55
  56 using namespace llvm;
  57
  58 #define DEBUG_TYPE "asm-printer"
  59
  60 namespace {
  61
  62 class AArch64AsmPrinter : public AsmPrinter {
  63   AArch64MCInstLower MCInstLowering;
  64   StackMaps SM;
  65   const AArch64Subtarget *STI;
  66
  67 public:
  68   AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
  69       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
  70         SM(*this) {}
  71
  72   StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
  73
  74   /// Wrapper for MCInstLowering.lowerOperand() for the
  75   /// tblgen'erated pseudo lowering.
  76   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
  77     return MCInstLowering.lowerOperand(MO, MCOp);
  78   }
  79
  80   void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
  81                      const MachineInstr &MI);
  82   void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
  83                        const MachineInstr &MI);
  84
  85   void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
  86   void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
  87   void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
  88
  89   void EmitSled(const MachineInstr &MI, SledKind Kind);
  90
  91   /// tblgen'erated driver function for lowering simple MI->MC
  92   /// pseudo instructions.
  93   bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
  94                                    const MachineInstr *MI);
  95
  96   void EmitInstruction(const MachineInstr *MI) override;
  97
  98   void getAnalysisUsage(AnalysisUsage &AU) const override {
  99     AsmPrinter::getAnalysisUsage(AU);
 100     AU.setPreservesAll();
 101   }
 102
 103   bool runOnMachineFunction(MachineFunction &F) override {
 104     AArch64FI = F.getInfo<AArch64FunctionInfo>();
 105     STI = static_cast<const AArch64Subtarget*>(&F.getSubtarget());
 106     bool Result = AsmPrinter::runOnMachineFunction(F);
 107     emitXRayTable();
 108     return Result;
 109   }
 110
 111 private:
 112   void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
 113   bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
 114   bool printAsmRegInClass(const MachineOperand &MO,
 115                           const TargetRegisterClass *RC, bool isVector,
 116                           raw_ostream &O);
 117
 118   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
 119                        unsigned AsmVariant, const char *ExtraCode,
 120                        raw_ostream &O) override;
 121   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
 122                              unsigned AsmVariant, const char *ExtraCode,
 123                              raw_ostream &O) override;
 124
 125   void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
 126
 127   void EmitFunctionBodyEnd() override;
 128
 129   MCSymbol *GetCPISymbol(unsigned CPID) const override;
 130   void EmitEndOfAsmFile(Module &M) override;
 131
 132   AArch64FunctionInfo *AArch64FI = nullptr;
 133
 134   /// Emit the LOHs contained in AArch64FI.
 135   void EmitLOHs();
 136
 137   /// Emit instruction to set float register to zero.
 138   void EmitFMov0(const MachineInstr &MI);
 139
 140   using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
 141
 142   MInstToMCSymbol LOHInstToLabel;
 143 };
 144
 145 } // end anonymous namespace
 146
 147 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
 148 {
 149   EmitSled(MI, SledKind::FUNCTION_ENTER);
 150 }
 151
 152 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
 153 {
 154   EmitSled(MI, SledKind::FUNCTION_EXIT);
 155 }
 156
 157 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
 158 {
 159   EmitSled(MI, SledKind::TAIL_CALL);
 160 }
 161
 162 void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
 163 {
 164   static const int8_t NoopsInSledCount = 7;
 165   // We want to emit the following pattern:
 166   //
 167   // .Lxray_sled_N:
 168   //   ALIGN
 169   //   B #32
 170   //   ; 7 NOP instructions (28 bytes)
 171   // .tmpN
 172   //
 173   // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
 174   // over the full 32 bytes (8 instructions) with the following pattern:
 175   //
 176   //   STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
 177   //   LDR W0, #12 ; W0 := function ID
 178   //   LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
 179   //   BLR X16 ; call the tracing trampoline
 180   //   ;DATA: 32 bits of function ID
 181   //   ;DATA: lower 32 bits of the address of the trampoline
 182   //   ;DATA: higher 32 bits of the address of the trampoline
 183   //   LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
 184   //
 185   OutStreamer->EmitCodeAlignment(4);
 186   auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
 187   OutStreamer->EmitLabel(CurSled);
 188   auto Target = OutContext.createTempSymbol();
 189
 190   // Emit "B #32" instruction, which jumps over the next 28 bytes.
 191   // The operand has to be the number of 4-byte instructions to jump over,
 192   // including the current instruction.
 193   EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
 194
 195   for (int8_t I = 0; I < NoopsInSledCount; I++)
 196     EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
 197
 198   OutStreamer->EmitLabel(Target);
 199   recordSled(CurSled, MI, Kind);
 200 }
 201
 202 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
 203   const Triple &TT = TM.getTargetTriple();
 204   if (TT.isOSBinFormatMachO()) {
 205     // Funny Darwin hack: This flag tells the linker that no global symbols
 206     // contain code that falls through to other global symbols (e.g. the obvious
 207     // implementation of multiple entry points).  If this doesn't occur, the
 208     // linker can safely perform dead code stripping.  Since LLVM never
 209     // generates code that does this, it is always safe to set.
 210     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
 211     SM.serializeToStackMapSection();
 212   }
 213 }
 214
 215 void AArch64AsmPrinter::EmitLOHs() {
 216   SmallVector<MCSymbol *, 3> MCArgs;
 217
 218   for (const auto &D : AArch64FI->getLOHContainer()) {
 219     for (const MachineInstr *MI : D.getArgs()) {
 220       MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
 221       assert(LabelIt != LOHInstToLabel.end() &&
 222              "Label hasn't been inserted for LOH related instruction");
 223       MCArgs.push_back(LabelIt->second);
 224     }
 225     OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
 226     MCArgs.clear();
 227   }
 228 }
 229
 230 void AArch64AsmPrinter::EmitFunctionBodyEnd() {
 231   if (!AArch64FI->getLOHRelated().empty())
 232     EmitLOHs();
 233 }
 234
 235 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
 236 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
 237   // Darwin uses a linker-private symbol name for constant-pools (to
 238   // avoid addends on the relocation?), ELF has no such concept and
 239   // uses a normal private symbol.
 240   if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
 241     return OutContext.getOrCreateSymbol(
 242         Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
 243         Twine(getFunctionNumber()) + "_" + Twine(CPID));
 244
 245   return OutContext.getOrCreateSymbol(
 246       Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
 247       Twine(getFunctionNumber()) + "_" + Twine(CPID));
 248 }
 249
 250 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
 251                                      raw_ostream &O) {
 252   const MachineOperand &MO = MI->getOperand(OpNum);
 253   switch (MO.getType()) {
 254   default:
 255     llvm_unreachable("<unknown operand type>");
 256   case MachineOperand::MO_Register: {
 257     unsigned Reg = MO.getReg();
 258     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
 259     assert(!MO.getSubReg() && "Subregs should be eliminated!");
 260     O << AArch64InstPrinter::getRegisterName(Reg);
 261     break;
 262   }
 263   case MachineOperand::MO_Immediate: {
 264     int64_t Imm = MO.getImm();
 265     O << '#' << Imm;
 266     break;
 267   }
 268   case MachineOperand::MO_GlobalAddress: {
 269     const GlobalValue *GV = MO.getGlobal();
 270     MCSymbol *Sym = getSymbol(GV);
 271
 272     // FIXME: Can we get anything other than a plain symbol here?
 273     assert(!MO.getTargetFlags() && "Unknown operand target flag!");
 274
 275     Sym->print(O, MAI);
 276     printOffset(MO.getOffset(), O);
 277     break;
 278   }
 279   case MachineOperand::MO_BlockAddress: {
 280     MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
 281     Sym->print(O, MAI);
 282     break;
 283   }
 284   }
 285 }
 286
 287 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
 288                                           raw_ostream &O) {
 289   unsigned Reg = MO.getReg();
 290   switch (Mode) {
 291   default:
 292     return true; // Unknown mode.
 293   case 'w':
 294     Reg = getWRegFromXReg(Reg);
 295     break;
 296   case 'x':
 297     Reg = getXRegFromWReg(Reg);
 298     break;
 299   }
 300
 301   O << AArch64InstPrinter::getRegisterName(Reg);
 302   return false;
 303 }
 304
 305 // Prints the register in MO using class RC using the offset in the
 306 // new register class. This should not be used for cross class
 307 // printing.
 308 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
 309                                            const TargetRegisterClass *RC,
 310                                            bool isVector, raw_ostream &O) {
 311   assert(MO.isReg() && "Should only get here with a register!");
 312   const TargetRegisterInfo *RI = STI->getRegisterInfo();
 313   unsigned Reg = MO.getReg();
 314   unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
 315   assert(RI->regsOverlap(RegToPrint, Reg));
 316   O << AArch64InstPrinter::getRegisterName(
 317            RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
 318   return false;
 319 }
 320
 321 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
 322                                         unsigned AsmVariant,
 323                                         const char *ExtraCode, raw_ostream &O) {
 324   const MachineOperand &MO = MI->getOperand(OpNum);
 325
 326   // First try the generic code, which knows about modifiers like 'c' and 'n'.
 327   if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
 328     return false;
 329
 330   // Does this asm operand have a single letter operand modifier?
 331   if (ExtraCode && ExtraCode[0]) {
 332     if (ExtraCode[1] != 0)
 333       return true; // Unknown modifier.
 334
 335     switch (ExtraCode[0]) {
 336     default:
 337       return true; // Unknown modifier.
 338     case 'a':      // Print 'a' modifier
 339       PrintAsmMemoryOperand(MI, OpNum, AsmVariant, ExtraCode, O);
 340       return false;
 341     case 'w':      // Print W register
 342     case 'x':      // Print X register
 343       if (MO.isReg())
 344         return printAsmMRegister(MO, ExtraCode[0], O);
 345       if (MO.isImm() && MO.getImm() == 0) {
 346         unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
 347         O << AArch64InstPrinter::getRegisterName(Reg);
 348         return false;
 349       }
 350       printOperand(MI, OpNum, O);
 351       return false;
 352     case 'b': // Print B register.
 353     case 'h': // Print H register.
 354     case 's': // Print S register.
 355     case 'd': // Print D register.
 356     case 'q': // Print Q register.
 357       if (MO.isReg()) {
 358         const TargetRegisterClass *RC;
 359         switch (ExtraCode[0]) {
 360         case 'b':
 361           RC = &AArch64::FPR8RegClass;
 362           break;
 363         case 'h':
 364           RC = &AArch64::FPR16RegClass;
 365           break;
 366         case 's':
 367           RC = &AArch64::FPR32RegClass;
 368           break;
 369         case 'd':
 370           RC = &AArch64::FPR64RegClass;
 371           break;
 372         case 'q':
 373           RC = &AArch64::FPR128RegClass;
 374           break;
 375         default:
 376           return true;
 377         }
 378         return printAsmRegInClass(MO, RC, false /* vector */, O);
 379       }
 380       printOperand(MI, OpNum, O);
 381       return false;
 382     }
 383   }
 384
 385   // According to ARM, we should emit x and v registers unless we have a
 386   // modifier.
 387   if (MO.isReg()) {
 388     unsigned Reg = MO.getReg();
 389
 390     // If this is a w or x register, print an x register.
 391     if (AArch64::GPR32allRegClass.contains(Reg) ||
 392         AArch64::GPR64allRegClass.contains(Reg))
 393       return printAsmMRegister(MO, 'x', O);
 394
 395     // If this is a b, h, s, d, or q register, print it as a v register.
 396     return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
 397                               O);
 398   }
 399
 400   printOperand(MI, OpNum, O);
 401   return false;
 402 }
 403
 404 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 405                                               unsigned OpNum,
 406                                               unsigned AsmVariant,
 407                                               const char *ExtraCode,
 408                                               raw_ostream &O) {
 409   if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
 410     return true; // Unknown modifier.
 411
 412   const MachineOperand &MO = MI->getOperand(OpNum);
 413   assert(MO.isReg() && "unexpected inline asm memory operand");
 414   O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
 415   return false;
 416 }
 417
 418 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
 419                                                raw_ostream &OS) {
 420   unsigned NOps = MI->getNumOperands();
 421   assert(NOps == 4);
 422   OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
 423   // cast away const; DIetc do not take const operands for some reason.
 424   OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
 425             ->getName();
 426   OS << " <- ";
 427   // Frame address.  Currently handles register +- offset only.
 428   assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
 429   OS << '[';
 430   printOperand(MI, 0, OS);
 431   OS << '+';
 432   printOperand(MI, 1, OS);
 433   OS << ']';
 434   OS << "+";
 435   printOperand(MI, NOps - 2, OS);
 436 }
 437
 438 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
 439                                       const MachineInstr &MI) {
 440   unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
 441
 442   SM.recordStackMap(MI);
 443   assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
 444
 445   // Scan ahead to trim the shadow.
 446   const MachineBasicBlock &MBB = *MI.getParent();
 447   MachineBasicBlock::const_iterator MII(MI);
 448   ++MII;
 449   while (NumNOPBytes > 0) {
 450     if (MII == MBB.end() || MII->isCall() ||
 451         MII->getOpcode() == AArch64::DBG_VALUE ||
 452         MII->getOpcode() == TargetOpcode::PATCHPOINT ||
 453         MII->getOpcode() == TargetOpcode::STACKMAP)
 454       break;
 455     ++MII;
 456     NumNOPBytes -= 4;
 457   }
 458
 459   // Emit nops.
 460   for (unsigned i = 0; i < NumNOPBytes; i += 4)
 461     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
 462 }
 463
 464 // Lower a patchpoint of the form:
 465 // [<def>], <id>, <numBytes>, <target>, <numArgs>
 466 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
 467                                         const MachineInstr &MI) {
 468   SM.recordPatchPoint(MI);
 469
 470   PatchPointOpers Opers(&MI);
 471
 472   int64_t CallTarget = Opers.getCallTarget().getImm();
 473   unsigned EncodedBytes = 0;
 474   if (CallTarget) {
 475     assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
 476            "High 16 bits of call target should be zero.");
 477     unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
 478     EncodedBytes = 16;
 479     // Materialize the jump address:
 480     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
 481                                     .addReg(ScratchReg)
 482                                     .addImm((CallTarget >> 32) & 0xFFFF)
 483                                     .addImm(32));
 484     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
 485                                     .addReg(ScratchReg)
 486                                     .addReg(ScratchReg)
 487                                     .addImm((CallTarget >> 16) & 0xFFFF)
 488                                     .addImm(16));
 489     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
 490                                     .addReg(ScratchReg)
 491                                     .addReg(ScratchReg)
 492                                     .addImm(CallTarget & 0xFFFF)
 493                                     .addImm(0));
 494     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
 495   }
 496   // Emit padding.
 497   unsigned NumBytes = Opers.getNumPatchBytes();
 498   assert(NumBytes >= EncodedBytes &&
 499          "Patchpoint can't request size less than the length of a call.");
 500   assert((NumBytes - EncodedBytes) % 4 == 0 &&
 501          "Invalid number of NOP bytes requested!");
 502   for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
 503     EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
 504 }
 505
 506 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
 507   unsigned DestReg = MI.getOperand(0).getReg();
 508   if (STI->hasZeroCycleZeroing() && !STI->hasZeroCycleZeroingFPWorkaround()) {
 509     // Convert H/S/D register to corresponding Q register
 510     if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
 511       DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
 512     else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
 513       DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
 514     else {
 515       assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
 516       DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
 517     }
 518     MCInst MOVI;
 519     MOVI.setOpcode(AArch64::MOVIv2d_ns);
 520     MOVI.addOperand(MCOperand::createReg(DestReg));
 521     MOVI.addOperand(MCOperand::createImm(0));
 522     EmitToStreamer(*OutStreamer, MOVI);
 523   } else {
 524     MCInst FMov;
 525     switch (MI.getOpcode()) {
 526     default: llvm_unreachable("Unexpected opcode");
 527     case AArch64::FMOVH0:
 528       FMov.setOpcode(AArch64::FMOVWHr);
 529       FMov.addOperand(MCOperand::createReg(DestReg));
 530       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
 531       break;
 532     case AArch64::FMOVS0:
 533       FMov.setOpcode(AArch64::FMOVWSr);
 534       FMov.addOperand(MCOperand::createReg(DestReg));
 535       FMov.addOperand(MCOperand::createReg(AArch64::WZR));
 536       break;
 537     case AArch64::FMOVD0:
 538       FMov.setOpcode(AArch64::FMOVXDr);
 539       FMov.addOperand(MCOperand::createReg(DestReg));
 540       FMov.addOperand(MCOperand::createReg(AArch64::XZR));
 541       break;
 542     }
 543     EmitToStreamer(*OutStreamer, FMov);
 544   }
 545 }
 546
 547 // Simple pseudo-instructions have their lowering (with expansion to real
 548 // instructions) auto-generated.
 549 #include "AArch64GenMCPseudoLowering.inc"
 550
 551 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
 552   // Do any auto-generated pseudo lowerings.
 553   if (emitPseudoExpansionLowering(*OutStreamer, MI))
 554     return;
 555
 556   if (AArch64FI->getLOHRelated().count(MI)) {
 557     // Generate a label for LOH related instruction
 558     MCSymbol *LOHLabel = createTempSymbol("loh");
 559     // Associate the instruction with the label
 560     LOHInstToLabel[MI] = LOHLabel;
 561     OutStreamer->EmitLabel(LOHLabel);
 562   }
 563
 564   // Do any manual lowerings.
 565   switch (MI->getOpcode()) {
 566   default:
 567     break;
 568   case AArch64::MOVIv2d_ns:
 569     // If the target has <rdar://problem/16473581>, lower this
 570     // instruction to movi.16b instead.
 571     if (STI->hasZeroCycleZeroingFPWorkaround() &&
 572         MI->getOperand(1).getImm() == 0) {
 573       MCInst TmpInst;
 574       TmpInst.setOpcode(AArch64::MOVIv16b_ns);
 575       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
 576       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
 577       EmitToStreamer(*OutStreamer, TmpInst);
 578       return;
 579     }
 580     break;
 581
 582   case AArch64::DBG_VALUE: {
 583     if (isVerbose() && OutStreamer->hasRawTextSupport()) {
 584       SmallString<128> TmpStr;
 585       raw_svector_ostream OS(TmpStr);
 586       PrintDebugValueComment(MI, OS);
 587       OutStreamer->EmitRawText(StringRef(OS.str()));
 588     }
 589     return;
 590   }
 591
 592   // Tail calls use pseudo instructions so they have the proper code-gen
 593   // attributes (isCall, isReturn, etc.). We lower them to the real
 594   // instruction here.
 595   case AArch64::TCRETURNri: {
 596     MCInst TmpInst;
 597     TmpInst.setOpcode(AArch64::BR);
 598     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
 599     EmitToStreamer(*OutStreamer, TmpInst);
 600     return;
 601   }
 602   case AArch64::TCRETURNdi: {
 603     MCOperand Dest;
 604     MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
 605     MCInst TmpInst;
 606     TmpInst.setOpcode(AArch64::B);
 607     TmpInst.addOperand(Dest);
 608     EmitToStreamer(*OutStreamer, TmpInst);
 609     return;
 610   }
 611   case AArch64::TLSDESC_CALLSEQ: {
 612     /// lower this to:
 613     ///    adrp  x0, :tlsdesc:var
 614     ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
 615     ///    add   x0, x0, #:tlsdesc_lo12:var
 616     ///    .tlsdesccall var
 617     ///    blr   x1
 618     ///    (TPIDR_EL0 offset now in x0)
 619     const MachineOperand &MO_Sym = MI->getOperand(0);
 620     MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
 621     MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
 622     MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
 623     MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
 624     MCInstLowering.lowerOperand(MO_Sym, Sym);
 625     MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
 626     MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
 627
 628     MCInst Adrp;
 629     Adrp.setOpcode(AArch64::ADRP);
 630     Adrp.addOperand(MCOperand::createReg(AArch64::X0));
 631     Adrp.addOperand(SymTLSDesc);
 632     EmitToStreamer(*OutStreamer, Adrp);
 633
 634     MCInst Ldr;
 635     Ldr.setOpcode(AArch64::LDRXui);
 636     Ldr.addOperand(MCOperand::createReg(AArch64::X1));
 637     Ldr.addOperand(MCOperand::createReg(AArch64::X0));
 638     Ldr.addOperand(SymTLSDescLo12);
 639     Ldr.addOperand(MCOperand::createImm(0));
 640     EmitToStreamer(*OutStreamer, Ldr);
 641
 642     MCInst Add;
 643     Add.setOpcode(AArch64::ADDXri);
 644     Add.addOperand(MCOperand::createReg(AArch64::X0));
 645     Add.addOperand(MCOperand::createReg(AArch64::X0));
 646     Add.addOperand(SymTLSDescLo12);
 647     Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
 648     EmitToStreamer(*OutStreamer, Add);
 649
 650     // Emit a relocation-annotation. This expands to no code, but requests
 651     // the following instruction gets an R_AARCH64_TLSDESC_CALL.
 652     MCInst TLSDescCall;
 653     TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
 654     TLSDescCall.addOperand(Sym);
 655     EmitToStreamer(*OutStreamer, TLSDescCall);
 656
 657     MCInst Blr;
 658     Blr.setOpcode(AArch64::BLR);
 659     Blr.addOperand(MCOperand::createReg(AArch64::X1));
 660     EmitToStreamer(*OutStreamer, Blr);
 661
 662     return;
 663   }
 664
 665   case AArch64::FMOVH0:
 666   case AArch64::FMOVS0:
 667   case AArch64::FMOVD0:
 668     EmitFMov0(*MI);
 669     return;
 670
 671   case TargetOpcode::STACKMAP:
 672     return LowerSTACKMAP(*OutStreamer, SM, *MI);
 673
 674   case TargetOpcode::PATCHPOINT:
 675     return LowerPATCHPOINT(*OutStreamer, SM, *MI);
 676
 677   case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
 678     LowerPATCHABLE_FUNCTION_ENTER(*MI);
 679     return;
 680
 681   case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
 682     LowerPATCHABLE_FUNCTION_EXIT(*MI);
 683     return;
 684
 685   case TargetOpcode::PATCHABLE_TAIL_CALL:
 686     LowerPATCHABLE_TAIL_CALL(*MI);
 687     return;
 688   }
 689
 690   // Finally, do the automated lowerings for everything else.
 691   MCInst TmpInst;
 692   MCInstLowering.Lower(MI, TmpInst);
 693   EmitToStreamer(*OutStreamer, TmpInst);
 694 }
 695
 696 // Force static initialization.
 697 extern "C" void LLVMInitializeAArch64AsmPrinter() {
 698   RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
 699   RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
 700   RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
 701 }