lib/Target/AMDGPU/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// Interface definition of the TargetLowering class that is common
  12 /// to all AMD GPUs.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
  17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
  18
  19 #include "AMDGPU.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/TargetLowering.h"
  22
  23 namespace llvm {
  24
  25 class AMDGPUMachineFunction;
  26 class AMDGPUSubtarget;
  27 struct ArgDescriptor;
  28
  29 class AMDGPUTargetLowering : public TargetLowering {
  30 private:
  31   const AMDGPUSubtarget *Subtarget;
  32
  33   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
  34   /// legalized from a smaller type VT. Need to match pre-legalized type because
  35   /// the generic legalization inserts the add/sub between the select and
  36   /// compare.
  37   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
  38
  39 public:
  40   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
  41   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
  42
  43 protected:
  44   AMDGPUAS AMDGPUASI;
  45
  46   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
  47   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
  48   /// Split a vector store into multiple scalar stores.
  49   /// \returns The resulting chain.
  50
  51   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
  52   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
  53   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
  54   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
  55   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
  56
  57   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
  58   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
  59   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
  60   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
  61   SDValue LowerFLOG(SDValue Op, SelectionDAG &Dag,
  62                     double Log2BaseInverted) const;
  63
  64   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
  65
  66   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  67   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  68   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
  69   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
  70
  71   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  72   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
  73   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
  74   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
  75
  76   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
  77
  78 protected:
  79   bool shouldCombineMemoryType(EVT VT) const;
  80   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  81   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  82   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  83
  84   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
  85                                        unsigned Opc, SDValue LHS,
  86                                        uint32_t ValLo, uint32_t ValHi) const;
  87   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  88   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  89   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  90   SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  91   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  92   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  93   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  94   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
  95   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
  96                              SDValue RHS, DAGCombinerInfo &DCI) const;
  97   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  98   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  99   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 100   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 101
 102   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
 103
 104   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
 105                                      SelectionDAG &DAG) const;
 106
 107   /// Return 64-bit value Op as two 32-bit integers.
 108   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
 109                                               SelectionDAG &DAG) const;
 110   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
 111   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
 112
 113   /// Split a vector load into 2 loads of half the vector.
 114   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
 115
 116   /// Split a vector store into 2 stores of half the vector.
 117   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
 118
 119   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 120   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
 121   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
 122   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
 123   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
 124                                     SmallVectorImpl<SDValue> &Results) const;
 125   void analyzeFormalArgumentsCompute(CCState &State,
 126                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
 127 public:
 128   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
 129
 130   bool mayIgnoreSignedZero(SDValue Op) const {
 131     if (getTargetMachine().Options.NoSignedZerosFPMath)
 132       return true;
 133
 134     const auto Flags = Op.getNode()->getFlags();
 135     if (Flags.isDefined())
 136       return Flags.hasNoSignedZeros();
 137
 138     return false;
 139   }
 140
 141   static inline SDValue stripBitcast(SDValue Val) {
 142     return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
 143   }
 144
 145   static bool allUsesHaveSourceMods(const SDNode *N,
 146                                     unsigned CostThreshold = 4);
 147   bool isFAbsFree(EVT VT) const override;
 148   bool isFNegFree(EVT VT) const override;
 149   bool isTruncateFree(EVT Src, EVT Dest) const override;
 150   bool isTruncateFree(Type *Src, Type *Dest) const override;
 151
 152   bool isZExtFree(Type *Src, Type *Dest) const override;
 153   bool isZExtFree(EVT Src, EVT Dest) const override;
 154   bool isZExtFree(SDValue Val, EVT VT2) const override;
 155
 156   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
 157
 158   MVT getVectorIdxTy(const DataLayout &) const override;
 159   bool isSelectSupported(SelectSupportKind) const override;
 160
 161   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 162   bool ShouldShrinkFPConstant(EVT VT) const override;
 163   bool shouldReduceLoadWidth(SDNode *Load,
 164                              ISD::LoadExtType ExtType,
 165                              EVT ExtVT) const override;
 166
 167   bool isLoadBitCastBeneficial(EVT, EVT) const final;
 168
 169   bool storeOfVectorConstantIsCheap(EVT MemVT,
 170                                     unsigned NumElem,
 171                                     unsigned AS) const override;
 172   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
 173   bool isCheapToSpeculateCttz() const override;
 174   bool isCheapToSpeculateCtlz() const override;
 175
 176   bool isSDNodeAlwaysUniform(const SDNode *N) const override;
 177   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
 178   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
 179
 180   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 181                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 182                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 183                       SelectionDAG &DAG) const override;
 184
 185   SDValue addTokenForArgument(SDValue Chain,
 186                               SelectionDAG &DAG,
 187                               MachineFrameInfo &MFI,
 188                               int ClobberedFI) const;
 189
 190   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
 191                              SmallVectorImpl<SDValue> &InVals,
 192                              StringRef Reason) const;
 193   SDValue LowerCall(CallLoweringInfo &CLI,
 194                     SmallVectorImpl<SDValue> &InVals) const override;
 195
 196   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
 197                                   SelectionDAG &DAG) const;
 198
 199   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 200   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 201   void ReplaceNodeResults(SDNode * N,
 202                           SmallVectorImpl<SDValue> &Results,
 203                           SelectionDAG &DAG) const override;
 204
 205   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
 206                                SDValue RHS, SDValue True, SDValue False,
 207                                SDValue CC, DAGCombinerInfo &DCI) const;
 208
 209   const char* getTargetNodeName(unsigned Opcode) const override;
 210
 211   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection
 212   // for AMDGPU.
 213   // A commit ( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
 214   // 91177308-0d34-0410-b5e6-96231b3b80d8 ) turned on
 215   // MergeConsecutiveStores() before Instruction Selection for all targets.
 216   // Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores()
 217   // merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores()
 218   // re-merges, etc. ) to warrant turning it off for now.
 219   bool mergeStoresAfterLegalization() const override { return false; }
 220
 221   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
 222     return true;
 223   }
 224   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
 225                            int &RefinementSteps, bool &UseOneConstNR,
 226                            bool Reciprocal) const override;
 227   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
 228                            int &RefinementSteps) const override;
 229
 230   virtual SDNode *PostISelFolding(MachineSDNode *N,
 231                                   SelectionDAG &DAG) const = 0;
 232
 233   /// Determine which of the bits specified in \p Mask are known to be
 234   /// either zero or one and return them in the \p KnownZero and \p KnownOne
 235   /// bitsets.
 236   void computeKnownBitsForTargetNode(const SDValue Op,
 237                                      KnownBits &Known,
 238                                      const APInt &DemandedElts,
 239                                      const SelectionDAG &DAG,
 240                                      unsigned Depth = 0) const override;
 241
 242   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
 243                                            const SelectionDAG &DAG,
 244                                            unsigned Depth = 0) const override;
 245
 246   /// Helper function that adds Reg to the LiveIn list of the DAG's
 247   /// MachineFunction.
 248   ///
 249   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
 250   /// a copy from the register.
 251   SDValue CreateLiveInRegister(SelectionDAG &DAG,
 252                                const TargetRegisterClass *RC,
 253                                unsigned Reg, EVT VT,
 254                                const SDLoc &SL,
 255                                bool RawReg = false) const;
 256   SDValue CreateLiveInRegister(SelectionDAG &DAG,
 257                                const TargetRegisterClass *RC,
 258                                unsigned Reg, EVT VT) const {
 259     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
 260   }
 261
 262   // Returns the raw live in register rather than a copy from it.
 263   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
 264                                   const TargetRegisterClass *RC,
 265                                   unsigned Reg, EVT VT) const {
 266     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
 267   }
 268
 269   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
 270   /// slot rather than passed in a register.
 271   SDValue loadStackInputValue(SelectionDAG &DAG,
 272                               EVT VT,
 273                               const SDLoc &SL,
 274                               int64_t Offset) const;
 275
 276   SDValue storeStackInputValue(SelectionDAG &DAG,
 277                                const SDLoc &SL,
 278                                SDValue Chain,
 279                                SDValue StackPtr,
 280                                SDValue ArgVal,
 281                                int64_t Offset) const;
 282
 283   SDValue loadInputValue(SelectionDAG &DAG,
 284                          const TargetRegisterClass *RC,
 285                          EVT VT, const SDLoc &SL,
 286                          const ArgDescriptor &Arg) const;
 287
 288   enum ImplicitParameter {
 289     FIRST_IMPLICIT,
 290     GRID_DIM = FIRST_IMPLICIT,
 291     GRID_OFFSET,
 292   };
 293
 294   /// Helper function that returns the byte offset of the given
 295   /// type of implicit parameter.
 296   uint32_t getImplicitParameterOffset(const MachineFunction &MF,
 297                                       const ImplicitParameter Param) const;
 298
 299   AMDGPUAS getAMDGPUAS() const {
 300     return AMDGPUASI;
 301   }
 302
 303   MVT getFenceOperandTy(const DataLayout &DL) const override {
 304     return MVT::i32;
 305   }
 306 };
 307
 308 namespace AMDGPUISD {
 309
 310 enum NodeType : unsigned {
 311   // AMDIL ISD Opcodes
 312   FIRST_NUMBER = ISD::BUILTIN_OP_END,
 313   UMUL,        // 32bit unsigned multiplication
 314   BRANCH_COND,
 315   // End AMDIL ISD Opcodes
 316
 317   // Function call.
 318   CALL,
 319   TC_RETURN,
 320   TRAP,
 321
 322   // Masked control flow nodes.
 323   IF,
 324   ELSE,
 325   LOOP,
 326
 327   // A uniform kernel return that terminates the wavefront.
 328   ENDPGM,
 329
 330   // Return to a shader part's epilog code.
 331   RETURN_TO_EPILOG,
 332
 333   // Return with values from a non-entry function.
 334   RET_FLAG,
 335
 336   DWORDADDR,
 337   FRACT,
 338
 339   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
 340   /// modifier behavior with dx10_enable.
 341   CLAMP,
 342
 343   // This is SETCC with the full mask result which is used for a compare with a
 344   // result bit per item in the wavefront.
 345   SETCC,
 346   SETREG,
 347   // FP ops with input and output chain.
 348   FMA_W_CHAIN,
 349   FMUL_W_CHAIN,
 350
 351   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
 352   // Denormals handled on some parts.
 353   COS_HW,
 354   SIN_HW,
 355   FMAX_LEGACY,
 356   FMIN_LEGACY,
 357   FMAX3,
 358   SMAX3,
 359   UMAX3,
 360   FMIN3,
 361   SMIN3,
 362   UMIN3,
 363   FMED3,
 364   SMED3,
 365   UMED3,
 366   URECIP,
 367   DIV_SCALE,
 368   DIV_FMAS,
 369   DIV_FIXUP,
 370   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
 371   // treated as an illegal operation.
 372   FMAD_FTZ,
 373   TRIG_PREOP, // 1 ULP max error for f64
 374
 375   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
 376   //            For f64, max error 2^29 ULP, handles denormals.
 377   RCP,
 378   RSQ,
 379   RCP_LEGACY,
 380   RSQ_LEGACY,
 381   RCP_IFLAG,
 382   FMUL_LEGACY,
 383   RSQ_CLAMP,
 384   LDEXP,
 385   FP_CLASS,
 386   DOT4,
 387   CARRY,
 388   BORROW,
 389   BFE_U32, // Extract range of bits with zero extension to 32-bits.
 390   BFE_I32, // Extract range of bits with sign extension to 32-bits.
 391   BFI, // (src0 & src1) | (~src0 & src2)
 392   BFM, // Insert a range of bits into a 32-bit word.
 393   FFBH_U32, // ctlz with -1 if input is zero.
 394   FFBH_I32,
 395   FFBL_B32, // cttz with -1 if input is zero.
 396   MUL_U24,
 397   MUL_I24,
 398   MULHI_U24,
 399   MULHI_I24,
 400   MAD_U24,
 401   MAD_I24,
 402   MAD_U64_U32,
 403   MAD_I64_I32,
 404   MUL_LOHI_I24,
 405   MUL_LOHI_U24,
 406   PERM,
 407   TEXTURE_FETCH,
 408   EXPORT, // exp on SI+
 409   EXPORT_DONE, // exp on SI+ with done bit set
 410   R600_EXPORT,
 411   CONST_ADDRESS,
 412   REGISTER_LOAD,
 413   REGISTER_STORE,
 414   SAMPLE,
 415   SAMPLEB,
 416   SAMPLED,
 417   SAMPLEL,
 418
 419   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
 420   CVT_F32_UBYTE0,
 421   CVT_F32_UBYTE1,
 422   CVT_F32_UBYTE2,
 423   CVT_F32_UBYTE3,
 424
 425   // Convert two float 32 numbers into a single register holding two packed f16
 426   // with round to zero.
 427   CVT_PKRTZ_F16_F32,
 428   CVT_PKNORM_I16_F32,
 429   CVT_PKNORM_U16_F32,
 430   CVT_PK_I16_I32,
 431   CVT_PK_U16_U32,
 432
 433   // Same as the standard node, except the high bits of the resulting integer
 434   // are known 0.
 435   FP_TO_FP16,
 436
 437   // Wrapper around fp16 results that are known to zero the high bits.
 438   FP16_ZEXT,
 439
 440   /// This node is for VLIW targets and it is used to represent a vector
 441   /// that is stored in consecutive registers with the same channel.
 442   /// For example:
 443   ///   |X  |Y|Z|W|
 444   /// T0|v.x| | | |
 445   /// T1|v.y| | | |
 446   /// T2|v.z| | | |
 447   /// T3|v.w| | | |
 448   BUILD_VERTICAL_VECTOR,
 449   /// Pointer to the start of the shader's constant data.
 450   CONST_DATA_PTR,
 451   INIT_EXEC,
 452   INIT_EXEC_FROM_INPUT,
 453   SENDMSG,
 454   SENDMSGHALT,
 455   INTERP_MOV,
 456   INTERP_P1,
 457   INTERP_P2,
 458   PC_ADD_REL_OFFSET,
 459   KILL,
 460   DUMMY_CHAIN,
 461   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
 462   STORE_MSKOR,
 463   LOAD_CONSTANT,
 464   TBUFFER_STORE_FORMAT,
 465   TBUFFER_STORE_FORMAT_X3,
 466   TBUFFER_STORE_FORMAT_D16,
 467   TBUFFER_LOAD_FORMAT,
 468   TBUFFER_LOAD_FORMAT_D16,
 469   ATOMIC_CMP_SWAP,
 470   ATOMIC_INC,
 471   ATOMIC_DEC,
 472   ATOMIC_LOAD_FADD,
 473   ATOMIC_LOAD_FMIN,
 474   ATOMIC_LOAD_FMAX,
 475   BUFFER_LOAD,
 476   BUFFER_LOAD_FORMAT,
 477   BUFFER_LOAD_FORMAT_D16,
 478   BUFFER_STORE,
 479   BUFFER_STORE_FORMAT,
 480   BUFFER_STORE_FORMAT_D16,
 481   BUFFER_ATOMIC_SWAP,
 482   BUFFER_ATOMIC_ADD,
 483   BUFFER_ATOMIC_SUB,
 484   BUFFER_ATOMIC_SMIN,
 485   BUFFER_ATOMIC_UMIN,
 486   BUFFER_ATOMIC_SMAX,
 487   BUFFER_ATOMIC_UMAX,
 488   BUFFER_ATOMIC_AND,
 489   BUFFER_ATOMIC_OR,
 490   BUFFER_ATOMIC_XOR,
 491   BUFFER_ATOMIC_CMPSWAP,
 492
 493   LAST_AMDGPU_ISD_NUMBER
 494 };
 495
 496
 497 } // End namespace AMDGPUISD
 498
 499 } // End namespace llvm
 500
 501 #endif