lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  24                                              "true", "Thumb mode">;
  25
  26 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  27                                              "true", "Use software floating "
  28                                              "point features.">;
  29
  30
  31 //===----------------------------------------------------------------------===//
  32 // ARM Subtarget features.
  33 //
  34
  35 // Floating Point, HW Division and Neon Support
  36 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  37                                              "Enable VFP2 instructions">;
  38
  39 def FeatureVFP3           : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  40                                              "Enable VFP3 instructions",
  41                                              [FeatureVFP2]>;
  42
  43 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  44                                              "Enable NEON instructions",
  45                                              [FeatureVFP3]>;
  46
  47 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  48                                              "Enable half-precision "
  49                                              "floating point">;
  50
  51 def FeatureVFP4           : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  52                                              "Enable VFP4 instructions",
  53                                              [FeatureVFP3, FeatureFP16]>;
  54
  55 def FeatureFPARMv8        : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  56                                              "true", "Enable ARMv8 FP",
  57                                              [FeatureVFP4]>;
  58
  59 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  60                                              "Enable full half-precision "
  61                                              "floating point",
  62                                              [FeatureFPARMv8]>;
  63
  64 def FeatureVFPOnlySP      : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  65                                              "Floating point unit supports "
  66                                              "single precision only">;
  67
  68 def FeatureD16            : SubtargetFeature<"d16", "HasD16", "true",
  69                                              "Restrict FP to 16 double registers">;
  70
  71 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
  72                                              "HasHardwareDivideInThumb", "true",
  73                                              "Enable divide instructions in Thumb">;
  74
  75 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
  76                                              "HasHardwareDivideInARM", "true",
  77                                              "Enable divide instructions in ARM mode">;
  78
  79 // Atomic Support
  80 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
  81                                              "Has data barrier (dmb/dsb) instructions">;
  82
  83 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  84                                              "Has v7 clrex instruction">;
  85
  86 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
  87                                    "Has full data barrier (dfb) instruction">;
  88
  89 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  90                                              "HasAcquireRelease", "true",
  91                                              "Has v8 acquire/release (lda/ldaex "
  92                                              " etc) instructions">;
  93
  94
  95 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  96                                              "FP compare + branch is slow">;
  97
  98 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  99                                              "Enable support for Performance "
 100                                              "Monitor extensions">;
 101
 102
 103 // TrustZone Security Extensions
 104 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 105                                              "Enable support for TrustZone "
 106                                              "security extensions">;
 107
 108 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 109                                              "Enable support for ARMv8-M "
 110                                              "Security Extensions">;
 111
 112 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 113                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 114
 115 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 116                                              "Enable AES support", [FeatureNEON]>;
 117
 118 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 119                                              "Enable support for "
 120                                              "Cryptography extensions",
 121                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 122
 123 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 124                                              "Enable support for CRC instructions">;
 125
 126 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 127                                              "Enable support for dot product instructions",
 128                                              [FeatureNEON]>;
 129
 130 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 131 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 132                                              "Enable Reliability, Availability "
 133                                              "and Serviceability extensions">;
 134
 135 // Fast computation of non-negative address offsets
 136 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 137                                              "Enable fast computation of "
 138                                              "positive address offsets">;
 139
 140 // Fast execution of AES crypto operations
 141 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 142                                              "CPU fuses AES crypto operations">;
 143
 144 // The way of reading thread pointer
 145 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 146                                       "Reading thread pointer from register">;
 147
 148 // Cyclone can zero VFP registers in 0 cycles.
 149 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 150                                              "Has zero-cycle zeroing instructions">;
 151
 152 // Whether it is profitable to unpredicate certain instructions during if-conversion
 153 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 154                                               "IsProfitableToUnpredicate", "true",
 155                                               "Is profitable to unpredicate">;
 156
 157 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 158 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 159                                              "HasSlowVGETLNi32", "true",
 160                                              "Has slow VGETLNi32 - prefer VMOV">;
 161
 162 // Some targets (e.g. Swift) have microcoded VDUP32.
 163 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 164                                              "true",
 165                                              "Has slow VDUP32 - prefer VMOV">;
 166
 167 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 168 // for scalar FP, as this allows more effective execution domain optimization.
 169 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 170                                              "true", "Prefer VMOVSR">;
 171
 172 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 173 // than ISH
 174 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 175                                                "true", "Prefer ISHST barriers">;
 176
 177 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 178 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 179                                              "true",
 180                                              "Has muxed AGU and NEON/FPU">;
 181
 182 // Whether VLDM/VSTM starting with odd register number need more microops
 183 // than single VLDRS
 184 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 185                                               "true", "VLDM/VSTM starting "
 186                                               "with an odd register is slow">;
 187
 188 // Some targets have a renaming dependency when loading into D subregisters.
 189 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 190                                               "SlowLoadDSubregister", "true",
 191                                               "Loading into D subregs is slow">;
 192
 193 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 194 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 195                                              "DontWidenVMOVS", "true",
 196                                              "Don't widen VMOVS to VMOVD">;
 197
 198 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 199 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 200                                              "ExpandMLx", "true",
 201                                              "Expand VFP/NEON MLA/MLS instructions">;
 202
 203 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 204 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 205                                              "true", "Has VMLx hazards">;
 206
 207 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 208 // VFP to NEON, as an execution domain optimization.
 209 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 210                                              "UseNEONForFPMovs", "true",
 211                                              "Convert VMOVSR, VMOVRS, "
 212                                              "VMOVS to NEON">;
 213
 214 // Some processors benefit from using NEON instructions for scalar
 215 // single-precision FP operations. This affects instruction selection and should
 216 // only be enabled if the handling of denormals is not important.
 217 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 218                                              "UseNEONForSinglePrecisionFP",
 219                                              "true",
 220                                              "Use NEON for single precision FP">;
 221
 222 // On some processors, VLDn instructions that access unaligned data take one
 223 // extra cycle. Take that into account when computing operand latencies.
 224 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 225                                              "true",
 226                                              "Check for VLDn unaligned access">;
 227
 228 // Some processors have a nonpipelined VFP coprocessor.
 229 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 230                                               "NonpipelinedVFP", "true",
 231                                               "VFP instructions are not pipelined">;
 232
 233 // Some processors have FP multiply-accumulate instructions that don't
 234 // play nicely with other VFP / NEON instructions, and it's generally better
 235 // to just not use them.
 236 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 237                                              "Disable VFP / NEON MAC instructions">;
 238
 239 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 240 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 241                                              "HasVMLxForwarding", "true",
 242                                              "Has multiplier accumulator forwarding">;
 243
 244 // Disable 32-bit to 16-bit narrowing for experimentation.
 245 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 246                                              "Prefer 32-bit Thumb instrs">;
 247
 248 /// Some instructions update CPSR partially, which can add false dependency for
 249 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 250 /// mapped to a separate physical register. Avoid partial CPSR update for these
 251 /// processors.
 252 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 253                                                "AvoidCPSRPartialUpdate", "true",
 254                                  "Avoid CPSR partial update for OOO execution">;
 255
 256 /// Disable +1 predication cost for instructions updating CPSR.
 257 /// Enabled for Cortex-A57.
 258 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 259                                                   "CheapPredicableCPSRDef",
 260                                                   "true",
 261                   "Disable +1 predication cost for instructions updating CPSR">;
 262
 263 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 264                                              "AvoidMOVsShifterOperand", "true",
 265                                              "Avoid movs instructions with "
 266                                              "shifter operand">;
 267
 268 // Some processors perform return stack prediction. CodeGen should avoid issue
 269 // "normal" call instructions to callees which do not return.
 270 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 271                                               "HasRetAddrStack", "true",
 272                                               "Has return address stack">;
 273
 274 // Some processors have no branch predictor, which changes the expected cost of
 275 // taking a branch which affects the choice of whether to use predicated
 276 // instructions.
 277 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 278                                                    "HasBranchPredictor", "false",
 279                                                    "Has no branch predictor">;
 280
 281 /// DSP extension.
 282 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 283                                              "Supports DSP instructions in "
 284                                              "ARM and/or Thumb2">;
 285
 286 // Multiprocessing extension.
 287 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 288                                         "Supports Multiprocessing extension">;
 289
 290 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 291 def FeatureVirtualization : SubtargetFeature<"virtualization",
 292                                              "HasVirtualization", "true",
 293                                              "Supports Virtualization extension",
 294                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 295
 296 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 297 // See ARMInstrInfo.td for details.
 298 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 299                                              "NaCl trap">;
 300
 301 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 302                                              "StrictAlign", "true",
 303                                              "Disallow all unaligned memory "
 304                                              "access">;
 305
 306 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 307                                              "Generate calls via indirect call "
 308                                              "instructions">;
 309
 310 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 311                                              "GenExecuteOnly", "true",
 312                                              "Enable the generation of "
 313                                              "execute only code.">;
 314
 315 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 316                                              "Reserve R9, making it unavailable"
 317                                              " as GPR">;
 318
 319 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 320                                              "Don't use movt/movw pairs for "
 321                                              "32-bit imms">;
 322
 323 def FeatureNoNegativeImmediates
 324                           : SubtargetFeature<"no-neg-immediates",
 325                                              "NegativeImmediates", "false",
 326                                              "Convert immediates and instructions "
 327                                              "to their negated or complemented "
 328                                              "equivalent when the immediate does "
 329                                              "not fit in the encoding.">;
 330
 331 // Use the MachineScheduler for instruction scheduling for the subtarget.
 332 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 333                                         "Use the MachineScheduler">;
 334
 335 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 336     "DisablePostRAScheduler", "true",
 337     "Don't schedule again after register allocation">;
 338
 339 // Enable use of alias analysis during code generation
 340 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 341                                     "Use alias analysis during codegen">;
 342
 343 //===----------------------------------------------------------------------===//
 344 // ARM architecture class
 345 //
 346
 347 // A-series ISA
 348 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 349                                      "Is application profile ('A' series)">;
 350
 351 // R-series ISA
 352 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 353                                      "Is realtime profile ('R' series)">;
 354
 355 // M-series ISA
 356 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 357                                      "Is microcontroller profile ('M' series)">;
 358
 359
 360 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 361                                      "Enable Thumb2 instructions">;
 362
 363 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 364                                      "Does not support ARM mode execution">;
 365
 366 //===----------------------------------------------------------------------===//
 367 // ARM ISAa.
 368 //
 369
 370 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 371                                    "Support ARM v4T instructions">;
 372
 373 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 374                                    "Support ARM v5T instructions",
 375                                    [HasV4TOps]>;
 376
 377 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 378                                    "Support ARM v5TE, v5TEj, and "
 379                                    "v5TExp instructions",
 380                                    [HasV5TOps]>;
 381
 382 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 383                                    "Support ARM v6 instructions",
 384                                    [HasV5TEOps]>;
 385
 386 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 387                                    "Support ARM v6M instructions",
 388                                    [HasV6Ops]>;
 389
 390 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 391                                          "Support ARM v8M Baseline instructions",
 392                                          [HasV6MOps]>;
 393
 394 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 395                                    "Support ARM v6k instructions",
 396                                    [HasV6Ops]>;
 397
 398 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 399                                    "Support ARM v6t2 instructions",
 400                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 401
 402 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 403                                    "Support ARM v7 instructions",
 404                                    [HasV6T2Ops, FeaturePerfMon,
 405                                     FeatureV7Clrex]>;
 406
 407 def HasV8MMainlineOps :
 408                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 409                                    "Support ARM v8M Mainline instructions",
 410                                    [HasV7Ops]>;
 411
 412 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 413                                    "Support ARM v8 instructions",
 414                                    [HasV7Ops, FeatureAcquireRelease]>;
 415
 416 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 417                                    "Support ARM v8.1a instructions",
 418                                    [HasV8Ops]>;
 419
 420 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 421                                    "Support ARM v8.2a instructions",
 422                                    [HasV8_1aOps]>;
 423
 424 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 425                                    "Support ARM v8.3a instructions",
 426                                    [HasV8_2aOps]>;
 427
 428 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 429                                    "Support ARM v8.4a instructions",
 430                                    [HasV8_3aOps, FeatureDotProd]>;
 431
 432 //===----------------------------------------------------------------------===//
 433 // ARM Processor subtarget features.
 434 //
 435
 436 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 437                                    "Cortex-A5 ARM processors", []>;
 438 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 439                                    "Cortex-A7 ARM processors", []>;
 440 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 441                                    "Cortex-A8 ARM processors", []>;
 442 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 443                                    "Cortex-A9 ARM processors", []>;
 444 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 445                                    "Cortex-A12 ARM processors", []>;
 446 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 447                                    "Cortex-A15 ARM processors", []>;
 448 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 449                                    "Cortex-A17 ARM processors", []>;
 450 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 451                                    "Cortex-A32 ARM processors", []>;
 452 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 453                                    "Cortex-A35 ARM processors", []>;
 454 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 455                                    "Cortex-A53 ARM processors", []>;
 456 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 457                                    "Cortex-A55 ARM processors", []>;
 458 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 459                                    "Cortex-A57 ARM processors", []>;
 460 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 461                                    "Cortex-A72 ARM processors", []>;
 462 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 463                                    "Cortex-A73 ARM processors", []>;
 464 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 465                                    "Cortex-A75 ARM processors", []>;
 466
 467 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 468                                    "Qualcomm Krait processors", []>;
 469 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 470                                    "Qualcomm Kryo processors", []>;
 471 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 472                                    "Swift ARM processors", []>;
 473
 474 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 475                                     "Samsung Exynos-Mx processors", []>;
 476
 477 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 478                                    "Cortex-R4 ARM processors", []>;
 479 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 480                                    "Cortex-R5 ARM processors", []>;
 481 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 482                                    "Cortex-R7 ARM processors", []>;
 483 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 484                                    "Cortex-R52 ARM processors", []>;
 485
 486 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 487                                    "Cortex-M3 ARM processors", []>;
 488
 489
 490 //===----------------------------------------------------------------------===//
 491 // ARM Helper classes.
 492 //
 493
 494 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 495   : SubtargetFeature<fname, "ARMArch", aname,
 496                      !strconcat(aname, " architecture"), features>;
 497
 498 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 499   : Processor<Name, NoItineraries, Features>;
 500
 501
 502 //===----------------------------------------------------------------------===//
 503 // ARM architectures
 504 //
 505
 506 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 507
 508 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 509
 510 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 511
 512 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 513
 514 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 515
 516 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 517
 518 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 519
 520 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 521
 522 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 523
 524 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 525                                                        FeatureDSP]>;
 526
 527 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 528                                                        FeatureDSP]>;
 529
 530 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 531
 532 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 533                                                        FeatureTrustZone]>;
 534
 535 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 536                                                        FeatureNoARM,
 537                                                        ModeThumb,
 538                                                        FeatureDB,
 539                                                        FeatureMClass,
 540                                                        FeatureStrictAlign]>;
 541
 542 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 543                                                        FeatureNoARM,
 544                                                        ModeThumb,
 545                                                        FeatureDB,
 546                                                        FeatureMClass,
 547                                                        FeatureStrictAlign]>;
 548
 549 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 550                                                        FeatureNEON,
 551                                                        FeatureDB,
 552                                                        FeatureDSP,
 553                                                        FeatureAClass]>;
 554
 555 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 556                                                        FeatureNEON,
 557                                                        FeatureDB,
 558                                                        FeatureDSP,
 559                                                        FeatureTrustZone,
 560                                                        FeatureMP,
 561                                                        FeatureVirtualization,
 562                                                        FeatureAClass]>;
 563
 564 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 565                                                        FeatureDB,
 566                                                        FeatureDSP,
 567                                                        FeatureHWDivThumb,
 568                                                        FeatureRClass]>;
 569
 570 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 571                                                        FeatureThumb2,
 572                                                        FeatureNoARM,
 573                                                        ModeThumb,
 574                                                        FeatureDB,
 575                                                        FeatureHWDivThumb,
 576                                                        FeatureMClass]>;
 577
 578 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 579                                                        FeatureThumb2,
 580                                                        FeatureNoARM,
 581                                                        ModeThumb,
 582                                                        FeatureDB,
 583                                                        FeatureHWDivThumb,
 584                                                        FeatureMClass,
 585                                                        FeatureDSP]>;
 586
 587 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 588                                                        FeatureAClass,
 589                                                        FeatureDB,
 590                                                        FeatureFPARMv8,
 591                                                        FeatureNEON,
 592                                                        FeatureDSP,
 593                                                        FeatureTrustZone,
 594                                                        FeatureMP,
 595                                                        FeatureVirtualization,
 596                                                        FeatureCrypto,
 597                                                        FeatureCRC]>;
 598
 599 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 600                                                        FeatureAClass,
 601                                                        FeatureDB,
 602                                                        FeatureFPARMv8,
 603                                                        FeatureNEON,
 604                                                        FeatureDSP,
 605                                                        FeatureTrustZone,
 606                                                        FeatureMP,
 607                                                        FeatureVirtualization,
 608                                                        FeatureCrypto,
 609                                                        FeatureCRC]>;
 610
 611 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 612                                                        FeatureAClass,
 613                                                        FeatureDB,
 614                                                        FeatureFPARMv8,
 615                                                        FeatureNEON,
 616                                                        FeatureDSP,
 617                                                        FeatureTrustZone,
 618                                                        FeatureMP,
 619                                                        FeatureVirtualization,
 620                                                        FeatureCrypto,
 621                                                        FeatureCRC,
 622                                                        FeatureRAS]>;
 623
 624 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 625                                                        FeatureAClass,
 626                                                        FeatureDB,
 627                                                        FeatureFPARMv8,
 628                                                        FeatureNEON,
 629                                                        FeatureDSP,
 630                                                        FeatureTrustZone,
 631                                                        FeatureMP,
 632                                                        FeatureVirtualization,
 633                                                        FeatureCrypto,
 634                                                        FeatureCRC,
 635                                                        FeatureRAS]>;
 636
 637 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 638                                                        FeatureAClass,
 639                                                        FeatureDB,
 640                                                        FeatureFPARMv8,
 641                                                        FeatureNEON,
 642                                                        FeatureDSP,
 643                                                        FeatureTrustZone,
 644                                                        FeatureMP,
 645                                                        FeatureVirtualization,
 646                                                        FeatureCrypto,
 647                                                        FeatureCRC,
 648                                                        FeatureRAS,
 649                                                        FeatureDotProd]>;
 650
 651 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 652                                                        FeatureRClass,
 653                                                        FeatureDB,
 654                                                        FeatureDFB,
 655                                                        FeatureDSP,
 656                                                        FeatureCRC,
 657                                                        FeatureMP,
 658                                                        FeatureVirtualization,
 659                                                        FeatureFPARMv8,
 660                                                        FeatureNEON]>;
 661
 662 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 663                                                       [HasV8MBaselineOps,
 664                                                        FeatureNoARM,
 665                                                        ModeThumb,
 666                                                        FeatureDB,
 667                                                        FeatureHWDivThumb,
 668                                                        FeatureV7Clrex,
 669                                                        Feature8MSecExt,
 670                                                        FeatureAcquireRelease,
 671                                                        FeatureMClass,
 672                                                        FeatureStrictAlign]>;
 673
 674 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 675                                                       [HasV8MMainlineOps,
 676                                                        FeatureNoARM,
 677                                                        ModeThumb,
 678                                                        FeatureDB,
 679                                                        FeatureHWDivThumb,
 680                                                        Feature8MSecExt,
 681                                                        FeatureAcquireRelease,
 682                                                        FeatureMClass]>;
 683
 684 // Aliases
 685 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 686 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 687 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 688 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 689 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 690 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 691
 692
 693 //===----------------------------------------------------------------------===//
 694 // ARM schedules.
 695 //===----------------------------------------------------------------------===//
 696 //
 697 include "ARMSchedule.td"
 698
 699 //===----------------------------------------------------------------------===//
 700 // ARM processors
 701 //
 702
 703 // Dummy CPU, used to target architectures
 704 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 705
 706 // FIXME: Several processors below are not using their own scheduler
 707 // model, but one of similar/previous processor. These should be fixed.
 708
 709 def : ProcNoItin<"arm8",                                [ARMv4]>;
 710 def : ProcNoItin<"arm810",                              [ARMv4]>;
 711 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 712 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 713 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 714 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 715
 716 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 717 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 718 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 719 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 720 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 721 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 722 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 723 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 724 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 725 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 726 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 727
 728 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 729 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 730
 731 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 732 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 733 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 734 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 735 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 736 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 737 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 738 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 739 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 740 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 741
 742 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 743 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 744                                                          FeatureVFP2,
 745                                                          FeatureHasSlowFPVMLx]>;
 746
 747 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 748 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 749 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 750 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 751
 752 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 753 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 754 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 755                                                          FeatureVFP2,
 756                                                          FeatureHasSlowFPVMLx]>;
 757
 758 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 759 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 760                                                          FeatureVFP2,
 761                                                          FeatureHasSlowFPVMLx]>;
 762
 763 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 764 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 765                                                          FeatureVFP2,
 766                                                          FeatureHasSlowFPVMLx]>;
 767
 768 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 769                                                          FeatureHasRetAddrStack,
 770                                                          FeatureTrustZone,
 771                                                          FeatureSlowFPBrcc,
 772                                                          FeatureHasSlowFPVMLx,
 773                                                          FeatureVMLxForwarding,
 774                                                          FeatureMP,
 775                                                          FeatureVFP4]>;
 776
 777 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 778                                                          FeatureHasRetAddrStack,
 779                                                          FeatureTrustZone,
 780                                                          FeatureSlowFPBrcc,
 781                                                          FeatureHasVMLxHazards,
 782                                                          FeatureHasSlowFPVMLx,
 783                                                          FeatureVMLxForwarding,
 784                                                          FeatureMP,
 785                                                          FeatureVFP4,
 786                                                          FeatureVirtualization]>;
 787
 788 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 789                                                          FeatureHasRetAddrStack,
 790                                                          FeatureNonpipelinedVFP,
 791                                                          FeatureTrustZone,
 792                                                          FeatureSlowFPBrcc,
 793                                                          FeatureHasVMLxHazards,
 794                                                          FeatureHasSlowFPVMLx,
 795                                                          FeatureVMLxForwarding]>;
 796
 797 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 798                                                          FeatureHasRetAddrStack,
 799                                                          FeatureTrustZone,
 800                                                          FeatureHasVMLxHazards,
 801                                                          FeatureVMLxForwarding,
 802                                                          FeatureFP16,
 803                                                          FeatureAvoidPartialCPSR,
 804                                                          FeatureExpandMLx,
 805                                                          FeaturePreferVMOVSR,
 806                                                          FeatureMuxedUnits,
 807                                                          FeatureNEONForFPMovs,
 808                                                          FeatureCheckVLDnAlign,
 809                                                          FeatureMP]>;
 810
 811 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 812                                                          FeatureHasRetAddrStack,
 813                                                          FeatureTrustZone,
 814                                                          FeatureVMLxForwarding,
 815                                                          FeatureVFP4,
 816                                                          FeatureAvoidPartialCPSR,
 817                                                          FeatureVirtualization,
 818                                                          FeatureMP]>;
 819
 820 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 821                                                          FeatureDontWidenVMOVS,
 822                                                          FeatureHasRetAddrStack,
 823                                                          FeatureMuxedUnits,
 824                                                          FeatureTrustZone,
 825                                                          FeatureVFP4,
 826                                                          FeatureMP,
 827                                                          FeatureCheckVLDnAlign,
 828                                                          FeatureAvoidPartialCPSR,
 829                                                          FeatureVirtualization]>;
 830
 831 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 832                                                          FeatureHasRetAddrStack,
 833                                                          FeatureTrustZone,
 834                                                          FeatureMP,
 835                                                          FeatureVMLxForwarding,
 836                                                          FeatureVFP4,
 837                                                          FeatureAvoidPartialCPSR,
 838                                                          FeatureVirtualization]>;
 839
 840 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 841 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 842                                                          FeatureHasRetAddrStack,
 843                                                          FeatureMuxedUnits,
 844                                                          FeatureCheckVLDnAlign,
 845                                                          FeatureVMLxForwarding,
 846                                                          FeatureFP16,
 847                                                          FeatureAvoidPartialCPSR,
 848                                                          FeatureVFP4,
 849                                                          FeatureHWDivThumb,
 850                                                          FeatureHWDivARM]>;
 851
 852 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 853                                                          FeatureHasRetAddrStack,
 854                                                          FeatureNEONForFP,
 855                                                          FeatureVFP4,
 856                                                          FeatureMP,
 857                                                          FeatureHWDivThumb,
 858                                                          FeatureHWDivARM,
 859                                                          FeatureAvoidPartialCPSR,
 860                                                          FeatureAvoidMOVsShOp,
 861                                                          FeatureHasSlowFPVMLx,
 862                                                          FeatureHasVMLxHazards,
 863                                                          FeatureProfUnpredicate,
 864                                                          FeaturePrefISHSTBarrier,
 865                                                          FeatureSlowOddRegister,
 866                                                          FeatureSlowLoadDSubreg,
 867                                                          FeatureSlowVGETLNi32,
 868                                                          FeatureSlowVDUP32,
 869                                                          FeatureUseMISched,
 870                                                          FeatureNoPostRASched]>;
 871
 872 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 873                                                          FeatureHasRetAddrStack,
 874                                                          FeatureAvoidPartialCPSR]>;
 875
 876 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 877                                                          FeatureHasRetAddrStack,
 878                                                          FeatureSlowFPBrcc,
 879                                                          FeatureHasSlowFPVMLx,
 880                                                          FeatureVFP3,
 881                                                          FeatureD16,
 882                                                          FeatureAvoidPartialCPSR]>;
 883
 884 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 885                                                          FeatureHasRetAddrStack,
 886                                                          FeatureVFP3,
 887                                                          FeatureD16,
 888                                                          FeatureSlowFPBrcc,
 889                                                          FeatureHWDivARM,
 890                                                          FeatureHasSlowFPVMLx,
 891                                                          FeatureAvoidPartialCPSR]>;
 892
 893 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 894                                                          FeatureHasRetAddrStack,
 895                                                          FeatureVFP3,
 896                                                          FeatureD16,
 897                                                          FeatureFP16,
 898                                                          FeatureMP,
 899                                                          FeatureSlowFPBrcc,
 900                                                          FeatureHWDivARM,
 901                                                          FeatureHasSlowFPVMLx,
 902                                                          FeatureAvoidPartialCPSR]>;
 903
 904 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 905                                                          FeatureHasRetAddrStack,
 906                                                          FeatureVFP3,
 907                                                          FeatureD16,
 908                                                          FeatureFP16,
 909                                                          FeatureMP,
 910                                                          FeatureSlowFPBrcc,
 911                                                          FeatureHWDivARM,
 912                                                          FeatureHasSlowFPVMLx,
 913                                                          FeatureAvoidPartialCPSR]>;
 914
 915 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
 916                                                          ProcM3,
 917                                                          FeatureHasNoBranchPredictor]>;
 918
 919 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
 920                                                          ProcM3,
 921                                                          FeatureHasNoBranchPredictor]>;
 922
 923 def : ProcessorModel<"cortex-m4", CortexM3Model,        [ARMv7em,
 924                                                          FeatureVFP4,
 925                                                          FeatureVFPOnlySP,
 926                                                          FeatureD16,
 927                                                          FeatureHasNoBranchPredictor]>;
 928
 929 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 930                                                          FeatureFPARMv8,
 931                                                          FeatureD16]>;
 932
 933 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
 934                                                          FeatureNoMovt]>;
 935
 936 def : ProcessorModel<"cortex-m33", CortexM3Model,       [ARMv8mMainline,
 937                                                          FeatureDSP,
 938                                                          FeatureFPARMv8,
 939                                                          FeatureD16,
 940                                                          FeatureVFPOnlySP,
 941                                                          FeatureHasNoBranchPredictor]>;
 942
 943 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
 944                                                          FeatureHWDivThumb,
 945                                                          FeatureHWDivARM,
 946                                                          FeatureCrypto,
 947                                                          FeatureCRC]>;
 948
 949 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
 950                                                          FeatureHWDivThumb,
 951                                                          FeatureHWDivARM,
 952                                                          FeatureCrypto,
 953                                                          FeatureCRC]>;
 954
 955 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 956                                                          FeatureHWDivThumb,
 957                                                          FeatureHWDivARM,
 958                                                          FeatureCrypto,
 959                                                          FeatureCRC,
 960                                                          FeatureFPAO]>;
 961
 962 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
 963                                                          FeatureHWDivThumb,
 964                                                          FeatureHWDivARM,
 965                                                          FeatureDotProd]>;
 966
 967 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
 968                                                          FeatureHWDivThumb,
 969                                                          FeatureHWDivARM,
 970                                                          FeatureCrypto,
 971                                                          FeatureCRC,
 972                                                          FeatureFPAO,
 973                                                          FeatureAvoidPartialCPSR,
 974                                                          FeatureCheapPredicableCPSR]>;
 975
 976 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 977                                                          FeatureHWDivThumb,
 978                                                          FeatureHWDivARM,
 979                                                          FeatureCrypto,
 980                                                          FeatureCRC]>;
 981
 982 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
 983                                                          FeatureHWDivThumb,
 984                                                          FeatureHWDivARM,
 985                                                          FeatureCrypto,
 986                                                          FeatureCRC]>;
 987
 988 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
 989                                                          FeatureHWDivThumb,
 990                                                          FeatureHWDivARM,
 991                                                          FeatureDotProd]>;
 992
 993 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 994                                                          FeatureHasRetAddrStack,
 995                                                          FeatureNEONForFP,
 996                                                          FeatureVFP4,
 997                                                          FeatureMP,
 998                                                          FeatureHWDivThumb,
 999                                                          FeatureHWDivARM,
1000                                                          FeatureAvoidPartialCPSR,
1001                                                          FeatureAvoidMOVsShOp,
1002                                                          FeatureHasSlowFPVMLx,
1003                                                          FeatureCrypto,
1004                                                          FeatureUseMISched,
1005                                                          FeatureZCZeroing,
1006                                                          FeatureNoPostRASched]>;
1007
1008 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
1009                                                          FeatureHWDivThumb,
1010                                                          FeatureHWDivARM,
1011                                                          FeatureCrypto,
1012                                                          FeatureCRC]>;
1013
1014 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
1015                                                          FeatureHWDivThumb,
1016                                                          FeatureHWDivARM,
1017                                                          FeatureCrypto,
1018                                                          FeatureCRC]>;
1019
1020 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
1021                                                          FeatureHWDivThumb,
1022                                                          FeatureHWDivARM,
1023                                                          FeatureCrypto,
1024                                                          FeatureCRC]>;
1025
1026 def : ProcNoItin<"exynos-m4",                           [ARMv8a, ProcExynosM1,
1027                                                          FeatureHWDivThumb,
1028                                                          FeatureHWDivARM,
1029                                                          FeatureCrypto,
1030                                                          FeatureCRC]>;
1031
1032 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1033                                                          FeatureHWDivThumb,
1034                                                          FeatureHWDivARM,
1035                                                          FeatureCrypto,
1036                                                          FeatureCRC]>;
1037
1038 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1039                                                          FeatureUseMISched,
1040                                                          FeatureFPAO,
1041                                                          FeatureUseAA]>;
1042
1043 //===----------------------------------------------------------------------===//
1044 // Register File Description
1045 //===----------------------------------------------------------------------===//
1046
1047 include "ARMRegisterInfo.td"
1048 include "ARMRegisterBanks.td"
1049 include "ARMCallingConv.td"
1050
1051 //===----------------------------------------------------------------------===//
1052 // Instruction Descriptions
1053 //===----------------------------------------------------------------------===//
1054
1055 include "ARMInstrInfo.td"
1056 def ARMInstrInfo : InstrInfo;
1057
1058 //===----------------------------------------------------------------------===//
1059 // Declare the target which we are implementing
1060 //===----------------------------------------------------------------------===//
1061
1062 def ARMAsmWriter : AsmWriter {
1063   string AsmWriterClassName  = "InstPrinter";
1064   int PassSubtarget = 1;
1065   int Variant = 0;
1066   bit isMCAsmWriter = 1;
1067 }
1068
1069 def ARMAsmParser : AsmParser {
1070   bit ReportMultipleNearMisses = 1;
1071 }
1072
1073 def ARMAsmParserVariant : AsmParserVariant {
1074   int Variant = 0;
1075   string Name = "ARM";
1076   string BreakCharacters = ".";
1077 }
1078
1079 def ARM : Target {
1080   // Pull in Instruction Info.
1081   let InstructionSet = ARMInstrInfo;
1082   let AssemblyWriters = [ARMAsmWriter];
1083   let AssemblyParsers = [ARMAsmParser];
1084   let AssemblyParserVariants = [ARMAsmParserVariant];
1085   let AllowRegisterRenaming = 1;
1086 }