lib/Target/ARM/ARMRegisterBankInfo.h

   1 //===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 /// \file
  10 /// This file declares the targeting of the RegisterBankInfo class for ARM.
  11 /// \todo This should be generated by TableGen.
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
  15 #define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
  16
  17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  18
  19 #define GET_REGBANK_DECLARATIONS
  20 #include "ARMGenRegisterBank.inc"
  21
  22 namespace llvm {
  23
  24 class TargetRegisterInfo;
  25
  26 class ARMGenRegisterBankInfo : public RegisterBankInfo {
  27 #define GET_TARGET_REGBANK_CLASS
  28 #include "ARMGenRegisterBank.inc"
  29 };
  30
  31 /// This class provides the information for the target register banks.
  32 class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
  33 public:
  34   ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
  35
  36   const RegisterBank &
  37   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
  38
  39   const InstructionMapping &
  40   getInstrMapping(const MachineInstr &MI) const override;
  41 };
  42 } // End llvm namespace.
  43 #endif