lib/Target/Mips/MipsInstrInfo.cpp

   1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MipsInstrInfo.h"
  15 #include "MCTargetDesc/MipsBaseInfo.h"
  16 #include "MCTargetDesc/MipsMCTargetDesc.h"
  17 #include "MipsSubtarget.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/CodeGen/MachineBasicBlock.h"
  20 #include "llvm/CodeGen/MachineFrameInfo.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineInstr.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/CodeGen/MachineOperand.h"
  25 #include "llvm/CodeGen/TargetOpcodes.h"
  26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  27 #include "llvm/IR/DebugLoc.h"
  28 #include "llvm/MC/MCInstrDesc.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include <cassert>
  31
  32 using namespace llvm;
  33
  34 #define GET_INSTRINFO_CTOR_DTOR
  35 #include "MipsGenInstrInfo.inc"
  36
  37 // Pin the vtable to this file.
  38 void MipsInstrInfo::anchor() {}
  39
  40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
  41     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
  42       Subtarget(STI), UncondBrOpc(UncondBr) {}
  43
  44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
  45   if (STI.inMips16Mode())
  46     return createMips16InstrInfo(STI);
  47
  48   return createMipsSEInstrInfo(STI);
  49 }
  50
  51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
  52   return op.isImm() && op.getImm() == 0;
  53 }
  54
  55 /// insertNoop - If data hazard condition is found insert the target nop
  56 /// instruction.
  57 // FIXME: This appears to be dead code.
  58 void MipsInstrInfo::
  59 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
  60 {
  61   DebugLoc DL;
  62   BuildMI(MBB, MI, DL, get(Mips::NOP));
  63 }
  64
  65 MachineMemOperand *
  66 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
  67                              MachineMemOperand::Flags Flags) const {
  68   MachineFunction &MF = *MBB.getParent();
  69   MachineFrameInfo &MFI = MF.getFrameInfo();
  70   unsigned Align = MFI.getObjectAlignment(FI);
  71
  72   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
  73                                  Flags, MFI.getObjectSize(FI), Align);
  74 }
  75
  76 //===----------------------------------------------------------------------===//
  77 // Branch Analysis
  78 //===----------------------------------------------------------------------===//
  79
  80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
  81                                   MachineBasicBlock *&BB,
  82                                   SmallVectorImpl<MachineOperand> &Cond) const {
  83   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
  84   int NumOp = Inst->getNumExplicitOperands();
  85
  86   // for both int and fp branches, the last explicit operand is the
  87   // MBB.
  88   BB = Inst->getOperand(NumOp-1).getMBB();
  89   Cond.push_back(MachineOperand::CreateImm(Opc));
  90
  91   for (int i = 0; i < NumOp-1; i++)
  92     Cond.push_back(Inst->getOperand(i));
  93 }
  94
  95 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
  96                                   MachineBasicBlock *&TBB,
  97                                   MachineBasicBlock *&FBB,
  98                                   SmallVectorImpl<MachineOperand> &Cond,
  99                                   bool AllowModify) const {
 100   SmallVector<MachineInstr*, 2> BranchInstrs;
 101   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
 102
 103   return (BT == BT_None) || (BT == BT_Indirect);
 104 }
 105
 106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 107                                 const DebugLoc &DL,
 108                                 ArrayRef<MachineOperand> Cond) const {
 109   unsigned Opc = Cond[0].getImm();
 110   const MCInstrDesc &MCID = get(Opc);
 111   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
 112
 113   for (unsigned i = 1; i < Cond.size(); ++i) {
 114     assert((Cond[i].isImm() || Cond[i].isReg()) &&
 115            "Cannot copy operand for conditional branch!");
 116     MIB.add(Cond[i]);
 117   }
 118   MIB.addMBB(TBB);
 119 }
 120
 121 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
 122                                      MachineBasicBlock *TBB,
 123                                      MachineBasicBlock *FBB,
 124                                      ArrayRef<MachineOperand> Cond,
 125                                      const DebugLoc &DL,
 126                                      int *BytesAdded) const {
 127   // Shouldn't be a fall through.
 128   assert(TBB && "insertBranch must not be told to insert a fallthrough");
 129   assert(!BytesAdded && "code size not handled");
 130
 131   // # of condition operands:
 132   //  Unconditional branches: 0
 133   //  Floating point branches: 1 (opc)
 134   //  Int BranchZero: 2 (opc, reg)
 135   //  Int Branch: 3 (opc, reg0, reg1)
 136   assert((Cond.size() <= 3) &&
 137          "# of Mips branch conditions must be <= 3!");
 138
 139   // Two-way Conditional branch.
 140   if (FBB) {
 141     BuildCondBr(MBB, TBB, DL, Cond);
 142     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
 143     return 2;
 144   }
 145
 146   // One way branch.
 147   // Unconditional branch.
 148   if (Cond.empty())
 149     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
 150   else // Conditional branch.
 151     BuildCondBr(MBB, TBB, DL, Cond);
 152   return 1;
 153 }
 154
 155 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
 156                                      int *BytesRemoved) const {
 157   assert(!BytesRemoved && "code size not handled");
 158
 159   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
 160   unsigned removed = 0;
 161
 162   // Up to 2 branches are removed.
 163   // Note that indirect branches are not removed.
 164   while (I != REnd && removed < 2) {
 165     // Skip past debug instructions.
 166     if (I->isDebugInstr()) {
 167       ++I;
 168       continue;
 169     }
 170     if (!getAnalyzableBrOpc(I->getOpcode()))
 171       break;
 172     // Remove the branch.
 173     I->eraseFromParent();
 174     I = MBB.rbegin();
 175     ++removed;
 176   }
 177
 178   return removed;
 179 }
 180
 181 /// reverseBranchCondition - Return the inverse opcode of the
 182 /// specified Branch instruction.
 183 bool MipsInstrInfo::reverseBranchCondition(
 184     SmallVectorImpl<MachineOperand> &Cond) const {
 185   assert( (Cond.size() && Cond.size() <= 3) &&
 186           "Invalid Mips branch condition!");
 187   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
 188   return false;
 189 }
 190
 191 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
 192     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
 193     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
 194     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
 195   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
 196
 197   // Skip all the debug instructions.
 198   while (I != REnd && I->isDebugInstr())
 199     ++I;
 200
 201   if (I == REnd || !isUnpredicatedTerminator(*I)) {
 202     // This block ends with no branches (it just falls through to its succ).
 203     // Leave TBB/FBB null.
 204     TBB = FBB = nullptr;
 205     return BT_NoBranch;
 206   }
 207
 208   MachineInstr *LastInst = &*I;
 209   unsigned LastOpc = LastInst->getOpcode();
 210   BranchInstrs.push_back(LastInst);
 211
 212   // Not an analyzable branch (e.g., indirect jump).
 213   if (!getAnalyzableBrOpc(LastOpc))
 214     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
 215
 216   // Get the second to last instruction in the block.
 217   unsigned SecondLastOpc = 0;
 218   MachineInstr *SecondLastInst = nullptr;
 219
 220   // Skip past any debug instruction to see if the second last actual
 221   // is a branch.
 222   ++I;
 223   while (I != REnd && I->isDebugInstr())
 224     ++I;
 225
 226   if (I != REnd) {
 227     SecondLastInst = &*I;
 228     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
 229
 230     // Not an analyzable branch (must be an indirect jump).
 231     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
 232       return BT_None;
 233   }
 234
 235   // If there is only one terminator instruction, process it.
 236   if (!SecondLastOpc) {
 237     // Unconditional branch.
 238     if (LastInst->isUnconditionalBranch()) {
 239       TBB = LastInst->getOperand(0).getMBB();
 240       return BT_Uncond;
 241     }
 242
 243     // Conditional branch
 244     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
 245     return BT_Cond;
 246   }
 247
 248   // If we reached here, there are two branches.
 249   // If there are three terminators, we don't know what sort of block this is.
 250   if (++I != REnd && isUnpredicatedTerminator(*I))
 251     return BT_None;
 252
 253   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
 254
 255   // If second to last instruction is an unconditional branch,
 256   // analyze it and remove the last instruction.
 257   if (SecondLastInst->isUnconditionalBranch()) {
 258     // Return if the last instruction cannot be removed.
 259     if (!AllowModify)
 260       return BT_None;
 261
 262     TBB = SecondLastInst->getOperand(0).getMBB();
 263     LastInst->eraseFromParent();
 264     BranchInstrs.pop_back();
 265     return BT_Uncond;
 266   }
 267
 268   // Conditional branch followed by an unconditional branch.
 269   // The last one must be unconditional.
 270   if (!LastInst->isUnconditionalBranch())
 271     return BT_None;
 272
 273   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
 274   FBB = LastInst->getOperand(0).getMBB();
 275
 276   return BT_CondUncond;
 277 }
 278
 279 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
 280   switch (BranchOpc) {
 281   case Mips::B:
 282   case Mips::BAL:
 283   case Mips::BC1F:
 284   case Mips::BC1FL:
 285   case Mips::BC1T:
 286   case Mips::BC1TL:
 287   case Mips::BEQ:     case Mips::BEQ64:
 288   case Mips::BEQL:
 289   case Mips::BGEZ:    case Mips::BGEZ64:
 290   case Mips::BGEZL:
 291   case Mips::BGEZAL:
 292   case Mips::BGEZALL:
 293   case Mips::BGTZ:    case Mips::BGTZ64:
 294   case Mips::BGTZL:
 295   case Mips::BLEZ:    case Mips::BLEZ64:
 296   case Mips::BLEZL:
 297   case Mips::BLTZ:    case Mips::BLTZ64:
 298   case Mips::BLTZL:
 299   case Mips::BLTZAL:
 300   case Mips::BLTZALL:
 301   case Mips::BNE:     case Mips::BNE64:
 302   case Mips::BNEL:
 303     return isInt<18>(BrOffset);
 304
 305   // microMIPSr3 branches
 306   case Mips::B_MM:
 307   case Mips::BC1F_MM:
 308   case Mips::BC1T_MM:
 309   case Mips::BEQ_MM:
 310   case Mips::BGEZ_MM:
 311   case Mips::BGEZAL_MM:
 312   case Mips::BGTZ_MM:
 313   case Mips::BLEZ_MM:
 314   case Mips::BLTZ_MM:
 315   case Mips::BLTZAL_MM:
 316   case Mips::BNE_MM:
 317   case Mips::BEQZC_MM:
 318   case Mips::BNEZC_MM:
 319     return isInt<17>(BrOffset);
 320
 321   // microMIPSR3 short branches.
 322   case Mips::B16_MM:
 323     return isInt<11>(BrOffset);
 324
 325   case Mips::BEQZ16_MM:
 326   case Mips::BNEZ16_MM:
 327     return isInt<8>(BrOffset);
 328
 329   // MIPSR6 branches.
 330   case Mips::BALC:
 331   case Mips::BC:
 332     return isInt<28>(BrOffset);
 333
 334   case Mips::BC1EQZ:
 335   case Mips::BC1NEZ:
 336   case Mips::BC2EQZ:
 337   case Mips::BC2NEZ:
 338   case Mips::BEQC:   case Mips::BEQC64:
 339   case Mips::BNEC:   case Mips::BNEC64:
 340   case Mips::BGEC:   case Mips::BGEC64:
 341   case Mips::BGEUC:  case Mips::BGEUC64:
 342   case Mips::BGEZC:  case Mips::BGEZC64:
 343   case Mips::BGTZC:  case Mips::BGTZC64:
 344   case Mips::BLEZC:  case Mips::BLEZC64:
 345   case Mips::BLTC:   case Mips::BLTC64:
 346   case Mips::BLTUC:  case Mips::BLTUC64:
 347   case Mips::BLTZC:  case Mips::BLTZC64:
 348   case Mips::BNVC:
 349   case Mips::BOVC:
 350   case Mips::BGEZALC:
 351   case Mips::BEQZALC:
 352   case Mips::BGTZALC:
 353   case Mips::BLEZALC:
 354   case Mips::BLTZALC:
 355   case Mips::BNEZALC:
 356     return isInt<18>(BrOffset);
 357
 358   case Mips::BEQZC:  case Mips::BEQZC64:
 359   case Mips::BNEZC:  case Mips::BNEZC64:
 360     return isInt<23>(BrOffset);
 361
 362   // microMIPSR6 branches
 363   case Mips::BC16_MMR6:
 364     return isInt<11>(BrOffset);
 365
 366   case Mips::BEQZC16_MMR6:
 367   case Mips::BNEZC16_MMR6:
 368     return isInt<8>(BrOffset);
 369
 370   case Mips::BALC_MMR6:
 371   case Mips::BC_MMR6:
 372     return isInt<27>(BrOffset);
 373
 374   case Mips::BC1EQZC_MMR6:
 375   case Mips::BC1NEZC_MMR6:
 376   case Mips::BC2EQZC_MMR6:
 377   case Mips::BC2NEZC_MMR6:
 378   case Mips::BGEZALC_MMR6:
 379   case Mips::BEQZALC_MMR6:
 380   case Mips::BGTZALC_MMR6:
 381   case Mips::BLEZALC_MMR6:
 382   case Mips::BLTZALC_MMR6:
 383   case Mips::BNEZALC_MMR6:
 384   case Mips::BNVC_MMR6:
 385   case Mips::BOVC_MMR6:
 386     return isInt<17>(BrOffset);
 387
 388   case Mips::BEQC_MMR6:
 389   case Mips::BNEC_MMR6:
 390   case Mips::BGEC_MMR6:
 391   case Mips::BGEUC_MMR6:
 392   case Mips::BGEZC_MMR6:
 393   case Mips::BGTZC_MMR6:
 394   case Mips::BLEZC_MMR6:
 395   case Mips::BLTC_MMR6:
 396   case Mips::BLTUC_MMR6:
 397   case Mips::BLTZC_MMR6:
 398     return isInt<18>(BrOffset);
 399
 400   case Mips::BEQZC_MMR6:
 401   case Mips::BNEZC_MMR6:
 402     return isInt<23>(BrOffset);
 403
 404   // DSP branches.
 405   case Mips::BPOSGE32:
 406     return isInt<18>(BrOffset);
 407   case Mips::BPOSGE32_MM:
 408   case Mips::BPOSGE32C_MMR3:
 409     return isInt<17>(BrOffset);
 410
 411   // cnMIPS branches.
 412   case Mips::BBIT0:
 413   case Mips::BBIT032:
 414   case Mips::BBIT1:
 415   case Mips::BBIT132:
 416     return isInt<18>(BrOffset);
 417
 418   // MSA branches.
 419   case Mips::BZ_B:
 420   case Mips::BZ_H:
 421   case Mips::BZ_W:
 422   case Mips::BZ_D:
 423   case Mips::BZ_V:
 424   case Mips::BNZ_B:
 425   case Mips::BNZ_H:
 426   case Mips::BNZ_W:
 427   case Mips::BNZ_D:
 428   case Mips::BNZ_V:
 429     return isInt<18>(BrOffset);
 430   }
 431
 432   llvm_unreachable("Unknown branch instruction!");
 433 }
 434
 435
 436 /// Return the corresponding compact (no delay slot) form of a branch.
 437 unsigned MipsInstrInfo::getEquivalentCompactForm(
 438     const MachineBasicBlock::iterator I) const {
 439   unsigned Opcode = I->getOpcode();
 440   bool canUseShortMicroMipsCTI = false;
 441
 442   if (Subtarget.inMicroMipsMode()) {
 443     switch (Opcode) {
 444     case Mips::BNE:
 445     case Mips::BNE_MM:
 446     case Mips::BEQ:
 447     case Mips::BEQ_MM:
 448     // microMIPS has NE,EQ branches that do not have delay slots provided one
 449     // of the operands is zero.
 450       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
 451         canUseShortMicroMipsCTI = true;
 452       break;
 453     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
 454     // expanded to JR_MM, so they can be replaced with JRC16_MM.
 455     case Mips::JR:
 456     case Mips::PseudoReturn:
 457     case Mips::PseudoIndirectBranch:
 458       canUseShortMicroMipsCTI = true;
 459       break;
 460     }
 461   }
 462
 463   // MIPSR6 forbids both operands being the zero register.
 464   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
 465       (I->getOperand(0).isReg() &&
 466        (I->getOperand(0).getReg() == Mips::ZERO ||
 467         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
 468       (I->getOperand(1).isReg() &&
 469        (I->getOperand(1).getReg() == Mips::ZERO ||
 470         I->getOperand(1).getReg() == Mips::ZERO_64)))
 471     return 0;
 472
 473   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
 474     switch (Opcode) {
 475     case Mips::B:
 476       return Mips::BC;
 477     case Mips::BAL:
 478       return Mips::BALC;
 479     case Mips::BEQ:
 480     case Mips::BEQ_MM:
 481       if (canUseShortMicroMipsCTI)
 482         return Mips::BEQZC_MM;
 483       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 484         return 0;
 485       return Mips::BEQC;
 486     case Mips::BNE:
 487     case Mips::BNE_MM:
 488       if (canUseShortMicroMipsCTI)
 489         return Mips::BNEZC_MM;
 490       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 491         return 0;
 492       return Mips::BNEC;
 493     case Mips::BGE:
 494       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 495         return 0;
 496       return Mips::BGEC;
 497     case Mips::BGEU:
 498       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 499         return 0;
 500       return Mips::BGEUC;
 501     case Mips::BGEZ:
 502       return Mips::BGEZC;
 503     case Mips::BGTZ:
 504       return Mips::BGTZC;
 505     case Mips::BLEZ:
 506       return Mips::BLEZC;
 507     case Mips::BLT:
 508       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 509         return 0;
 510       return Mips::BLTC;
 511     case Mips::BLTU:
 512       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 513         return 0;
 514       return Mips::BLTUC;
 515     case Mips::BLTZ:
 516       return Mips::BLTZC;
 517     case Mips::BEQ64:
 518       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 519         return 0;
 520       return Mips::BEQC64;
 521     case Mips::BNE64:
 522       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
 523         return 0;
 524       return Mips::BNEC64;
 525     case Mips::BGTZ64:
 526       return Mips::BGTZC64;
 527     case Mips::BGEZ64:
 528       return Mips::BGEZC64;
 529     case Mips::BLTZ64:
 530       return Mips::BLTZC64;
 531     case Mips::BLEZ64:
 532       return Mips::BLEZC64;
 533     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
 534     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
 535     case Mips::JR:
 536     case Mips::PseudoIndirectBranchR6:
 537     case Mips::PseudoReturn:
 538     case Mips::TAILCALLR6REG:
 539       if (canUseShortMicroMipsCTI)
 540         return Mips::JRC16_MM;
 541       return Mips::JIC;
 542     case Mips::JALRPseudo:
 543       return Mips::JIALC;
 544     case Mips::JR64:
 545     case Mips::PseudoIndirectBranch64R6:
 546     case Mips::PseudoReturn64:
 547     case Mips::TAILCALL64R6REG:
 548       return Mips::JIC64;
 549     case Mips::JALR64Pseudo:
 550       return Mips::JIALC64;
 551     default:
 552       return 0;
 553     }
 554   }
 555
 556   return 0;
 557 }
 558
 559 /// Predicate for distingushing between control transfer instructions and all
 560 /// other instructions for handling forbidden slots. Consider inline assembly
 561 /// as unsafe as well.
 562 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
 563   if (MI.isInlineAsm())
 564     return false;
 565
 566   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
 567 }
 568
 569 /// Predicate for distingushing instructions that have forbidden slots.
 570 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
 571   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
 572 }
 573
 574 /// Return the number of bytes of code the specified instruction may be.
 575 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
 576   switch (MI.getOpcode()) {
 577   default:
 578     return MI.getDesc().getSize();
 579   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
 580     const MachineFunction *MF = MI.getParent()->getParent();
 581     const char *AsmStr = MI.getOperand(0).getSymbolName();
 582     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
 583   }
 584   case Mips::CONSTPOOL_ENTRY:
 585     // If this machine instr is a constant pool entry, its size is recorded as
 586     // operand #2.
 587     return MI.getOperand(2).getImm();
 588   }
 589 }
 590
 591 MachineInstrBuilder
 592 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
 593                                   MachineBasicBlock::iterator I) const {
 594   MachineInstrBuilder MIB;
 595
 596   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
 597   // Pick the zero form of the branch for readable assembly and for greater
 598   // branch distance in non-microMIPS mode.
 599   // Additional MIPSR6 does not permit the use of register $zero for compact
 600   // branches.
 601   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
 602   // Mips::ZERO, which is incorrect. This test should be updated to use
 603   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
 604   // are fixed.
 605   int ZeroOperandPosition = -1;
 606   bool BranchWithZeroOperand = false;
 607   if (I->isBranch() && !I->isPseudo()) {
 608     auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
 609     ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
 610     BranchWithZeroOperand = ZeroOperandPosition != -1;
 611   }
 612
 613   if (BranchWithZeroOperand) {
 614     switch (NewOpc) {
 615     case Mips::BEQC:
 616       NewOpc = Mips::BEQZC;
 617       break;
 618     case Mips::BNEC:
 619       NewOpc = Mips::BNEZC;
 620       break;
 621     case Mips::BGEC:
 622       NewOpc = Mips::BGEZC;
 623       break;
 624     case Mips::BLTC:
 625       NewOpc = Mips::BLTZC;
 626       break;
 627     case Mips::BEQC64:
 628       NewOpc = Mips::BEQZC64;
 629       break;
 630     case Mips::BNEC64:
 631       NewOpc = Mips::BNEZC64;
 632       break;
 633     }
 634   }
 635
 636   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
 637
 638   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
 639   // immediate 0 as an operand and requires the removal of it's implicit-def %ra
 640   // implicit operand as copying the implicit operations of the instructio we're
 641   // looking at will give us the correct flags.
 642   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
 643       NewOpc == Mips::JIALC64) {
 644
 645     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
 646       MIB->RemoveOperand(0);
 647
 648     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
 649       MIB.add(I->getOperand(J));
 650     }
 651
 652     MIB.addImm(0);
 653
 654   } else {
 655     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
 656       if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
 657         continue;
 658
 659       MIB.add(I->getOperand(J));
 660     }
 661   }
 662
 663   MIB.copyImplicitOps(*I);
 664
 665   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
 666   return MIB;
 667 }
 668
 669 bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
 670                                           unsigned &SrcOpIdx2) const {
 671   assert(!MI.isBundle() &&
 672          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
 673
 674   const MCInstrDesc &MCID = MI.getDesc();
 675   if (!MCID.isCommutable())
 676     return false;
 677
 678   switch (MI.getOpcode()) {
 679   case Mips::DPADD_U_H:
 680   case Mips::DPADD_U_W:
 681   case Mips::DPADD_U_D:
 682   case Mips::DPADD_S_H:
 683   case Mips::DPADD_S_W:
 684   case Mips::DPADD_S_D:
 685     // The first operand is both input and output, so it should not commute
 686     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
 687       return false;
 688
 689     if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
 690       return false;
 691     return true;
 692   }
 693   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
 694 }
 695
 696 // ins, ext, dext*, dins have the following constraints:
 697 // X <= pos      <  Y
 698 // X <  size     <= Y
 699 // X <  pos+size <= Y
 700 //
 701 // dinsm and dinsu have the following constraints:
 702 // X <= pos      <  Y
 703 // X <= size     <= Y
 704 // X <  pos+size <= Y
 705 //
 706 // The callee of verifyInsExtInstruction however gives the bounds of
 707 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
 708 // function doesn't have to vary it's behaviour based on the instruction
 709 // being checked.
 710 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
 711                                     const int64_t PosLow, const int64_t PosHigh,
 712                                     const int64_t SizeLow,
 713                                     const int64_t SizeHigh,
 714                                     const int64_t BothLow,
 715                                     const int64_t BothHigh) {
 716   MachineOperand MOPos = MI.getOperand(2);
 717   if (!MOPos.isImm()) {
 718     ErrInfo = "Position is not an immediate!";
 719     return false;
 720   }
 721   int64_t Pos = MOPos.getImm();
 722   if (!((PosLow <= Pos) && (Pos < PosHigh))) {
 723     ErrInfo = "Position operand is out of range!";
 724     return false;
 725   }
 726
 727   MachineOperand MOSize = MI.getOperand(3);
 728   if (!MOSize.isImm()) {
 729     ErrInfo = "Size operand is not an immediate!";
 730     return false;
 731   }
 732   int64_t Size = MOSize.getImm();
 733   if (!((SizeLow < Size) && (Size <= SizeHigh))) {
 734     ErrInfo = "Size operand is out of range!";
 735     return false;
 736   }
 737
 738   if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
 739     ErrInfo = "Position + Size is out of range!";
 740     return false;
 741   }
 742
 743   return true;
 744 }
 745
 746 //  Perform target specific instruction verification.
 747 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
 748                                       StringRef &ErrInfo) const {
 749   // Verify that ins and ext instructions are well formed.
 750   switch (MI.getOpcode()) {
 751     case Mips::EXT:
 752     case Mips::EXT_MM:
 753     case Mips::INS:
 754     case Mips::INS_MM:
 755     case Mips::DINS:
 756       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
 757     case Mips::DINSM:
 758       // The ISA spec has a subtle difference between dinsm and dextm
 759       // in that it says:
 760       // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
 761       // To make the bounds checks similar, the range 1 < size <= 64 is checked
 762       // for 'dinsm'.
 763       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
 764     case Mips::DINSU:
 765       // The ISA spec has a subtle difference between dinsu and dextu in that
 766       // the size range of dinsu is specified as 1 <= size <= 32 whereas size
 767       // for dextu is 0 < size <= 32. The range checked for dinsu here is
 768       // 0 < size <= 32, which is equivalent and similar to dextu.
 769       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
 770     case Mips::DEXT:
 771       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
 772     case Mips::DEXTM:
 773       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
 774     case Mips::DEXTU:
 775       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
 776     case Mips::TAILCALLREG:
 777     case Mips::PseudoIndirectBranch:
 778     case Mips::JR:
 779     case Mips::JR64:
 780     case Mips::JALR:
 781     case Mips::JALR64:
 782     case Mips::JALRPseudo:
 783       if (!Subtarget.useIndirectJumpsHazard())
 784         return true;
 785
 786       ErrInfo = "invalid instruction when using jump guards!";
 787       return false;
 788     default:
 789       return true;
 790   }
 791
 792   return true;
 793 }
 794
 795 std::pair<unsigned, unsigned>
 796 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
 797   return std::make_pair(TF, 0u);
 798 }
 799
 800 ArrayRef<std::pair<unsigned, const char*>>
 801 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
 802  using namespace MipsII;
 803
 804  static const std::pair<unsigned, const char*> Flags[] = {
 805     {MO_GOT,          "mips-got"},
 806     {MO_GOT_CALL,     "mips-got-call"},
 807     {MO_GPREL,        "mips-gprel"},
 808     {MO_ABS_HI,       "mips-abs-hi"},
 809     {MO_ABS_LO,       "mips-abs-lo"},
 810     {MO_TLSGD,        "mips-tlsgd"},
 811     {MO_TLSLDM,       "mips-tlsldm"},
 812     {MO_DTPREL_HI,    "mips-dtprel-hi"},
 813     {MO_DTPREL_LO,    "mips-dtprel-lo"},
 814     {MO_GOTTPREL,     "mips-gottprel"},
 815     {MO_TPREL_HI,     "mips-tprel-hi"},
 816     {MO_TPREL_LO,     "mips-tprel-lo"},
 817     {MO_GPOFF_HI,     "mips-gpoff-hi"},
 818     {MO_GPOFF_LO,     "mips-gpoff-lo"},
 819     {MO_GOT_DISP,     "mips-got-disp"},
 820     {MO_GOT_PAGE,     "mips-got-page"},
 821     {MO_GOT_OFST,     "mips-got-ofst"},
 822     {MO_HIGHER,       "mips-higher"},
 823     {MO_HIGHEST,      "mips-highest"},
 824     {MO_GOT_HI16,     "mips-got-hi16"},
 825     {MO_GOT_LO16,     "mips-got-lo16"},
 826     {MO_CALL_HI16,    "mips-call-hi16"},
 827     {MO_CALL_LO16,    "mips-call-lo16"}
 828   };
 829   return makeArrayRef(Flags);
 830 }