lib/Target/PowerPC/PPCISelLowering.h

   1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that PPC uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  17
  18 #include "PPC.h"
  19 #include "PPCInstrInfo.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineMemOperand.h"
  23 #include "llvm/CodeGen/SelectionDAG.h"
  24 #include "llvm/CodeGen/SelectionDAGNodes.h"
  25 #include "llvm/CodeGen/TargetLowering.h"
  26 #include "llvm/CodeGen/ValueTypes.h"
  27 #include "llvm/IR/Attributes.h"
  28 #include "llvm/IR/CallingConv.h"
  29 #include "llvm/IR/Function.h"
  30 #include "llvm/IR/InlineAsm.h"
  31 #include "llvm/IR/Metadata.h"
  32 #include "llvm/IR/Type.h"
  33 #include "llvm/Support/MachineValueType.h"
  34 #include <utility>
  35
  36 namespace llvm {
  37
  38   namespace PPCISD {
  39
  40     // When adding a NEW PPCISD node please add it to the correct position in
  41     // the enum. The order of elements in this enum matters!
  42     // Values that are added after this entry:
  43     //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
  44     // are considerd memory opcodes and are treated differently than entries
  45     // that come before it. For example, ADD or MUL should be placed before
  46     // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
  47     // after it.
  48     enum NodeType : unsigned {
  49       // Start the numbering where the builtin ops and target ops leave off.
  50       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  51
  52       /// FSEL - Traditional three-operand fsel node.
  53       ///
  54       FSEL,
  55
  56       /// FCFID - The FCFID instruction, taking an f64 operand and producing
  57       /// and f64 value containing the FP representation of the integer that
  58       /// was temporarily in the f64 operand.
  59       FCFID,
  60
  61       /// Newer FCFID[US] integer-to-floating-point conversion instructions for
  62       /// unsigned integers and single-precision outputs.
  63       FCFIDU, FCFIDS, FCFIDUS,
  64
  65       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
  66       /// operand, producing an f64 value containing the integer representation
  67       /// of that FP value.
  68       FCTIDZ, FCTIWZ,
  69
  70       /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
  71       /// unsigned integers with round toward zero.
  72       FCTIDUZ, FCTIWUZ,
  73
  74       /// Floating-point-to-interger conversion instructions
  75       FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
  76
  77       /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
  78       /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
  79       VEXTS,
  80
  81       /// SExtVElems, takes an input vector of a smaller type and sign
  82       /// extends to an output vector of a larger type.
  83       SExtVElems,
  84
  85       /// Reciprocal estimate instructions (unary FP ops).
  86       FRE, FRSQRTE,
  87
  88       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
  89       // three v4f32 operands and producing a v4f32 result.
  90       VMADDFP, VNMSUBFP,
  91
  92       /// VPERM - The PPC VPERM Instruction.
  93       ///
  94       VPERM,
  95
  96       /// XXSPLT - The PPC VSX splat instructions
  97       ///
  98       XXSPLT,
  99
 100       /// VECINSERT - The PPC vector insert instruction
 101       ///
 102       VECINSERT,
 103
 104       /// XXREVERSE - The PPC VSX reverse instruction
 105       ///
 106       XXREVERSE,
 107
 108       /// VECSHL - The PPC vector shift left instruction
 109       ///
 110       VECSHL,
 111
 112       /// XXPERMDI - The PPC XXPERMDI instruction
 113       ///
 114       XXPERMDI,
 115
 116       /// The CMPB instruction (takes two operands of i32 or i64).
 117       CMPB,
 118
 119       /// Hi/Lo - These represent the high and low 16-bit parts of a global
 120       /// address respectively.  These nodes have two operands, the first of
 121       /// which must be a TargetGlobalAddress, and the second of which must be a
 122       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
 123       /// though these are usually folded into other nodes.
 124       Hi, Lo,
 125
 126       /// The following two target-specific nodes are used for calls through
 127       /// function pointers in the 64-bit SVR4 ABI.
 128
 129       /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
 130       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 131       /// compute an allocation on the stack.
 132       DYNALLOC,
 133
 134       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 135       /// compute an offset from native SP to the address  of the most recent
 136       /// dynamic alloca.
 137       DYNAREAOFFSET,
 138
 139       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
 140       /// at function entry, used for PIC code.
 141       GlobalBaseReg,
 142
 143       /// These nodes represent PPC shifts.
 144       ///
 145       /// For scalar types, only the last `n + 1` bits of the shift amounts
 146       /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
 147       /// for exact behaviors.
 148       ///
 149       /// For vector types, only the last n bits are used. See vsld.
 150       SRL, SRA, SHL,
 151
 152       /// The combination of sra[wd]i and addze used to implemented signed
 153       /// integer division by a power of 2. The first operand is the dividend,
 154       /// and the second is the constant shift amount (representing the
 155       /// divisor).
 156       SRA_ADDZE,
 157
 158       /// CALL - A direct function call.
 159       /// CALL_NOP is a call with the special NOP which follows 64-bit
 160       /// SVR4 calls.
 161       CALL, CALL_NOP,
 162
 163       /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
 164       /// MTCTR instruction.
 165       MTCTR,
 166
 167       /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
 168       /// BCTRL instruction.
 169       BCTRL,
 170
 171       /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
 172       /// instruction and the TOC reload required on SVR4 PPC64.
 173       BCTRL_LOAD_TOC,
 174
 175       /// Return with a flag operand, matched by 'blr'
 176       RET_FLAG,
 177
 178       /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
 179       /// This copies the bits corresponding to the specified CRREG into the
 180       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
 181       MFOCRF,
 182
 183       /// Direct move from a VSX register to a GPR
 184       MFVSR,
 185
 186       /// Direct move from a GPR to a VSX register (algebraic)
 187       MTVSRA,
 188
 189       /// Direct move from a GPR to a VSX register (zero)
 190       MTVSRZ,
 191
 192       /// Direct move of 2 consective GPR to a VSX register.
 193       BUILD_FP128,
 194
 195       /// Extract a subvector from signed integer vector and convert to FP.
 196       /// It is primarily used to convert a (widened) illegal integer vector
 197       /// type to a legal floating point vector type.
 198       /// For example v2i32 -> widened to v4i32 -> v2f64
 199       SINT_VEC_TO_FP,
 200
 201       /// Extract a subvector from unsigned integer vector and convert to FP.
 202       /// As with SINT_VEC_TO_FP, used for converting illegal types.
 203       UINT_VEC_TO_FP,
 204
 205       // FIXME: Remove these once the ANDI glue bug is fixed:
 206       /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
 207       /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
 208       /// implement truncation of i32 or i64 to i1.
 209       ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
 210
 211       // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
 212       // target (returns (Lo, Hi)). It takes a chain operand.
 213       READ_TIME_BASE,
 214
 215       // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
 216       EH_SJLJ_SETJMP,
 217
 218       // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
 219       EH_SJLJ_LONGJMP,
 220
 221       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
 222       /// instructions.  For lack of better number, we use the opcode number
 223       /// encoding for the OPC field to identify the compare.  For example, 838
 224       /// is VCMPGTSH.
 225       VCMP,
 226
 227       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
 228       /// altivec VCMP*o instructions.  For lack of better number, we use the
 229       /// opcode number encoding for the OPC field to identify the compare.  For
 230       /// example, 838 is VCMPGTSH.
 231       VCMPo,
 232
 233       /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
 234       /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
 235       /// condition register to branch on, OPC is the branch opcode to use (e.g.
 236       /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
 237       /// an optional input flag argument.
 238       COND_BRANCH,
 239
 240       /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
 241       /// loops.
 242       BDNZ, BDZ,
 243
 244       /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
 245       /// towards zero.  Used only as part of the long double-to-int
 246       /// conversion sequence.
 247       FADDRTZ,
 248
 249       /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
 250       MFFS,
 251
 252       /// TC_RETURN - A tail call return.
 253       ///   operand #0 chain
 254       ///   operand #1 callee (register or absolute)
 255       ///   operand #2 stack adjustment
 256       ///   operand #3 optional in flag
 257       TC_RETURN,
 258
 259       /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
 260       CR6SET,
 261       CR6UNSET,
 262
 263       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
 264       /// on PPC32.
 265       PPC32_GOT,
 266
 267       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
 268       /// local dynamic TLS on PPC32.
 269       PPC32_PICGOT,
 270
 271       /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
 272       /// TLS model, produces an ADDIS8 instruction that adds the GOT
 273       /// base to sym\@got\@tprel\@ha.
 274       ADDIS_GOT_TPREL_HA,
 275
 276       /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
 277       /// TLS model, produces a LD instruction with base register G8RReg
 278       /// and offset sym\@got\@tprel\@l.  This completes the addition that
 279       /// finds the offset of "sym" relative to the thread pointer.
 280       LD_GOT_TPREL_L,
 281
 282       /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
 283       /// model, produces an ADD instruction that adds the contents of
 284       /// G8RReg to the thread pointer.  Symbol contains a relocation
 285       /// sym\@tls which is to be replaced by the thread pointer and
 286       /// identifies to the linker that the instruction is part of a
 287       /// TLS sequence.
 288       ADD_TLS,
 289
 290       /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
 291       /// model, produces an ADDIS8 instruction that adds the GOT base
 292       /// register to sym\@got\@tlsgd\@ha.
 293       ADDIS_TLSGD_HA,
 294
 295       /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
 296       /// model, produces an ADDI8 instruction that adds G8RReg to
 297       /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
 298       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 299       ADDI_TLSGD_L,
 300
 301       /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
 302       /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
 303       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 304       GET_TLS_ADDR,
 305
 306       /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
 307       /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
 308       /// register assignment.
 309       ADDI_TLSGD_L_ADDR,
 310
 311       /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
 312       /// model, produces an ADDIS8 instruction that adds the GOT base
 313       /// register to sym\@got\@tlsld\@ha.
 314       ADDIS_TLSLD_HA,
 315
 316       /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
 317       /// model, produces an ADDI8 instruction that adds G8RReg to
 318       /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
 319       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 320       ADDI_TLSLD_L,
 321
 322       /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
 323       /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
 324       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 325       GET_TLSLD_ADDR,
 326
 327       /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
 328       /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
 329       /// following register assignment.
 330       ADDI_TLSLD_L_ADDR,
 331
 332       /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
 333       /// model, produces an ADDIS8 instruction that adds X3 to
 334       /// sym\@dtprel\@ha.
 335       ADDIS_DTPREL_HA,
 336
 337       /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
 338       /// model, produces an ADDI8 instruction that adds G8RReg to
 339       /// sym\@got\@dtprel\@l.
 340       ADDI_DTPREL_L,
 341
 342       /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
 343       /// during instruction selection to optimize a BUILD_VECTOR into
 344       /// operations on splats.  This is necessary to avoid losing these
 345       /// optimizations due to constant folding.
 346       VADD_SPLAT,
 347
 348       /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
 349       /// operand identifies the operating system entry point.
 350       SC,
 351
 352       /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
 353       CLRBHRB,
 354
 355       /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
 356       /// history rolling buffer entry.
 357       MFBHRBE,
 358
 359       /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
 360       RFEBB,
 361
 362       /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
 363       /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
 364       /// or stxvd2x instruction.  The chain is necessary because the
 365       /// sequence replaces a load and needs to provide the same number
 366       /// of outputs.
 367       XXSWAPD,
 368
 369       /// An SDNode for swaps that are not associated with any loads/stores
 370       /// and thereby have no chain.
 371       SWAP_NO_CHAIN,
 372
 373       /// QVFPERM = This corresponds to the QPX qvfperm instruction.
 374       QVFPERM,
 375
 376       /// QVGPCI = This corresponds to the QPX qvgpci instruction.
 377       QVGPCI,
 378
 379       /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
 380       QVALIGNI,
 381
 382       /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
 383       QVESPLATI,
 384
 385       /// QBFLT = Access the underlying QPX floating-point boolean
 386       /// representation.
 387       QBFLT,
 388
 389       /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
 390       /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
 391       /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
 392       /// i32.
 393       STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 394
 395       /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
 396       /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
 397       /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
 398       /// or i32.
 399       LBRX,
 400
 401       /// STFIWX - The STFIWX instruction.  The first operand is an input token
 402       /// chain, then an f64 value to store, then an address to store it to.
 403       STFIWX,
 404
 405       /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
 406       /// load which sign-extends from a 32-bit integer value into the
 407       /// destination 64-bit register.
 408       LFIWAX,
 409
 410       /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
 411       /// load which zero-extends from a 32-bit integer value into the
 412       /// destination 64-bit register.
 413       LFIWZX,
 414
 415       /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
 416       /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
 417       /// This can be used for converting loaded integers to floating point.
 418       LXSIZX,
 419
 420       /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
 421       /// chain, then an f64 value to store, then an address to store it to,
 422       /// followed by a byte-width for the store.
 423       STXSIX,
 424
 425       /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
 426       /// Maps directly to an lxvd2x instruction that will be followed by
 427       /// an xxswapd.
 428       LXVD2X,
 429
 430       /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
 431       /// Maps directly to an stxvd2x instruction that will be preceded by
 432       /// an xxswapd.
 433       STXVD2X,
 434
 435       /// Store scalar integers from VSR.
 436       ST_VSR_SCAL_INT,
 437
 438       /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
 439       /// The 4xf32 load used for v4i1 constants.
 440       QVLFSb,
 441
 442       /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
 443       /// except they ensure that the compare input is zero-extended for
 444       /// sub-word versions because the atomic loads zero-extend.
 445       ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
 446
 447       /// GPRC = TOC_ENTRY GA, TOC
 448       /// Loads the entry for GA from the TOC, where the TOC base is given by
 449       /// the last operand.
 450       TOC_ENTRY
 451     };
 452
 453   } // end namespace PPCISD
 454
 455   /// Define some predicates that are used for node matching.
 456   namespace PPC {
 457
 458     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
 459     /// VPKUHUM instruction.
 460     bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 461                               SelectionDAG &DAG);
 462
 463     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
 464     /// VPKUWUM instruction.
 465     bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 466                               SelectionDAG &DAG);
 467
 468     /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
 469     /// VPKUDUM instruction.
 470     bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 471                               SelectionDAG &DAG);
 472
 473     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
 474     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
 475     bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 476                             unsigned ShuffleKind, SelectionDAG &DAG);
 477
 478     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
 479     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
 480     bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 481                             unsigned ShuffleKind, SelectionDAG &DAG);
 482
 483     /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
 484     /// a VMRGEW or VMRGOW instruction
 485     bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
 486                              unsigned ShuffleKind, SelectionDAG &DAG);
 487     /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
 488     /// for a XXSLDWI instruction.
 489     bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 490                               bool &Swap, bool IsLE);
 491
 492     /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
 493     /// for a XXBRH instruction.
 494     bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
 495
 496     /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
 497     /// for a XXBRW instruction.
 498     bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
 499
 500     /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
 501     /// for a XXBRD instruction.
 502     bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
 503
 504     /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
 505     /// for a XXBRQ instruction.
 506     bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
 507
 508     /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
 509     /// for a XXPERMDI instruction.
 510     bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 511                               bool &Swap, bool IsLE);
 512
 513     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
 514     /// shift amount, otherwise return -1.
 515     int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
 516                             SelectionDAG &DAG);
 517
 518     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 519     /// specifies a splat of a single element that is suitable for input to
 520     /// VSPLTB/VSPLTH/VSPLTW.
 521     bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
 522
 523     /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
 524     /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
 525     /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
 526     /// vector into the other. This function will also set a couple of
 527     /// output parameters for how much the source vector needs to be shifted and
 528     /// what byte number needs to be specified for the instruction to put the
 529     /// element in the desired location of the target vector.
 530     bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 531                          unsigned &InsertAtByte, bool &Swap, bool IsLE);
 532
 533     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 534     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
 535     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
 536
 537     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
 538     /// formed by using a vspltis[bhw] instruction of the specified element
 539     /// size, return the constant being splatted.  The ByteSize field indicates
 540     /// the number of bytes of each element [124] -> [bhw].
 541     SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
 542
 543     /// If this is a qvaligni shuffle mask, return the shift
 544     /// amount, otherwise return -1.
 545     int isQVALIGNIShuffleMask(SDNode *N);
 546
 547   } // end namespace PPC
 548
 549   class PPCTargetLowering : public TargetLowering {
 550     const PPCSubtarget &Subtarget;
 551
 552   public:
 553     explicit PPCTargetLowering(const PPCTargetMachine &TM,
 554                                const PPCSubtarget &STI);
 555
 556     /// getTargetNodeName() - This method returns the name of a target specific
 557     /// DAG node.
 558     const char *getTargetNodeName(unsigned Opcode) const override;
 559
 560     /// getPreferredVectorAction - The code we generate when vector types are
 561     /// legalized by promoting the integer element type is often much worse
 562     /// than code we generate if we widen the type for applicable vector types.
 563     /// The issue with promoting is that the vector is scalaraized, individual
 564     /// elements promoted and then the vector is rebuilt. So say we load a pair
 565     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
 566     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
 567     /// then the VPERM for the shuffle. All in all a very slow sequence.
 568     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
 569       const override {
 570       if (VT.getScalarSizeInBits() % 8 == 0)
 571         return TypeWidenVector;
 572       return TargetLoweringBase::getPreferredVectorAction(VT);
 573     }
 574
 575     bool useSoftFloat() const override;
 576
 577     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
 578       return MVT::i32;
 579     }
 580
 581     bool isCheapToSpeculateCttz() const override {
 582       return true;
 583     }
 584
 585     bool isCheapToSpeculateCtlz() const override {
 586       return true;
 587     }
 588
 589     bool isCtlzFast() const override {
 590       return true;
 591     }
 592
 593     bool hasAndNotCompare(SDValue) const override {
 594       return true;
 595     }
 596
 597     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 598       return VT.isScalarInteger();
 599     }
 600
 601     bool supportSplitCSR(MachineFunction *MF) const override {
 602       return
 603         MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 604         MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 605     }
 606
 607     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 608
 609     void insertCopiesSplitCSR(
 610       MachineBasicBlock *Entry,
 611       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 612
 613     /// getSetCCResultType - Return the ISD::SETCC ValueType
 614     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 615                            EVT VT) const override;
 616
 617     /// Return true if target always beneficiates from combining into FMA for a
 618     /// given value type. This must typically return false on targets where FMA
 619     /// takes more cycles to execute than FADD.
 620     bool enableAggressiveFMAFusion(EVT VT) const override;
 621
 622     /// getPreIndexedAddressParts - returns true by value, base pointer and
 623     /// offset pointer and addressing mode by reference if the node's address
 624     /// can be legally represented as pre-indexed load / store address.
 625     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
 626                                    SDValue &Offset,
 627                                    ISD::MemIndexedMode &AM,
 628                                    SelectionDAG &DAG) const override;
 629
 630     /// SelectAddressRegReg - Given the specified addressed, check to see if it
 631     /// can be represented as an indexed [r+r] operation.  Returns false if it
 632     /// can be more efficiently represented with [r+imm].
 633     bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
 634                              SelectionDAG &DAG) const;
 635
 636     /// SelectAddressRegImm - Returns true if the address N can be represented
 637     /// by a base register plus a signed 16-bit displacement [r+imm], and if it
 638     /// is not better represented as reg+reg.  If Aligned is true, only accept
 639     /// displacements suitable for STD and friends, i.e. multiples of 4.
 640     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
 641                              SelectionDAG &DAG, unsigned Alignment) const;
 642
 643     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
 644     /// represented as an indexed [r+r] operation.
 645     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
 646                                  SelectionDAG &DAG) const;
 647
 648     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 649
 650     /// LowerOperation - Provide custom lowering hooks for some operations.
 651     ///
 652     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 653
 654     /// ReplaceNodeResults - Replace the results of node with an illegal result
 655     /// type with new values built out of custom code.
 656     ///
 657     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 658                             SelectionDAG &DAG) const override;
 659
 660     SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 661     SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 662
 663     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 664
 665     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 666                           std::vector<SDNode *> *Created) const override;
 667
 668     unsigned getRegisterByName(const char* RegName, EVT VT,
 669                                SelectionDAG &DAG) const override;
 670
 671     void computeKnownBitsForTargetNode(const SDValue Op,
 672                                        KnownBits &Known,
 673                                        const APInt &DemandedElts,
 674                                        const SelectionDAG &DAG,
 675                                        unsigned Depth = 0) const override;
 676
 677     unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
 678
 679     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 680       return true;
 681     }
 682
 683     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 684                                   AtomicOrdering Ord) const override;
 685     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 686                                    AtomicOrdering Ord) const override;
 687
 688     MachineBasicBlock *
 689     EmitInstrWithCustomInserter(MachineInstr &MI,
 690                                 MachineBasicBlock *MBB) const override;
 691     MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
 692                                         MachineBasicBlock *MBB,
 693                                         unsigned AtomicSize,
 694                                         unsigned BinOpcode,
 695                                         unsigned CmpOpcode = 0,
 696                                         unsigned CmpPred = 0) const;
 697     MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
 698                                                 MachineBasicBlock *MBB,
 699                                                 bool is8bit,
 700                                                 unsigned Opcode,
 701                                                 unsigned CmpOpcode = 0,
 702                                                 unsigned CmpPred = 0) const;
 703
 704     MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
 705                                         MachineBasicBlock *MBB) const;
 706
 707     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
 708                                          MachineBasicBlock *MBB) const;
 709
 710     ConstraintType getConstraintType(StringRef Constraint) const override;
 711
 712     /// Examine constraint string and operand type and determine a weight value.
 713     /// The operand object must already have been set up with the operand type.
 714     ConstraintWeight getSingleConstraintMatchWeight(
 715       AsmOperandInfo &info, const char *constraint) const override;
 716
 717     std::pair<unsigned, const TargetRegisterClass *>
 718     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 719                                  StringRef Constraint, MVT VT) const override;
 720
 721     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 722     /// function arguments in the caller parameter area.  This is the actual
 723     /// alignment, not its logarithm.
 724     unsigned getByValTypeAlignment(Type *Ty,
 725                                    const DataLayout &DL) const override;
 726
 727     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 728     /// vector.  If it is invalid, don't add anything to Ops.
 729     void LowerAsmOperandForConstraint(SDValue Op,
 730                                       std::string &Constraint,
 731                                       std::vector<SDValue> &Ops,
 732                                       SelectionDAG &DAG) const override;
 733
 734     unsigned
 735     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 736       if (ConstraintCode == "es")
 737         return InlineAsm::Constraint_es;
 738       else if (ConstraintCode == "o")
 739         return InlineAsm::Constraint_o;
 740       else if (ConstraintCode == "Q")
 741         return InlineAsm::Constraint_Q;
 742       else if (ConstraintCode == "Z")
 743         return InlineAsm::Constraint_Z;
 744       else if (ConstraintCode == "Zy")
 745         return InlineAsm::Constraint_Zy;
 746       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 747     }
 748
 749     /// isLegalAddressingMode - Return true if the addressing mode represented
 750     /// by AM is legal for this target, for a load/store of the specified type.
 751     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 752                                Type *Ty, unsigned AS,
 753                                Instruction *I = nullptr) const override;
 754
 755     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 756     /// icmp immediate, that is the target has icmp instructions which can
 757     /// compare a register against the immediate without having to materialize
 758     /// the immediate into a register.
 759     bool isLegalICmpImmediate(int64_t Imm) const override;
 760
 761     /// isLegalAddImmediate - Return true if the specified immediate is legal
 762     /// add immediate, that is the target has add instructions which can
 763     /// add a register and the immediate without having to materialize
 764     /// the immediate into a register.
 765     bool isLegalAddImmediate(int64_t Imm) const override;
 766
 767     /// isTruncateFree - Return true if it's free to truncate a value of
 768     /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
 769     /// register X1 to i32 by referencing its sub-register R1.
 770     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 771     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 772
 773     bool isZExtFree(SDValue Val, EVT VT2) const override;
 774
 775     bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
 776
 777     /// Returns true if it is beneficial to convert a load of a constant
 778     /// to just the constant itself.
 779     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 780                                            Type *Ty) const override;
 781
 782     bool convertSelectOfConstantsToMath(EVT VT) const override {
 783       return true;
 784     }
 785
 786     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 787
 788     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 789                             const CallInst &I,
 790                             MachineFunction &MF,
 791                             unsigned Intrinsic) const override;
 792
 793     /// getOptimalMemOpType - Returns the target specific optimal type for load
 794     /// and store operations as a result of memset, memcpy, and memmove
 795     /// lowering. If DstAlign is zero that means it's safe to destination
 796     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 797     /// means there isn't a need to check it against alignment requirement,
 798     /// probably because the source does not need to be loaded. If 'IsMemset' is
 799     /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
 800     /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
 801     /// source is constant so it does not need to be loaded.
 802     /// It returns EVT::Other if the type should be determined using generic
 803     /// target-independent logic.
 804     EVT
 805     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
 806                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
 807                         MachineFunction &MF) const override;
 808
 809     /// Is unaligned memory access allowed for the given type, and is it fast
 810     /// relative to software emulation.
 811     bool allowsMisalignedMemoryAccesses(EVT VT,
 812                                         unsigned AddrSpace,
 813                                         unsigned Align = 1,
 814                                         bool *Fast = nullptr) const override;
 815
 816     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 817     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 818     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 819     /// expanded to fmul + fadd.
 820     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 821
 822     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 823
 824     // Should we expand the build vector with shuffles?
 825     bool
 826     shouldExpandBuildVectorWithShuffles(EVT VT,
 827                                         unsigned DefinedValues) const override;
 828
 829     /// createFastISel - This method returns a target-specific FastISel object,
 830     /// or null if the target does not support "fast" instruction selection.
 831     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
 832                              const TargetLibraryInfo *LibInfo) const override;
 833
 834     /// Returns true if an argument of type Ty needs to be passed in a
 835     /// contiguous block of registers in calling convention CallConv.
 836     bool functionArgumentNeedsConsecutiveRegisters(
 837       Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
 838       // We support any array type as "consecutive" block in the parameter
 839       // save area.  The element type defines the alignment requirement and
 840       // whether the argument should go in GPRs, FPRs, or VRs if available.
 841       //
 842       // Note that clang uses this capability both to implement the ELFv2
 843       // homogeneous float/vector aggregate ABI, and to avoid having to use
 844       // "byval" when passing aggregates that might fully fit in registers.
 845       return Ty->isArrayTy();
 846     }
 847
 848     /// If a physical register, this returns the register that receives the
 849     /// exception address on entry to an EH pad.
 850     unsigned
 851     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 852
 853     /// If a physical register, this returns the register that receives the
 854     /// exception typeid on entry to a landing pad.
 855     unsigned
 856     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 857
 858     /// Override to support customized stack guard loading.
 859     bool useLoadStackGuardNode() const override;
 860     void insertSSPDeclarations(Module &M) const override;
 861
 862     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 863
 864     unsigned getJumpTableEncoding() const override;
 865     bool isJumpTableRelative() const override;
 866     SDValue getPICJumpTableRelocBase(SDValue Table,
 867                                      SelectionDAG &DAG) const override;
 868     const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
 869                                                unsigned JTI,
 870                                                MCContext &Ctx) const override;
 871
 872   private:
 873     struct ReuseLoadInfo {
 874       SDValue Ptr;
 875       SDValue Chain;
 876       SDValue ResChain;
 877       MachinePointerInfo MPI;
 878       bool IsDereferenceable = false;
 879       bool IsInvariant = false;
 880       unsigned Alignment = 0;
 881       AAMDNodes AAInfo;
 882       const MDNode *Ranges = nullptr;
 883
 884       ReuseLoadInfo() = default;
 885
 886       MachineMemOperand::Flags MMOFlags() const {
 887         MachineMemOperand::Flags F = MachineMemOperand::MONone;
 888         if (IsDereferenceable)
 889           F |= MachineMemOperand::MODereferenceable;
 890         if (IsInvariant)
 891           F |= MachineMemOperand::MOInvariant;
 892         return F;
 893       }
 894     };
 895
 896     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 897       // Addrspacecasts are always noops.
 898       return true;
 899     }
 900
 901     bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
 902                              SelectionDAG &DAG,
 903                              ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
 904     void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
 905                          SelectionDAG &DAG) const;
 906
 907     void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
 908                                 SelectionDAG &DAG, const SDLoc &dl) const;
 909     SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
 910                                      const SDLoc &dl) const;
 911
 912     bool directMoveIsProfitable(const SDValue &Op) const;
 913     SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
 914                                      const SDLoc &dl) const;
 915
 916     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
 917     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
 918
 919     bool
 920     IsEligibleForTailCallOptimization(SDValue Callee,
 921                                       CallingConv::ID CalleeCC,
 922                                       bool isVarArg,
 923                                       const SmallVectorImpl<ISD::InputArg> &Ins,
 924                                       SelectionDAG& DAG) const;
 925
 926     bool
 927     IsEligibleForTailCallOptimization_64SVR4(
 928                                     SDValue Callee,
 929                                     CallingConv::ID CalleeCC,
 930                                     ImmutableCallSite CS,
 931                                     bool isVarArg,
 932                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 933                                     const SmallVectorImpl<ISD::InputArg> &Ins,
 934                                     SelectionDAG& DAG) const;
 935
 936     SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
 937                                          SDValue Chain, SDValue &LROpOut,
 938                                          SDValue &FPOpOut,
 939                                          const SDLoc &dl) const;
 940
 941     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 942     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 943     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 944     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 945     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 946     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 947     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 948     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 949     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 950     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 951     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 952     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 953     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
 954     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
 955     SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
 956     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 957     SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
 958     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
 959     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 960     SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
 961     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 962     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
 963                            const SDLoc &dl) const;
 964     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 965     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 966     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
 967     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
 968     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
 969     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 970     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
 971     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 972     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 973     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 974     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
 975     SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
 976     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
 977     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
 978     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
 979     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 980     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
 981
 982     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
 983     SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
 984
 985     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 986                             CallingConv::ID CallConv, bool isVarArg,
 987                             const SmallVectorImpl<ISD::InputArg> &Ins,
 988                             const SDLoc &dl, SelectionDAG &DAG,
 989                             SmallVectorImpl<SDValue> &InVals) const;
 990     SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
 991                        bool isTailCall, bool isVarArg, bool isPatchPoint,
 992                        bool hasNest, SelectionDAG &DAG,
 993                        SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
 994                        SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
 995                        SDValue &Callee, int SPDiff, unsigned NumBytes,
 996                        const SmallVectorImpl<ISD::InputArg> &Ins,
 997                        SmallVectorImpl<SDValue> &InVals,
 998                        ImmutableCallSite CS) const;
 999
1000     SDValue
1001     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1002                          const SmallVectorImpl<ISD::InputArg> &Ins,
1003                          const SDLoc &dl, SelectionDAG &DAG,
1004                          SmallVectorImpl<SDValue> &InVals) const override;
1005
1006     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1007                       SmallVectorImpl<SDValue> &InVals) const override;
1008
1009     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1010                         bool isVarArg,
1011                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1012                         LLVMContext &Context) const override;
1013
1014     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1015                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1016                         const SmallVectorImpl<SDValue> &OutVals,
1017                         const SDLoc &dl, SelectionDAG &DAG) const override;
1018
1019     SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1020                               SelectionDAG &DAG, SDValue ArgVal,
1021                               const SDLoc &dl) const;
1022
1023     SDValue LowerFormalArguments_Darwin(
1024         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1025         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1026         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1027     SDValue LowerFormalArguments_64SVR4(
1028         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1029         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1030         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1031     SDValue LowerFormalArguments_32SVR4(
1032         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1033         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1034         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1035
1036     SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1037                                        SDValue CallSeqStart,
1038                                        ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1039                                        const SDLoc &dl) const;
1040
1041     SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1042                              CallingConv::ID CallConv, bool isVarArg,
1043                              bool isTailCall, bool isPatchPoint,
1044                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1045                              const SmallVectorImpl<SDValue> &OutVals,
1046                              const SmallVectorImpl<ISD::InputArg> &Ins,
1047                              const SDLoc &dl, SelectionDAG &DAG,
1048                              SmallVectorImpl<SDValue> &InVals,
1049                              ImmutableCallSite CS) const;
1050     SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1051                              CallingConv::ID CallConv, bool isVarArg,
1052                              bool isTailCall, bool isPatchPoint,
1053                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1054                              const SmallVectorImpl<SDValue> &OutVals,
1055                              const SmallVectorImpl<ISD::InputArg> &Ins,
1056                              const SDLoc &dl, SelectionDAG &DAG,
1057                              SmallVectorImpl<SDValue> &InVals,
1058                              ImmutableCallSite CS) const;
1059     SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1060                              CallingConv::ID CallConv, bool isVarArg,
1061                              bool isTailCall, bool isPatchPoint,
1062                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1063                              const SmallVectorImpl<SDValue> &OutVals,
1064                              const SmallVectorImpl<ISD::InputArg> &Ins,
1065                              const SDLoc &dl, SelectionDAG &DAG,
1066                              SmallVectorImpl<SDValue> &InVals,
1067                              ImmutableCallSite CS) const;
1068
1069     SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1070     SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1071     SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1072
1073     SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1074     SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1075     SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1076     SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1077     SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1078     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1079     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1080     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1081
1082     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1083     /// SETCC with integer subtraction when (1) there is a legal way of doing it
1084     /// (2) keeping the result of comparison in GPR has performance benefit.
1085     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1086
1087     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1088                             int &RefinementSteps, bool &UseOneConstNR,
1089                             bool Reciprocal) const override;
1090     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1091                              int &RefinementSteps) const override;
1092     unsigned combineRepeatedFPDivisors() const override;
1093
1094     CCAssignFn *useFastISelCCs(unsigned Flag) const;
1095
1096     SDValue
1097     combineElementTruncationToVectorTruncation(SDNode *N,
1098                                                DAGCombinerInfo &DCI) const;
1099
1100     /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1101     /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1102     /// essentially any shuffle of v8i16 vectors that just inserts one element
1103     /// from one vector into the other.
1104     SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1105
1106     /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1107     /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1108     /// essentially v16i8 vector version of VINSERTH.
1109     SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1110
1111     // Return whether the call instruction can potentially be optimized to a
1112     // tail call. This will cause the optimizers to attempt to move, or
1113     // duplicate return instructions to help enable tail call optimizations.
1114     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1115     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1116   }; // end class PPCTargetLowering
1117
1118   namespace PPC {
1119
1120     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1121                              const TargetLibraryInfo *LibInfo);
1122
1123   } // end namespace PPC
1124
1125   bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1126                                   CCValAssign::LocInfo &LocInfo,
1127                                   ISD::ArgFlagsTy &ArgFlags,
1128                                   CCState &State);
1129
1130   bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1131                                          MVT &LocVT,
1132                                          CCValAssign::LocInfo &LocInfo,
1133                                          ISD::ArgFlagsTy &ArgFlags,
1134                                          CCState &State);
1135
1136   bool
1137   CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
1138                                                  MVT &LocVT,
1139                                                  CCValAssign::LocInfo &LocInfo,
1140                                                  ISD::ArgFlagsTy &ArgFlags,
1141                                                  CCState &State);
1142
1143   bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1144                                            MVT &LocVT,
1145                                            CCValAssign::LocInfo &LocInfo,
1146                                            ISD::ArgFlagsTy &ArgFlags,
1147                                            CCState &State);
1148
1149   bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1150   bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1151
1152 } // end namespace llvm
1153
1154 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H