lib/Target/RISCV/RISCVTargetMachine.cpp

   1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Implements the info about RISCV target spec.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "RISCV.h"
  15 #include "RISCVTargetMachine.h"
  16 #include "RISCVTargetObjectFile.h"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  20 #include "llvm/CodeGen/TargetPassConfig.h"
  21 #include "llvm/IR/LegacyPassManager.h"
  22 #include "llvm/Support/FormattedStream.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24 #include "llvm/Target/TargetOptions.h"
  25 using namespace llvm;
  26
  27 extern "C" void LLVMInitializeRISCVTarget() {
  28   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
  29   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
  30 }
  31
  32 static std::string computeDataLayout(const Triple &TT) {
  33   if (TT.isArch64Bit()) {
  34     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
  35   } else {
  36     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
  37     return "e-m:e-p:32:32-i64:64-n32-S128";
  38   }
  39 }
  40
  41 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
  42                                            Optional<Reloc::Model> RM) {
  43   if (!RM.hasValue())
  44     return Reloc::Static;
  45   return *RM;
  46 }
  47
  48 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
  49   if (CM)
  50     return *CM;
  51   return CodeModel::Small;
  52 }
  53
  54 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
  55                                        StringRef CPU, StringRef FS,
  56                                        const TargetOptions &Options,
  57                                        Optional<Reloc::Model> RM,
  58                                        Optional<CodeModel::Model> CM,
  59                                        CodeGenOpt::Level OL, bool JIT)
  60     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
  61                         getEffectiveRelocModel(TT, RM),
  62                         getEffectiveCodeModel(CM), OL),
  63       TLOF(make_unique<RISCVELFTargetObjectFile>()),
  64       Subtarget(TT, CPU, FS, *this) {
  65   initAsmInfo();
  66 }
  67
  68 namespace {
  69 class RISCVPassConfig : public TargetPassConfig {
  70 public:
  71   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
  72       : TargetPassConfig(TM, PM) {}
  73
  74   RISCVTargetMachine &getRISCVTargetMachine() const {
  75     return getTM<RISCVTargetMachine>();
  76   }
  77
  78   void addIRPasses() override;
  79   bool addInstSelector() override;
  80   void addPreEmitPass() override;
  81   void addPreRegAlloc() override;
  82 };
  83 }
  84
  85 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
  86   return new RISCVPassConfig(*this, PM);
  87 }
  88
  89 void RISCVPassConfig::addIRPasses() {
  90   addPass(createAtomicExpandPass());
  91   TargetPassConfig::addIRPasses();
  92 }
  93
  94 bool RISCVPassConfig::addInstSelector() {
  95   addPass(createRISCVISelDag(getRISCVTargetMachine()));
  96
  97   return false;
  98 }
  99
 100 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
 101
 102 void RISCVPassConfig::addPreRegAlloc() {
 103   addPass(createRISCVMergeBaseOffsetOptPass());
 104 }