1 //===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the XCore target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 include "XCoreRegisterInfo.td"
25 include "XCoreInstrInfo.td"
26 include "XCoreCallingConv.td"
28 def XCoreInstrInfo : InstrInfo;
30 //===----------------------------------------------------------------------===//
31 // XCore processors supported.
32 //===----------------------------------------------------------------------===//
34 class Proc<string Name, list<SubtargetFeature> Features>
35 : Processor<Name, NoItineraries, Features>;
37 def : Proc<"generic", []>;
38 def : Proc<"xs1b-generic", []>;
40 //===----------------------------------------------------------------------===//
41 // Declare the target which we are implementing
42 //===----------------------------------------------------------------------===//
45 // Pull in Instruction Info:
46 let InstructionSet = XCoreInstrInfo;