lib/Target/XCore/XCoreISelDAGToDAG.cpp

   1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines an instruction selector for the XCore target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "XCore.h"
  15 #include "XCoreTargetMachine.h"
  16 #include "llvm/CodeGen/MachineFrameInfo.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/CodeGen/SelectionDAG.h"
  21 #include "llvm/CodeGen/SelectionDAGISel.h"
  22 #include "llvm/CodeGen/TargetLowering.h"
  23 #include "llvm/IR/CallingConv.h"
  24 #include "llvm/IR/Constants.h"
  25 #include "llvm/IR/DerivedTypes.h"
  26 #include "llvm/IR/Function.h"
  27 #include "llvm/IR/Intrinsics.h"
  28 #include "llvm/IR/LLVMContext.h"
  29 #include "llvm/Support/Debug.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/raw_ostream.h"
  32 using namespace llvm;
  33
  34 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
  35 /// instructions for SelectionDAG operations.
  36 ///
  37 namespace {
  38   class XCoreDAGToDAGISel : public SelectionDAGISel {
  39
  40   public:
  41     XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel)
  42       : SelectionDAGISel(TM, OptLevel) {}
  43
  44     void Select(SDNode *N) override;
  45     bool tryBRIND(SDNode *N);
  46
  47     /// getI32Imm - Return a target constant with the specified value, of type
  48     /// i32.
  49     inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) {
  50       return CurDAG->getTargetConstant(Imm, dl, MVT::i32);
  51     }
  52
  53     inline bool immMskBitp(SDNode *inN) const {
  54       ConstantSDNode *N = cast<ConstantSDNode>(inN);
  55       uint32_t value = (uint32_t)N->getZExtValue();
  56       if (!isMask_32(value)) {
  57         return false;
  58       }
  59       int msksize = 32 - countLeadingZeros(value);
  60       return (msksize >= 1 && msksize <= 8) ||
  61               msksize == 16 || msksize == 24 || msksize == 32;
  62     }
  63
  64     // Complex Pattern Selectors.
  65     bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
  66
  67     bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
  68                                       std::vector<SDValue> &OutOps) override;
  69
  70     StringRef getPassName() const override {
  71       return "XCore DAG->DAG Pattern Instruction Selection";
  72     }
  73
  74     // Include the pieces autogenerated from the target description.
  75   #include "XCoreGenDAGISel.inc"
  76   };
  77 }  // end anonymous namespace
  78
  79 /// createXCoreISelDag - This pass converts a legalized DAG into a
  80 /// XCore-specific DAG, ready for instruction scheduling.
  81 ///
  82 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM,
  83                                        CodeGenOpt::Level OptLevel) {
  84   return new XCoreDAGToDAGISel(TM, OptLevel);
  85 }
  86
  87 bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base,
  88                                        SDValue &Offset) {
  89   FrameIndexSDNode *FIN = nullptr;
  90   if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
  91     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
  92     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
  93     return true;
  94   }
  95   if (Addr.getOpcode() == ISD::ADD) {
  96     ConstantSDNode *CN = nullptr;
  97     if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
  98       && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
  99       && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
 100       // Constant positive word offset from frame index
 101       Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
 102       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
 103                                          MVT::i32);
 104       return true;
 105     }
 106   }
 107   return false;
 108 }
 109
 110 bool XCoreDAGToDAGISel::
 111 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
 112                              std::vector<SDValue> &OutOps) {
 113   SDValue Reg;
 114   switch (ConstraintID) {
 115   default: return true;
 116   case InlineAsm::Constraint_m: // Memory.
 117     switch (Op.getOpcode()) {
 118     default: return true;
 119     case XCoreISD::CPRelativeWrapper:
 120       Reg = CurDAG->getRegister(XCore::CP, MVT::i32);
 121       break;
 122     case XCoreISD::DPRelativeWrapper:
 123       Reg = CurDAG->getRegister(XCore::DP, MVT::i32);
 124       break;
 125     }
 126   }
 127   OutOps.push_back(Reg);
 128   OutOps.push_back(Op.getOperand(0));
 129   return false;
 130 }
 131
 132 void XCoreDAGToDAGISel::Select(SDNode *N) {
 133   SDLoc dl(N);
 134   switch (N->getOpcode()) {
 135   default: break;
 136   case ISD::Constant: {
 137     uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
 138     if (immMskBitp(N)) {
 139       // Transformation function: get the size of a mask
 140       // Look for the first non-zero bit
 141       SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl);
 142       ReplaceNode(N, CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
 143                                             MVT::i32, MskSize));
 144       return;
 145     }
 146     else if (!isUInt<16>(Val)) {
 147       SDValue CPIdx = CurDAG->getTargetConstantPool(
 148           ConstantInt::get(Type::getInt32Ty(*CurDAG->getContext()), Val),
 149           getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
 150       SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
 151                                             MVT::Other, CPIdx,
 152                                             CurDAG->getEntryNode());
 153       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
 154       MemOp[0] =
 155           MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
 156                                    MachineMemOperand::MOLoad, 4, 4);
 157       cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1);
 158       ReplaceNode(N, node);
 159       return;
 160     }
 161     break;
 162   }
 163   case XCoreISD::LADD: {
 164     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 165                         N->getOperand(2) };
 166     ReplaceNode(N, CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32,
 167                                           MVT::i32, Ops));
 168     return;
 169   }
 170   case XCoreISD::LSUB: {
 171     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 172                         N->getOperand(2) };
 173     ReplaceNode(N, CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32,
 174                                           MVT::i32, Ops));
 175     return;
 176   }
 177   case XCoreISD::MACCU: {
 178     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 179                       N->getOperand(2), N->getOperand(3) };
 180     ReplaceNode(N, CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32,
 181                                           MVT::i32, Ops));
 182     return;
 183   }
 184   case XCoreISD::MACCS: {
 185     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 186                       N->getOperand(2), N->getOperand(3) };
 187     ReplaceNode(N, CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32,
 188                                           MVT::i32, Ops));
 189     return;
 190   }
 191   case XCoreISD::LMUL: {
 192     SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
 193                       N->getOperand(2), N->getOperand(3) };
 194     ReplaceNode(N, CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32,
 195                                           MVT::i32, Ops));
 196     return;
 197   }
 198   case XCoreISD::CRC8: {
 199     SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
 200     ReplaceNode(N, CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32,
 201                                           MVT::i32, Ops));
 202     return;
 203   }
 204   case ISD::BRIND:
 205     if (tryBRIND(N))
 206       return;
 207     break;
 208   // Other cases are autogenerated.
 209   }
 210   SelectCode(N);
 211 }
 212
 213 /// Given a chain return a new chain where any appearance of Old is replaced
 214 /// by New. There must be at most one instruction between Old and Chain and
 215 /// this instruction must be a TokenFactor. Returns an empty SDValue if
 216 /// these conditions don't hold.
 217 static SDValue
 218 replaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New)
 219 {
 220   if (Chain == Old)
 221     return New;
 222   if (Chain->getOpcode() != ISD::TokenFactor)
 223     return SDValue();
 224   SmallVector<SDValue, 8> Ops;
 225   bool found = false;
 226   for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) {
 227     if (Chain->getOperand(i) == Old) {
 228       Ops.push_back(New);
 229       found = true;
 230     } else {
 231       Ops.push_back(Chain->getOperand(i));
 232     }
 233   }
 234   if (!found)
 235     return SDValue();
 236   return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
 237 }
 238
 239 bool XCoreDAGToDAGISel::tryBRIND(SDNode *N) {
 240   SDLoc dl(N);
 241   // (brind (int_xcore_checkevent (addr)))
 242   SDValue Chain = N->getOperand(0);
 243   SDValue Addr = N->getOperand(1);
 244   if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
 245     return false;
 246   unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
 247   if (IntNo != Intrinsic::xcore_checkevent)
 248     return false;
 249   SDValue nextAddr = Addr->getOperand(2);
 250   SDValue CheckEventChainOut(Addr.getNode(), 1);
 251   if (!CheckEventChainOut.use_empty()) {
 252     // If the chain out of the checkevent intrinsic is an operand of the
 253     // indirect branch or used in a TokenFactor which is the operand of the
 254     // indirect branch then build a new chain which uses the chain coming into
 255     // the checkevent intrinsic instead.
 256     SDValue CheckEventChainIn = Addr->getOperand(0);
 257     SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut,
 258                                       CheckEventChainIn);
 259     if (!NewChain.getNode())
 260       return false;
 261     Chain = NewChain;
 262   }
 263   // Enable events on the thread using setsr 1 and then disable them immediately
 264   // after with clrsr 1. If any resources owned by the thread are ready an event
 265   // will be taken. If no resource is ready we branch to the address which was
 266   // the operand to the checkevent intrinsic.
 267   SDValue constOne = getI32Imm(1, dl);
 268   SDValue Glue =
 269     SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,
 270                                    constOne, Chain), 0);
 271   Glue =
 272     SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue,
 273                                    constOne, Glue), 0);
 274   if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper &&
 275       nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
 276     CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other,
 277                          nextAddr->getOperand(0), Glue);
 278     return true;
 279   }
 280   CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue);
 281   return true;
 282 }