test/MC/Hexagon/instructions/alu32_alu.s

   1 # RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
   2 # Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
   3
   4 # Add
   5 # CHECK: f1 c3 15 b0
   6 r17 = add(r21, #31)
   7 # CHECK: 11 df 15 f3
   8 r17 = add(r21, r31)
   9 # CHECK: 11 df 55 f6
  10 r17 = add(r21, r31):sat
  11
  12 # And
  13 # CHECK: f1 c3 15 76
  14 r17 = and(r21, #31)
  15 # CHECK: f1 c3 95 76
  16 r17 = or(r21, #31)
  17 # CHECK: 11 df 15 f1
  18 r17 = and(r21, r31)
  19 # CHECK: 11 df 35 f1
  20 r17 = or(r21, r31)
  21 # CHECK: 11 df 75 f1
  22 r17 = xor(r21, r31)
  23 # CHECK: 11 d5 9f f1
  24 r17 = and(r21, ~r31)
  25 # CHECK: 11 d5 bf f1
  26 r17 = or(r21, ~r31)
  27
  28 # Nop
  29 # CHECK: 00 c0 00 7f
  30 nop
  31
  32 # Subtract
  33 # CHECK: b1 c2 5f 76
  34 r17 = sub(#21, r31)
  35 # CHECK: 11 df 35 f3
  36 r17 = sub(r31, r21)
  37 # CHECK: 11 df d5 f6
  38 r17 = sub(r31, r21):sat
  39
  40 # Sign extend
  41 # CHECK: 11 c0 bf 70
  42 r17 = sxtb(r31)
  43
  44 # Transfer immediate
  45 # CHECK: 15 c0 31 72
  46 r17.h = #21
  47 # CHECK: 15 c0 31 71
  48 r17.l = #21
  49 # CHECK: f1 ff 5f 78
  50 r17 = #32767
  51 # CHECK: f1 ff df 78
  52 r17 = #-1
  53
  54 # Transfer register
  55 # CHECK: 11 c0 75 70
  56 r17 = r21
  57
  58 # Vector add halfwords
  59 # CHECK: 11 df 15 f6
  60 r17 = vaddh(r21, r31)
  61 # CHECK: 11 df 35 f6
  62 r17 = vaddh(r21, r31):sat
  63 # CHECK: 11 df 75 f6
  64 r17 = vadduh(r21, r31):sat
  65
  66 # Vector average halfwords
  67 # CHECK: 11 df 15 f7
  68 r17 = vavgh(r21, r31)
  69 # CHECK: 11 df 35 f7
  70 r17 = vavgh(r21, r31):rnd
  71 # CHECK: 11 df 75 f7
  72 r17 = vnavgh(r31, r21)
  73
  74 # Vector subtract halfwords
  75 # CHECK: 11 df 95 f6
  76 r17 = vsubh(r31, r21)
  77 # CHECK: 11 df b5 f6
  78 r17 = vsubh(r31, r21):sat
  79 # CHECK: 11 df f5 f6
  80 r17 = vsubuh(r31, r21):sat
  81
  82 # Zero extend
  83 # CHECK: 11 c0 d5 70
  84 r17 = zxth(r21)