1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -basicaa -newgvn -enable-store-refinement -S | FileCheck %s
3 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
5 ;; Both of these tests are tests of phi nodes that end up all equivalent to each other
6 ;; Without proper leader ordering, we will end up cycling the leader between all of them and never converge.
11 ; CHECK-NEXT: br label [[BB1:%.*]]
13 ; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 1, [[BB18:%.*]] ]
14 ; CHECK-NEXT: br label [[BB2:%.*]]
16 ; CHECK-NEXT: br label [[BB4:%.*]]
18 ; CHECK-NEXT: br i1 undef, label [[BB18]], label [[BB7:%.*]]
20 ; CHECK-NEXT: br label [[BB9:%.*]]
22 ; CHECK-NEXT: br i1 undef, label [[BB2]], label [[BB11:%.*]]
24 ; CHECK-NEXT: br i1 undef, label [[BB16:%.*]], label [[BB14:%.*]]
26 ; CHECK-NEXT: br label [[BB4]]
28 ; CHECK-NEXT: br label [[BB7]]
30 ; CHECK-NEXT: br label [[BB1]]
35 bb1: ; preds = %bb18, %bb
36 %tmp = phi i32 [ 0, %bb ], [ 1, %bb18 ]
39 bb2: ; preds = %bb9, %bb1
40 %tmp3 = phi i32 [ %tmp, %bb1 ], [ %tmp8, %bb9 ]
43 bb4: ; preds = %bb14, %bb2
44 %tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp15, %bb14 ]
45 br i1 undef, label %bb18, label %bb7
47 bb7: ; preds = %bb16, %bb4
48 %tmp8 = phi i32 [ %tmp17, %bb16 ], [ %tmp5, %bb4 ]
52 br i1 undef, label %bb2, label %bb11
55 br i1 undef, label %bb16, label %bb14
58 %tmp15 = phi i32 [ %tmp8, %bb11 ]
62 %tmp17 = phi i32 [ %tmp8, %bb11 ]
72 declare void @c.d.p(i64, i8*)
74 define void @e(i32 %a0, i32 %a1, %struct.a** %p2) {
76 ; CHECK-NEXT: [[F:%.*]] = alloca i32
77 ; CHECK-NEXT: store i32 [[A0:%.*]], i32* [[F]], !g !0
78 ; CHECK-NEXT: br label [[H:%.*]]
80 ; CHECK-NEXT: call void @c.d.p(i64 8, i8* undef)
81 ; CHECK-NEXT: [[I:%.*]] = load i32, i32* [[F]]
82 ; CHECK-NEXT: [[J:%.*]] = load i32, i32* null
83 ; CHECK-NEXT: [[K:%.*]] = icmp eq i32 [[I]], [[J]]
84 ; CHECK-NEXT: br i1 [[K]], label [[L:%.*]], label [[Q:%.*]]
86 ; CHECK-NEXT: br label [[R:%.*]]
88 ; CHECK-NEXT: [[M:%.*]] = load %struct.a*, %struct.a** null
89 ; CHECK-NEXT: br label [[R]]
91 ; CHECK-NEXT: switch i32 undef, label [[N:%.*]] [
92 ; CHECK-NEXT: i32 0, label [[S:%.*]]
95 ; CHECK-NEXT: store i32 [[A1:%.*]], i32* [[F]], !g !0
96 ; CHECK-NEXT: br label [[H]]
98 ; CHECK-NEXT: [[O:%.*]] = load %struct.a*, %struct.a** [[P2:%.*]]
99 ; CHECK-NEXT: ret void
102 store i32 %a0, i32* %f, !g !0
106 call void @c.d.p(i64 8, i8* undef)
107 %i = load i32, i32* %f
108 %j = load i32, i32* null
109 %k = icmp eq i32 %i, %j
110 br i1 %k, label %l, label %q
116 %m = load %struct.a*, %struct.a** null
117 %1 = bitcast %struct.a* %m to %struct.b*
121 switch i32 undef, label %n [
126 store i32 %a1, i32* %f, !g !0
130 %o = load %struct.a*, %struct.a** %p2
131 %2 = bitcast %struct.a* %o to %struct.b*