1 ; RUN: llc -march=hexagon < %s | FileCheck %s
4 ; CHECK-DAG: r[[REG:[0-9]+]] = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}})
5 ; CHECK-DAG: jumpr r[[REG]]
7 define void @main() #0 {
9 %ret = alloca i32, align 4
13 %ret.0.load17 = load volatile i32, i32* %ret, align 4
14 switch i32 %ret.0.load17, label %label6 [
24 %ret.0.load18 = load volatile i32, i32* %ret, align 4
25 %inc = add nsw i32 %ret.0.load18, 1
26 store volatile i32 %inc, i32* %ret, align 4
30 %ret.0.load19 = load volatile i32, i32* %ret, align 4
31 %inc2 = add nsw i32 %ret.0.load19, 1
32 store volatile i32 %inc2, i32* %ret, align 4
36 %ret.0.load20 = load volatile i32, i32* %ret, align 4
37 %inc4 = add nsw i32 %ret.0.load20, 1
38 store volatile i32 %inc4, i32* %ret, align 4
42 %ret.0.load21 = load volatile i32, i32* %ret, align 4
43 %inc6 = add nsw i32 %ret.0.load21, 1
44 store volatile i32 %inc6, i32* %ret, align 4
48 %ret.0.load22 = load volatile i32, i32* %ret, align 4
49 %inc8 = add nsw i32 %ret.0.load22, 1
50 store volatile i32 %inc8, i32* %ret, align 4
54 %ret.0.load23 = load volatile i32, i32* %ret, align 4
55 %inc10 = add nsw i32 %ret.0.load23, 1
56 store volatile i32 %inc10, i32* %ret, align 4
60 store volatile i32 0, i32* %ret, align 4
64 attributes #0 = { noreturn nounwind "target-cpu"="hexagonv4" }