lib/Target/PowerPC/PPCISelLowering.h

   1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that PPC uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
  16
  17 #include "PPCInstrInfo.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/MachineMemOperand.h"
  21 #include "llvm/CodeGen/SelectionDAG.h"
  22 #include "llvm/CodeGen/SelectionDAGNodes.h"
  23 #include "llvm/CodeGen/TargetLowering.h"
  24 #include "llvm/CodeGen/ValueTypes.h"
  25 #include "llvm/IR/Attributes.h"
  26 #include "llvm/IR/CallingConv.h"
  27 #include "llvm/IR/Function.h"
  28 #include "llvm/IR/InlineAsm.h"
  29 #include "llvm/IR/Metadata.h"
  30 #include "llvm/IR/Type.h"
  31 #include "llvm/Support/MachineValueType.h"
  32 #include <utility>
  33
  34 namespace llvm {
  35
  36   namespace PPCISD {
  37
  38     // When adding a NEW PPCISD node please add it to the correct position in
  39     // the enum. The order of elements in this enum matters!
  40     // Values that are added after this entry:
  41     //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
  42     // are considered memory opcodes and are treated differently than entries
  43     // that come before it. For example, ADD or MUL should be placed before
  44     // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
  45     // after it.
  46     enum NodeType : unsigned {
  47       // Start the numbering where the builtin ops and target ops leave off.
  48       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  49
  50       /// FSEL - Traditional three-operand fsel node.
  51       ///
  52       FSEL,
  53
  54       /// FCFID - The FCFID instruction, taking an f64 operand and producing
  55       /// and f64 value containing the FP representation of the integer that
  56       /// was temporarily in the f64 operand.
  57       FCFID,
  58
  59       /// Newer FCFID[US] integer-to-floating-point conversion instructions for
  60       /// unsigned integers and single-precision outputs.
  61       FCFIDU, FCFIDS, FCFIDUS,
  62
  63       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
  64       /// operand, producing an f64 value containing the integer representation
  65       /// of that FP value.
  66       FCTIDZ, FCTIWZ,
  67
  68       /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
  69       /// unsigned integers with round toward zero.
  70       FCTIDUZ, FCTIWUZ,
  71
  72       /// Floating-point-to-interger conversion instructions
  73       FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
  74
  75       /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
  76       /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
  77       VEXTS,
  78
  79       /// SExtVElems, takes an input vector of a smaller type and sign
  80       /// extends to an output vector of a larger type.
  81       SExtVElems,
  82
  83       /// Reciprocal estimate instructions (unary FP ops).
  84       FRE, FRSQRTE,
  85
  86       // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
  87       // three v4f32 operands and producing a v4f32 result.
  88       VMADDFP, VNMSUBFP,
  89
  90       /// VPERM - The PPC VPERM Instruction.
  91       ///
  92       VPERM,
  93
  94       /// XXSPLT - The PPC VSX splat instructions
  95       ///
  96       XXSPLT,
  97
  98       /// VECINSERT - The PPC vector insert instruction
  99       ///
 100       VECINSERT,
 101
 102       /// XXREVERSE - The PPC VSX reverse instruction
 103       ///
 104       XXREVERSE,
 105
 106       /// VECSHL - The PPC vector shift left instruction
 107       ///
 108       VECSHL,
 109
 110       /// XXPERMDI - The PPC XXPERMDI instruction
 111       ///
 112       XXPERMDI,
 113
 114       /// The CMPB instruction (takes two operands of i32 or i64).
 115       CMPB,
 116
 117       /// Hi/Lo - These represent the high and low 16-bit parts of a global
 118       /// address respectively.  These nodes have two operands, the first of
 119       /// which must be a TargetGlobalAddress, and the second of which must be a
 120       /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
 121       /// though these are usually folded into other nodes.
 122       Hi, Lo,
 123
 124       /// The following two target-specific nodes are used for calls through
 125       /// function pointers in the 64-bit SVR4 ABI.
 126
 127       /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
 128       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 129       /// compute an allocation on the stack.
 130       DYNALLOC,
 131
 132       /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
 133       /// compute an offset from native SP to the address  of the most recent
 134       /// dynamic alloca.
 135       DYNAREAOFFSET,
 136
 137       /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
 138       /// at function entry, used for PIC code.
 139       GlobalBaseReg,
 140
 141       /// These nodes represent PPC shifts.
 142       ///
 143       /// For scalar types, only the last `n + 1` bits of the shift amounts
 144       /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
 145       /// for exact behaviors.
 146       ///
 147       /// For vector types, only the last n bits are used. See vsld.
 148       SRL, SRA, SHL,
 149
 150       /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
 151       /// word and shift left immediate.
 152       EXTSWSLI,
 153
 154       /// The combination of sra[wd]i and addze used to implemented signed
 155       /// integer division by a power of 2. The first operand is the dividend,
 156       /// and the second is the constant shift amount (representing the
 157       /// divisor).
 158       SRA_ADDZE,
 159
 160       /// CALL - A direct function call.
 161       /// CALL_NOP is a call with the special NOP which follows 64-bit
 162       /// SVR4 calls and 32-bit/64-bit AIX calls.
 163       CALL, CALL_NOP,
 164
 165       /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
 166       /// MTCTR instruction.
 167       MTCTR,
 168
 169       /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
 170       /// BCTRL instruction.
 171       BCTRL,
 172
 173       /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
 174       /// instruction and the TOC reload required on SVR4 PPC64.
 175       BCTRL_LOAD_TOC,
 176
 177       /// Return with a flag operand, matched by 'blr'
 178       RET_FLAG,
 179
 180       /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
 181       /// This copies the bits corresponding to the specified CRREG into the
 182       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
 183       MFOCRF,
 184
 185       /// Direct move from a VSX register to a GPR
 186       MFVSR,
 187
 188       /// Direct move from a GPR to a VSX register (algebraic)
 189       MTVSRA,
 190
 191       /// Direct move from a GPR to a VSX register (zero)
 192       MTVSRZ,
 193
 194       /// Direct move of 2 consecutive GPR to a VSX register.
 195       BUILD_FP128,
 196
 197       /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
 198       /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
 199       /// unsupported for this target.
 200       /// Merge 2 GPRs to a single SPE register.
 201       BUILD_SPE64,
 202
 203       /// Extract SPE register component, second argument is high or low.
 204       EXTRACT_SPE,
 205
 206       /// Extract a subvector from signed integer vector and convert to FP.
 207       /// It is primarily used to convert a (widened) illegal integer vector
 208       /// type to a legal floating point vector type.
 209       /// For example v2i32 -> widened to v4i32 -> v2f64
 210       SINT_VEC_TO_FP,
 211
 212       /// Extract a subvector from unsigned integer vector and convert to FP.
 213       /// As with SINT_VEC_TO_FP, used for converting illegal types.
 214       UINT_VEC_TO_FP,
 215
 216       // FIXME: Remove these once the ANDI glue bug is fixed:
 217       /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
 218       /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
 219       /// implement truncation of i32 or i64 to i1.
 220       ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
 221
 222       // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
 223       // target (returns (Lo, Hi)). It takes a chain operand.
 224       READ_TIME_BASE,
 225
 226       // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
 227       EH_SJLJ_SETJMP,
 228
 229       // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
 230       EH_SJLJ_LONGJMP,
 231
 232       /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
 233       /// instructions.  For lack of better number, we use the opcode number
 234       /// encoding for the OPC field to identify the compare.  For example, 838
 235       /// is VCMPGTSH.
 236       VCMP,
 237
 238       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
 239       /// altivec VCMP*o instructions.  For lack of better number, we use the
 240       /// opcode number encoding for the OPC field to identify the compare.  For
 241       /// example, 838 is VCMPGTSH.
 242       VCMPo,
 243
 244       /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
 245       /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
 246       /// condition register to branch on, OPC is the branch opcode to use (e.g.
 247       /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
 248       /// an optional input flag argument.
 249       COND_BRANCH,
 250
 251       /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
 252       /// loops.
 253       BDNZ, BDZ,
 254
 255       /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
 256       /// towards zero.  Used only as part of the long double-to-int
 257       /// conversion sequence.
 258       FADDRTZ,
 259
 260       /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
 261       MFFS,
 262
 263       /// TC_RETURN - A tail call return.
 264       ///   operand #0 chain
 265       ///   operand #1 callee (register or absolute)
 266       ///   operand #2 stack adjustment
 267       ///   operand #3 optional in flag
 268       TC_RETURN,
 269
 270       /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
 271       CR6SET,
 272       CR6UNSET,
 273
 274       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
 275       /// for non-position independent code on PPC32.
 276       PPC32_GOT,
 277
 278       /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
 279       /// local dynamic TLS and position indendepent code on PPC32.
 280       PPC32_PICGOT,
 281
 282       /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
 283       /// TLS model, produces an ADDIS8 instruction that adds the GOT
 284       /// base to sym\@got\@tprel\@ha.
 285       ADDIS_GOT_TPREL_HA,
 286
 287       /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
 288       /// TLS model, produces a LD instruction with base register G8RReg
 289       /// and offset sym\@got\@tprel\@l.  This completes the addition that
 290       /// finds the offset of "sym" relative to the thread pointer.
 291       LD_GOT_TPREL_L,
 292
 293       /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
 294       /// model, produces an ADD instruction that adds the contents of
 295       /// G8RReg to the thread pointer.  Symbol contains a relocation
 296       /// sym\@tls which is to be replaced by the thread pointer and
 297       /// identifies to the linker that the instruction is part of a
 298       /// TLS sequence.
 299       ADD_TLS,
 300
 301       /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
 302       /// model, produces an ADDIS8 instruction that adds the GOT base
 303       /// register to sym\@got\@tlsgd\@ha.
 304       ADDIS_TLSGD_HA,
 305
 306       /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
 307       /// model, produces an ADDI8 instruction that adds G8RReg to
 308       /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
 309       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 310       ADDI_TLSGD_L,
 311
 312       /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
 313       /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
 314       /// ADDIS_TLSGD_L_ADDR until after register assignment.
 315       GET_TLS_ADDR,
 316
 317       /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
 318       /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
 319       /// register assignment.
 320       ADDI_TLSGD_L_ADDR,
 321
 322       /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
 323       /// model, produces an ADDIS8 instruction that adds the GOT base
 324       /// register to sym\@got\@tlsld\@ha.
 325       ADDIS_TLSLD_HA,
 326
 327       /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
 328       /// model, produces an ADDI8 instruction that adds G8RReg to
 329       /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
 330       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 331       ADDI_TLSLD_L,
 332
 333       /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
 334       /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
 335       /// ADDIS_TLSLD_L_ADDR until after register assignment.
 336       GET_TLSLD_ADDR,
 337
 338       /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
 339       /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
 340       /// following register assignment.
 341       ADDI_TLSLD_L_ADDR,
 342
 343       /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
 344       /// model, produces an ADDIS8 instruction that adds X3 to
 345       /// sym\@dtprel\@ha.
 346       ADDIS_DTPREL_HA,
 347
 348       /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
 349       /// model, produces an ADDI8 instruction that adds G8RReg to
 350       /// sym\@got\@dtprel\@l.
 351       ADDI_DTPREL_L,
 352
 353       /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
 354       /// during instruction selection to optimize a BUILD_VECTOR into
 355       /// operations on splats.  This is necessary to avoid losing these
 356       /// optimizations due to constant folding.
 357       VADD_SPLAT,
 358
 359       /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
 360       /// operand identifies the operating system entry point.
 361       SC,
 362
 363       /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
 364       CLRBHRB,
 365
 366       /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
 367       /// history rolling buffer entry.
 368       MFBHRBE,
 369
 370       /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
 371       RFEBB,
 372
 373       /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
 374       /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
 375       /// or stxvd2x instruction.  The chain is necessary because the
 376       /// sequence replaces a load and needs to provide the same number
 377       /// of outputs.
 378       XXSWAPD,
 379
 380       /// An SDNode for swaps that are not associated with any loads/stores
 381       /// and thereby have no chain.
 382       SWAP_NO_CHAIN,
 383
 384       /// An SDNode for Power9 vector absolute value difference.
 385       /// operand #0 vector
 386       /// operand #1 vector
 387       /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
 388       /// the most significant bit for signed i32
 389       ///
 390       /// Power9 VABSD* instructions are designed to support unsigned integer
 391       /// vectors (byte/halfword/word), if we want to make use of them for signed
 392       /// integer vectors, we have to flip their sign bits first. To flip sign bit
 393       /// for byte/halfword integer vector would become inefficient, but for word
 394       /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
 395       /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
 396       ///               => VABSDUW((XVNEGSP a), (XVNEGSP b))
 397       VABSD,
 398
 399       /// QVFPERM = This corresponds to the QPX qvfperm instruction.
 400       QVFPERM,
 401
 402       /// QVGPCI = This corresponds to the QPX qvgpci instruction.
 403       QVGPCI,
 404
 405       /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
 406       QVALIGNI,
 407
 408       /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
 409       QVESPLATI,
 410
 411       /// QBFLT = Access the underlying QPX floating-point boolean
 412       /// representation.
 413       QBFLT,
 414
 415       /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
 416       /// lower (IDX=1) half of v4f32 to v2f64.
 417       FP_EXTEND_HALF,
 418
 419       /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
 420       /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
 421       /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
 422       /// i32.
 423       STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
 424
 425       /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
 426       /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
 427       /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
 428       /// or i32.
 429       LBRX,
 430
 431       /// STFIWX - The STFIWX instruction.  The first operand is an input token
 432       /// chain, then an f64 value to store, then an address to store it to.
 433       STFIWX,
 434
 435       /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
 436       /// load which sign-extends from a 32-bit integer value into the
 437       /// destination 64-bit register.
 438       LFIWAX,
 439
 440       /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
 441       /// load which zero-extends from a 32-bit integer value into the
 442       /// destination 64-bit register.
 443       LFIWZX,
 444
 445       /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
 446       /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
 447       /// This can be used for converting loaded integers to floating point.
 448       LXSIZX,
 449
 450       /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
 451       /// chain, then an f64 value to store, then an address to store it to,
 452       /// followed by a byte-width for the store.
 453       STXSIX,
 454
 455       /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
 456       /// Maps directly to an lxvd2x instruction that will be followed by
 457       /// an xxswapd.
 458       LXVD2X,
 459
 460       /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
 461       /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
 462       /// the vector type to load vector in big-endian element order.
 463       LOAD_VEC_BE,
 464
 465       /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
 466       /// v2f32 value into the lower half of a VSR register.
 467       LD_VSX_LH,
 468
 469       /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
 470       /// Maps directly to an stxvd2x instruction that will be preceded by
 471       /// an xxswapd.
 472       STXVD2X,
 473
 474       /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
 475       /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
 476       /// the vector type to store vector in big-endian element order.
 477       STORE_VEC_BE,
 478
 479       /// Store scalar integers from VSR.
 480       ST_VSR_SCAL_INT,
 481
 482       /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
 483       /// The 4xf32 load used for v4i1 constants.
 484       QVLFSb,
 485
 486       /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
 487       /// except they ensure that the compare input is zero-extended for
 488       /// sub-word versions because the atomic loads zero-extend.
 489       ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
 490
 491       /// GPRC = TOC_ENTRY GA, TOC
 492       /// Loads the entry for GA from the TOC, where the TOC base is given by
 493       /// the last operand.
 494       TOC_ENTRY
 495     };
 496
 497   } // end namespace PPCISD
 498
 499   /// Define some predicates that are used for node matching.
 500   namespace PPC {
 501
 502     /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
 503     /// VPKUHUM instruction.
 504     bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 505                               SelectionDAG &DAG);
 506
 507     /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
 508     /// VPKUWUM instruction.
 509     bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 510                               SelectionDAG &DAG);
 511
 512     /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
 513     /// VPKUDUM instruction.
 514     bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
 515                               SelectionDAG &DAG);
 516
 517     /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
 518     /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
 519     bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 520                             unsigned ShuffleKind, SelectionDAG &DAG);
 521
 522     /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
 523     /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
 524     bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
 525                             unsigned ShuffleKind, SelectionDAG &DAG);
 526
 527     /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
 528     /// a VMRGEW or VMRGOW instruction
 529     bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
 530                              unsigned ShuffleKind, SelectionDAG &DAG);
 531     /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
 532     /// for a XXSLDWI instruction.
 533     bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 534                               bool &Swap, bool IsLE);
 535
 536     /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
 537     /// for a XXBRH instruction.
 538     bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
 539
 540     /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
 541     /// for a XXBRW instruction.
 542     bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
 543
 544     /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
 545     /// for a XXBRD instruction.
 546     bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
 547
 548     /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
 549     /// for a XXBRQ instruction.
 550     bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
 551
 552     /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
 553     /// for a XXPERMDI instruction.
 554     bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 555                               bool &Swap, bool IsLE);
 556
 557     /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
 558     /// shift amount, otherwise return -1.
 559     int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
 560                             SelectionDAG &DAG);
 561
 562     /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
 563     /// specifies a splat of a single element that is suitable for input to
 564     /// VSPLTB/VSPLTH/VSPLTW.
 565     bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
 566
 567     /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
 568     /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
 569     /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
 570     /// vector into the other. This function will also set a couple of
 571     /// output parameters for how much the source vector needs to be shifted and
 572     /// what byte number needs to be specified for the instruction to put the
 573     /// element in the desired location of the target vector.
 574     bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
 575                          unsigned &InsertAtByte, bool &Swap, bool IsLE);
 576
 577     /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
 578     /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
 579     unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
 580
 581     /// get_VSPLTI_elt - If this is a build_vector of constants which can be
 582     /// formed by using a vspltis[bhw] instruction of the specified element
 583     /// size, return the constant being splatted.  The ByteSize field indicates
 584     /// the number of bytes of each element [124] -> [bhw].
 585     SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
 586
 587     /// If this is a qvaligni shuffle mask, return the shift
 588     /// amount, otherwise return -1.
 589     int isQVALIGNIShuffleMask(SDNode *N);
 590
 591   } // end namespace PPC
 592
 593   class PPCTargetLowering : public TargetLowering {
 594     const PPCSubtarget &Subtarget;
 595
 596   public:
 597     explicit PPCTargetLowering(const PPCTargetMachine &TM,
 598                                const PPCSubtarget &STI);
 599
 600     /// getTargetNodeName() - This method returns the name of a target specific
 601     /// DAG node.
 602     const char *getTargetNodeName(unsigned Opcode) const override;
 603
 604     bool isSelectSupported(SelectSupportKind Kind) const override {
 605       // PowerPC does not support scalar condition selects on vectors.
 606       return (Kind != SelectSupportKind::ScalarCondVectorVal);
 607     }
 608
 609     /// getPreferredVectorAction - The code we generate when vector types are
 610     /// legalized by promoting the integer element type is often much worse
 611     /// than code we generate if we widen the type for applicable vector types.
 612     /// The issue with promoting is that the vector is scalaraized, individual
 613     /// elements promoted and then the vector is rebuilt. So say we load a pair
 614     /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
 615     /// loads, moves back into VSR's (or memory ops if we don't have moves) and
 616     /// then the VPERM for the shuffle. All in all a very slow sequence.
 617     TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
 618       const override {
 619       if (VT.getScalarSizeInBits() % 8 == 0)
 620         return TypeWidenVector;
 621       return TargetLoweringBase::getPreferredVectorAction(VT);
 622     }
 623
 624     bool useSoftFloat() const override;
 625
 626     bool hasSPE() const;
 627
 628     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
 629       return MVT::i32;
 630     }
 631
 632     bool isCheapToSpeculateCttz() const override {
 633       return true;
 634     }
 635
 636     bool isCheapToSpeculateCtlz() const override {
 637       return true;
 638     }
 639
 640     bool isCtlzFast() const override {
 641       return true;
 642     }
 643
 644     bool hasAndNotCompare(SDValue) const override {
 645       return true;
 646     }
 647
 648     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 649
 650     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 651       return VT.isScalarInteger();
 652     }
 653
 654     bool supportSplitCSR(MachineFunction *MF) const override {
 655       return
 656         MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 657         MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 658     }
 659
 660     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 661
 662     void insertCopiesSplitCSR(
 663       MachineBasicBlock *Entry,
 664       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 665
 666     /// getSetCCResultType - Return the ISD::SETCC ValueType
 667     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 668                            EVT VT) const override;
 669
 670     /// Return true if target always beneficiates from combining into FMA for a
 671     /// given value type. This must typically return false on targets where FMA
 672     /// takes more cycles to execute than FADD.
 673     bool enableAggressiveFMAFusion(EVT VT) const override;
 674
 675     /// getPreIndexedAddressParts - returns true by value, base pointer and
 676     /// offset pointer and addressing mode by reference if the node's address
 677     /// can be legally represented as pre-indexed load / store address.
 678     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
 679                                    SDValue &Offset,
 680                                    ISD::MemIndexedMode &AM,
 681                                    SelectionDAG &DAG) const override;
 682
 683     /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
 684     /// it can be more efficiently represented as [r+imm].
 685     bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
 686                                 SelectionDAG &DAG) const;
 687
 688     /// SelectAddressRegReg - Given the specified addressed, check to see if it
 689     /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
 690     /// is non-zero, only accept displacement which is not suitable for [r+imm].
 691     /// Returns false if it can be represented by [r+imm], which are preferred.
 692     bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
 693                              SelectionDAG &DAG,
 694                              unsigned EncodingAlignment = 0) const;
 695
 696     /// SelectAddressRegImm - Returns true if the address N can be represented
 697     /// by a base register plus a signed 16-bit displacement [r+imm], and if it
 698     /// is not better represented as reg+reg. If \p EncodingAlignment is
 699     /// non-zero, only accept displacements suitable for instruction encoding
 700     /// requirement, i.e. multiples of 4 for DS form.
 701     bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
 702                              SelectionDAG &DAG,
 703                              unsigned EncodingAlignment) const;
 704
 705     /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
 706     /// represented as an indexed [r+r] operation.
 707     bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
 708                                  SelectionDAG &DAG) const;
 709
 710     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 711
 712     /// LowerOperation - Provide custom lowering hooks for some operations.
 713     ///
 714     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 715
 716     /// ReplaceNodeResults - Replace the results of node with an illegal result
 717     /// type with new values built out of custom code.
 718     ///
 719     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 720                             SelectionDAG &DAG) const override;
 721
 722     SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 723     SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
 724
 725     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 726
 727     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 728                           SmallVectorImpl<SDNode *> &Created) const override;
 729
 730     unsigned getRegisterByName(const char* RegName, EVT VT,
 731                                SelectionDAG &DAG) const override;
 732
 733     void computeKnownBitsForTargetNode(const SDValue Op,
 734                                        KnownBits &Known,
 735                                        const APInt &DemandedElts,
 736                                        const SelectionDAG &DAG,
 737                                        unsigned Depth = 0) const override;
 738
 739     llvm::Align getPrefLoopAlignment(MachineLoop *ML) const override;
 740
 741     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 742       return true;
 743     }
 744
 745     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 746                                   AtomicOrdering Ord) const override;
 747     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 748                                    AtomicOrdering Ord) const override;
 749
 750     MachineBasicBlock *
 751     EmitInstrWithCustomInserter(MachineInstr &MI,
 752                                 MachineBasicBlock *MBB) const override;
 753     MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
 754                                         MachineBasicBlock *MBB,
 755                                         unsigned AtomicSize,
 756                                         unsigned BinOpcode,
 757                                         unsigned CmpOpcode = 0,
 758                                         unsigned CmpPred = 0) const;
 759     MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
 760                                                 MachineBasicBlock *MBB,
 761                                                 bool is8bit,
 762                                                 unsigned Opcode,
 763                                                 unsigned CmpOpcode = 0,
 764                                                 unsigned CmpPred = 0) const;
 765
 766     MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
 767                                         MachineBasicBlock *MBB) const;
 768
 769     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
 770                                          MachineBasicBlock *MBB) const;
 771
 772     ConstraintType getConstraintType(StringRef Constraint) const override;
 773
 774     /// Examine constraint string and operand type and determine a weight value.
 775     /// The operand object must already have been set up with the operand type.
 776     ConstraintWeight getSingleConstraintMatchWeight(
 777       AsmOperandInfo &info, const char *constraint) const override;
 778
 779     std::pair<unsigned, const TargetRegisterClass *>
 780     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 781                                  StringRef Constraint, MVT VT) const override;
 782
 783     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 784     /// function arguments in the caller parameter area.  This is the actual
 785     /// alignment, not its logarithm.
 786     unsigned getByValTypeAlignment(Type *Ty,
 787                                    const DataLayout &DL) const override;
 788
 789     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 790     /// vector.  If it is invalid, don't add anything to Ops.
 791     void LowerAsmOperandForConstraint(SDValue Op,
 792                                       std::string &Constraint,
 793                                       std::vector<SDValue> &Ops,
 794                                       SelectionDAG &DAG) const override;
 795
 796     unsigned
 797     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 798       if (ConstraintCode == "es")
 799         return InlineAsm::Constraint_es;
 800       else if (ConstraintCode == "o")
 801         return InlineAsm::Constraint_o;
 802       else if (ConstraintCode == "Q")
 803         return InlineAsm::Constraint_Q;
 804       else if (ConstraintCode == "Z")
 805         return InlineAsm::Constraint_Z;
 806       else if (ConstraintCode == "Zy")
 807         return InlineAsm::Constraint_Zy;
 808       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 809     }
 810
 811     /// isLegalAddressingMode - Return true if the addressing mode represented
 812     /// by AM is legal for this target, for a load/store of the specified type.
 813     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 814                                Type *Ty, unsigned AS,
 815                                Instruction *I = nullptr) const override;
 816
 817     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 818     /// icmp immediate, that is the target has icmp instructions which can
 819     /// compare a register against the immediate without having to materialize
 820     /// the immediate into a register.
 821     bool isLegalICmpImmediate(int64_t Imm) const override;
 822
 823     /// isLegalAddImmediate - Return true if the specified immediate is legal
 824     /// add immediate, that is the target has add instructions which can
 825     /// add a register and the immediate without having to materialize
 826     /// the immediate into a register.
 827     bool isLegalAddImmediate(int64_t Imm) const override;
 828
 829     /// isTruncateFree - Return true if it's free to truncate a value of
 830     /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
 831     /// register X1 to i32 by referencing its sub-register R1.
 832     bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
 833     bool isTruncateFree(EVT VT1, EVT VT2) const override;
 834
 835     bool isZExtFree(SDValue Val, EVT VT2) const override;
 836
 837     bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
 838
 839     /// Returns true if it is beneficial to convert a load of a constant
 840     /// to just the constant itself.
 841     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 842                                            Type *Ty) const override;
 843
 844     bool convertSelectOfConstantsToMath(EVT VT) const override {
 845       return true;
 846     }
 847
 848     bool isDesirableToTransformToIntegerOp(unsigned Opc,
 849                                            EVT VT) const override {
 850       // Only handle float load/store pair because float(fpr) load/store
 851       // instruction has more cycles than integer(gpr) load/store in PPC.
 852       if (Opc != ISD::LOAD && Opc != ISD::STORE)
 853         return false;
 854       if (VT != MVT::f32 && VT != MVT::f64)
 855         return false;
 856
 857       return true;
 858     }
 859
 860     // Returns true if the address of the global is stored in TOC entry.
 861     bool isAccessedAsGotIndirect(SDValue N) const;
 862
 863     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 864
 865     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 866                             const CallInst &I,
 867                             MachineFunction &MF,
 868                             unsigned Intrinsic) const override;
 869
 870     /// getOptimalMemOpType - Returns the target specific optimal type for load
 871     /// and store operations as a result of memset, memcpy, and memmove
 872     /// lowering. If DstAlign is zero that means it's safe to destination
 873     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
 874     /// means there isn't a need to check it against alignment requirement,
 875     /// probably because the source does not need to be loaded. If 'IsMemset' is
 876     /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
 877     /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
 878     /// source is constant so it does not need to be loaded.
 879     /// It returns EVT::Other if the type should be determined using generic
 880     /// target-independent logic.
 881     EVT
 882     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
 883                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
 884                         const AttributeList &FuncAttributes) const override;
 885
 886     /// Is unaligned memory access allowed for the given type, and is it fast
 887     /// relative to software emulation.
 888     bool allowsMisalignedMemoryAccesses(
 889         EVT VT, unsigned AddrSpace, unsigned Align = 1,
 890         MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
 891         bool *Fast = nullptr) const override;
 892
 893     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 894     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 895     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 896     /// expanded to fmul + fadd.
 897     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 898
 899     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 900
 901     // Should we expand the build vector with shuffles?
 902     bool
 903     shouldExpandBuildVectorWithShuffles(EVT VT,
 904                                         unsigned DefinedValues) const override;
 905
 906     /// createFastISel - This method returns a target-specific FastISel object,
 907     /// or null if the target does not support "fast" instruction selection.
 908     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
 909                              const TargetLibraryInfo *LibInfo) const override;
 910
 911     /// Returns true if an argument of type Ty needs to be passed in a
 912     /// contiguous block of registers in calling convention CallConv.
 913     bool functionArgumentNeedsConsecutiveRegisters(
 914       Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
 915       // We support any array type as "consecutive" block in the parameter
 916       // save area.  The element type defines the alignment requirement and
 917       // whether the argument should go in GPRs, FPRs, or VRs if available.
 918       //
 919       // Note that clang uses this capability both to implement the ELFv2
 920       // homogeneous float/vector aggregate ABI, and to avoid having to use
 921       // "byval" when passing aggregates that might fully fit in registers.
 922       return Ty->isArrayTy();
 923     }
 924
 925     /// If a physical register, this returns the register that receives the
 926     /// exception address on entry to an EH pad.
 927     unsigned
 928     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 929
 930     /// If a physical register, this returns the register that receives the
 931     /// exception typeid on entry to a landing pad.
 932     unsigned
 933     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 934
 935     /// Override to support customized stack guard loading.
 936     bool useLoadStackGuardNode() const override;
 937     void insertSSPDeclarations(Module &M) const override;
 938
 939     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 940                       bool ForCodeSize) const override;
 941
 942     unsigned getJumpTableEncoding() const override;
 943     bool isJumpTableRelative() const override;
 944     SDValue getPICJumpTableRelocBase(SDValue Table,
 945                                      SelectionDAG &DAG) const override;
 946     const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
 947                                                unsigned JTI,
 948                                                MCContext &Ctx) const override;
 949
 950   private:
 951     struct ReuseLoadInfo {
 952       SDValue Ptr;
 953       SDValue Chain;
 954       SDValue ResChain;
 955       MachinePointerInfo MPI;
 956       bool IsDereferenceable = false;
 957       bool IsInvariant = false;
 958       unsigned Alignment = 0;
 959       AAMDNodes AAInfo;
 960       const MDNode *Ranges = nullptr;
 961
 962       ReuseLoadInfo() = default;
 963
 964       MachineMemOperand::Flags MMOFlags() const {
 965         MachineMemOperand::Flags F = MachineMemOperand::MONone;
 966         if (IsDereferenceable)
 967           F |= MachineMemOperand::MODereferenceable;
 968         if (IsInvariant)
 969           F |= MachineMemOperand::MOInvariant;
 970         return F;
 971       }
 972     };
 973
 974     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 975       // Addrspacecasts are always noops.
 976       return true;
 977     }
 978
 979     bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
 980                              SelectionDAG &DAG,
 981                              ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
 982     void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
 983                          SelectionDAG &DAG) const;
 984
 985     void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
 986                                 SelectionDAG &DAG, const SDLoc &dl) const;
 987     SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
 988                                      const SDLoc &dl) const;
 989
 990     bool directMoveIsProfitable(const SDValue &Op) const;
 991     SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
 992                                      const SDLoc &dl) const;
 993
 994     SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
 995                                  const SDLoc &dl) const;
 996
 997     SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
 998
 999     SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1000     SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1001
1002     bool
1003     IsEligibleForTailCallOptimization(SDValue Callee,
1004                                       CallingConv::ID CalleeCC,
1005                                       bool isVarArg,
1006                                       const SmallVectorImpl<ISD::InputArg> &Ins,
1007                                       SelectionDAG& DAG) const;
1008
1009     bool
1010     IsEligibleForTailCallOptimization_64SVR4(
1011                                     SDValue Callee,
1012                                     CallingConv::ID CalleeCC,
1013                                     ImmutableCallSite CS,
1014                                     bool isVarArg,
1015                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
1016                                     const SmallVectorImpl<ISD::InputArg> &Ins,
1017                                     SelectionDAG& DAG) const;
1018
1019     SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1020                                          SDValue Chain, SDValue &LROpOut,
1021                                          SDValue &FPOpOut,
1022                                          const SDLoc &dl) const;
1023
1024     SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1025
1026     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1027     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1028     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1029     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1030     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1031     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1032     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1033     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1034     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1035     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1036     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1037     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1038     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1039     SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1040     SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1041     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1042     SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1043     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1044     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1045     SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1046     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1047     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1048                            const SDLoc &dl) const;
1049     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1050     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1051     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1052     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1053     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1054     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1055     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1056     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1057     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1058     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1059     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1060     SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
1061     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1062     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1063     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1064     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
1065     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1066     SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1067     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1068
1069     SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1070     SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1071
1072     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1073                             CallingConv::ID CallConv, bool isVarArg,
1074                             const SmallVectorImpl<ISD::InputArg> &Ins,
1075                             const SDLoc &dl, SelectionDAG &DAG,
1076                             SmallVectorImpl<SDValue> &InVals) const;
1077     SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
1078                        bool isTailCall, bool isVarArg, bool isPatchPoint,
1079                        bool hasNest, SelectionDAG &DAG,
1080                        SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1081                        SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1082                        SDValue &Callee, int SPDiff, unsigned NumBytes,
1083                        const SmallVectorImpl<ISD::InputArg> &Ins,
1084                        SmallVectorImpl<SDValue> &InVals,
1085                        ImmutableCallSite CS) const;
1086
1087     SDValue
1088     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1089                          const SmallVectorImpl<ISD::InputArg> &Ins,
1090                          const SDLoc &dl, SelectionDAG &DAG,
1091                          SmallVectorImpl<SDValue> &InVals) const override;
1092
1093     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1094                       SmallVectorImpl<SDValue> &InVals) const override;
1095
1096     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1097                         bool isVarArg,
1098                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1099                         LLVMContext &Context) const override;
1100
1101     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1102                         const SmallVectorImpl<ISD::OutputArg> &Outs,
1103                         const SmallVectorImpl<SDValue> &OutVals,
1104                         const SDLoc &dl, SelectionDAG &DAG) const override;
1105
1106     SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1107                               SelectionDAG &DAG, SDValue ArgVal,
1108                               const SDLoc &dl) const;
1109
1110     SDValue LowerFormalArguments_Darwin(
1111         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1112         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1113         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1114     SDValue LowerFormalArguments_64SVR4(
1115         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1116         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1117         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1118     SDValue LowerFormalArguments_32SVR4(
1119         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1120         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1121         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1122
1123     SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1124                                        SDValue CallSeqStart,
1125                                        ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1126                                        const SDLoc &dl) const;
1127
1128     SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1129                              CallingConv::ID CallConv, bool isVarArg,
1130                              bool isTailCall, bool isPatchPoint,
1131                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1132                              const SmallVectorImpl<SDValue> &OutVals,
1133                              const SmallVectorImpl<ISD::InputArg> &Ins,
1134                              const SDLoc &dl, SelectionDAG &DAG,
1135                              SmallVectorImpl<SDValue> &InVals,
1136                              ImmutableCallSite CS) const;
1137     SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1138                              CallingConv::ID CallConv, bool isVarArg,
1139                              bool isTailCall, bool isPatchPoint,
1140                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1141                              const SmallVectorImpl<SDValue> &OutVals,
1142                              const SmallVectorImpl<ISD::InputArg> &Ins,
1143                              const SDLoc &dl, SelectionDAG &DAG,
1144                              SmallVectorImpl<SDValue> &InVals,
1145                              ImmutableCallSite CS) const;
1146     SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1147                              CallingConv::ID CallConv, bool isVarArg,
1148                              bool isTailCall, bool isPatchPoint,
1149                              const SmallVectorImpl<ISD::OutputArg> &Outs,
1150                              const SmallVectorImpl<SDValue> &OutVals,
1151                              const SmallVectorImpl<ISD::InputArg> &Ins,
1152                              const SDLoc &dl, SelectionDAG &DAG,
1153                              SmallVectorImpl<SDValue> &InVals,
1154                              ImmutableCallSite CS) const;
1155     SDValue LowerCall_AIX(SDValue Chain, SDValue Callee,
1156                           CallingConv::ID CallConv, bool isVarArg,
1157                           bool isTailCall, bool isPatchPoint,
1158                           const SmallVectorImpl<ISD::OutputArg> &Outs,
1159                           const SmallVectorImpl<SDValue> &OutVals,
1160                           const SmallVectorImpl<ISD::InputArg> &Ins,
1161                           const SDLoc &dl, SelectionDAG &DAG,
1162                           SmallVectorImpl<SDValue> &InVals,
1163                           ImmutableCallSite CS) const;
1164
1165     SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1166     SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1167     SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1168
1169     SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1170     SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1171     SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1172     SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1173     SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1174     SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1175     SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1176     SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1177     SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1178     SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1179     SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1180     SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1181     SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1182     SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1183     SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1184                                  DAGCombinerInfo &DCI) const;
1185
1186     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1187     /// SETCC with integer subtraction when (1) there is a legal way of doing it
1188     /// (2) keeping the result of comparison in GPR has performance benefit.
1189     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1190
1191     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1192                             int &RefinementSteps, bool &UseOneConstNR,
1193                             bool Reciprocal) const override;
1194     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1195                              int &RefinementSteps) const override;
1196     unsigned combineRepeatedFPDivisors() const override;
1197
1198     SDValue
1199     combineElementTruncationToVectorTruncation(SDNode *N,
1200                                                DAGCombinerInfo &DCI) const;
1201
1202     /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1203     /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1204     /// essentially any shuffle of v8i16 vectors that just inserts one element
1205     /// from one vector into the other.
1206     SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1207
1208     /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1209     /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1210     /// essentially v16i8 vector version of VINSERTH.
1211     SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1212
1213     // Return whether the call instruction can potentially be optimized to a
1214     // tail call. This will cause the optimizers to attempt to move, or
1215     // duplicate return instructions to help enable tail call optimizations.
1216     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1217     bool hasBitPreservingFPLogic(EVT VT) const override;
1218     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1219   }; // end class PPCTargetLowering
1220
1221   namespace PPC {
1222
1223     FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1224                              const TargetLibraryInfo *LibInfo);
1225
1226   } // end namespace PPC
1227
1228   bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1229   bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1230
1231 } // end namespace llvm
1232
1233 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H