lib/Target/AMDGPU/AMDGPU.td

   1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===------------------------------------------------------------===//
   9
  10 include "llvm/TableGen/SearchableTable.td"
  11 include "llvm/Target/Target.td"
  12 include "AMDGPUFeatures.td"
  13
  14 //===------------------------------------------------------------===//
  15 // Subtarget Features (device properties)
  16 //===------------------------------------------------------------===//
  17
  18 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
  19   "FastFMAF32",
  20   "true",
  21   "Assuming f32 fma is at least as fast as mul + add"
  22 >;
  23
  24 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
  25   "MIMG_R128",
  26   "true",
  27   "Support 128-bit texture resources"
  28 >;
  29
  30 def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
  31   "HalfRate64Ops",
  32   "true",
  33   "Most fp64 instructions are half rate instead of quarter"
  34 >;
  35
  36 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  37   "FlatAddressSpace",
  38   "true",
  39   "Support flat address space"
  40 >;
  41
  42 def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
  43   "FlatInstOffsets",
  44   "true",
  45   "Flat instructions have immediate offset addressing mode"
  46 >;
  47
  48 def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
  49   "FlatGlobalInsts",
  50   "true",
  51   "Have global_* flat memory instructions"
  52 >;
  53
  54 def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
  55   "FlatScratchInsts",
  56   "true",
  57   "Have scratch_* flat memory instructions"
  58 >;
  59
  60 def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
  61   "AddNoCarryInsts",
  62   "true",
  63   "Have VALU add/sub instructions without carry out"
  64 >;
  65
  66 def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
  67   "UnalignedBufferAccess",
  68   "true",
  69   "Support unaligned global loads and stores"
  70 >;
  71
  72 def FeatureTrapHandler: SubtargetFeature<"trap-handler",
  73   "TrapHandler",
  74   "true",
  75   "Trap handler support"
  76 >;
  77
  78 def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
  79   "UnalignedScratchAccess",
  80   "true",
  81   "Support unaligned scratch loads and stores"
  82 >;
  83
  84 def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
  85   "HasApertureRegs",
  86   "true",
  87   "Has Memory Aperture Base and Size Registers"
  88 >;
  89
  90 def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
  91   "HasMadMixInsts",
  92   "true",
  93   "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
  94 >;
  95
  96 def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
  97   "HasFmaMixInsts",
  98   "true",
  99   "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
 100 >;
 101
 102 // XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
 103 // XNACK. The current default kernel driver setting is:
 104 // - graphics ring: XNACK disabled
 105 // - compute ring: XNACK enabled
 106 //
 107 // If XNACK is enabled, the VMEM latency can be worse.
 108 // If XNACK is disabled, the 2 SGPRs can be used for general purposes.
 109 def FeatureXNACK : SubtargetFeature<"xnack",
 110   "EnableXNACK",
 111   "true",
 112   "Enable XNACK support"
 113 >;
 114
 115 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
 116   "SGPRInitBug",
 117   "true",
 118   "VI SGPR initialization bug requiring a fixed SGPR allocation size"
 119 >;
 120
 121 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
 122   "ldsbankcount"#Value,
 123   "LDSBankCount",
 124   !cast<string>(Value),
 125   "The number of LDS banks per compute unit."
 126 >;
 127
 128 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
 129 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
 130
 131 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
 132   "GCN3Encoding",
 133   "true",
 134   "Encoding format for VI"
 135 >;
 136
 137 def FeatureCIInsts : SubtargetFeature<"ci-insts",
 138   "CIInsts",
 139   "true",
 140   "Additional instructions for CI+"
 141 >;
 142
 143 def FeatureVIInsts : SubtargetFeature<"vi-insts",
 144   "VIInsts",
 145   "true",
 146   "Additional instructions for VI+"
 147 >;
 148
 149 def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
 150   "GFX9Insts",
 151   "true",
 152   "Additional instructions for GFX9+"
 153 >;
 154
 155 def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
 156   "HasSMemRealTime",
 157   "true",
 158   "Has s_memrealtime instruction"
 159 >;
 160
 161 def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
 162   "HasInv2PiInlineImm",
 163   "true",
 164   "Has 1 / (2 * pi) as inline immediate"
 165 >;
 166
 167 def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
 168   "Has16BitInsts",
 169   "true",
 170   "Has i16/f16 instructions"
 171 >;
 172
 173 def FeatureVOP3P : SubtargetFeature<"vop3p",
 174   "HasVOP3PInsts",
 175   "true",
 176   "Has VOP3P packed instructions"
 177 >;
 178
 179 def FeatureMovrel : SubtargetFeature<"movrel",
 180   "HasMovrel",
 181   "true",
 182   "Has v_movrel*_b32 instructions"
 183 >;
 184
 185 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
 186   "HasVGPRIndexMode",
 187   "true",
 188   "Has VGPR mode register indexing"
 189 >;
 190
 191 def FeatureScalarStores : SubtargetFeature<"scalar-stores",
 192   "HasScalarStores",
 193   "true",
 194   "Has store scalar memory instructions"
 195 >;
 196
 197 def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
 198   "HasScalarAtomics",
 199   "true",
 200   "Has atomic scalar memory instructions"
 201 >;
 202
 203 def FeatureSDWA : SubtargetFeature<"sdwa",
 204   "HasSDWA",
 205   "true",
 206   "Support SDWA (Sub-DWORD Addressing) extension"
 207 >;
 208
 209 def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
 210   "HasSDWAOmod",
 211   "true",
 212   "Support OMod with SDWA (Sub-DWORD Addressing) extension"
 213 >;
 214
 215 def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
 216   "HasSDWAScalar",
 217   "true",
 218   "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
 219 >;
 220
 221 def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
 222   "HasSDWASdst",
 223   "true",
 224   "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
 225 >;
 226
 227 def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
 228   "HasSDWAMac",
 229   "true",
 230   "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
 231 >;
 232
 233 def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
 234   "HasSDWAOutModsVOPC",
 235   "true",
 236   "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
 237 >;
 238
 239 def FeatureDPP : SubtargetFeature<"dpp",
 240   "HasDPP",
 241   "true",
 242   "Support DPP (Data Parallel Primitives) extension"
 243 >;
 244
 245 def FeatureR128A16 : SubtargetFeature<"r128-a16",
 246   "HasR128A16",
 247   "true",
 248   "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
 249 >;
 250
 251 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
 252   "HasIntClamp",
 253   "true",
 254   "Support clamp for integer destination"
 255 >;
 256
 257 def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
 258   "HasUnpackedD16VMem",
 259   "true",
 260   "Has unpacked d16 vmem instructions"
 261 >;
 262
 263 def FeatureDLInsts : SubtargetFeature<"dl-insts",
 264   "HasDLInsts",
 265   "true",
 266   "Has deep learning instructions"
 267 >;
 268
 269 def FeatureD16PreservesUnusedBits : SubtargetFeature<
 270   "d16-preserves-unused-bits",
 271   "D16PreservesUnusedBits",
 272   "true",
 273   "If present, then instructions defined by HasD16LoadStore predicate preserve "
 274   "unused bits. Otherwise instructions defined by HasD16LoadStore predicate "
 275   "zero unused bits."
 276 >;
 277
 278 //===------------------------------------------------------------===//
 279 // Subtarget Features (options and debugging)
 280 //===------------------------------------------------------------===//
 281
 282 // Denormal handling for fp64 and fp16 is controlled by the same
 283 // config register when fp16 supported.
 284 // TODO: Do we need a separate f16 setting when not legal?
 285 def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
 286   "FP64FP16Denormals",
 287   "true",
 288   "Enable double and half precision denormal handling",
 289   [FeatureFP64]
 290 >;
 291
 292 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
 293   "FP64FP16Denormals",
 294   "true",
 295   "Enable double and half precision denormal handling",
 296   [FeatureFP64, FeatureFP64FP16Denormals]
 297 >;
 298
 299 def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
 300   "FP64FP16Denormals",
 301   "true",
 302   "Enable half precision denormal handling",
 303   [FeatureFP64FP16Denormals]
 304 >;
 305
 306 def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
 307   "FPExceptions",
 308   "true",
 309   "Enable floating point exceptions"
 310 >;
 311
 312 class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
 313   "max-private-element-size-"#size,
 314   "MaxPrivateElementSize",
 315   !cast<string>(size),
 316   "Maximum private access size may be "#size
 317 >;
 318
 319 def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
 320 def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
 321 def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
 322
 323 def FeatureEnableHugePrivateBuffer : SubtargetFeature<
 324   "huge-private-buffer",
 325   "EnableHugePrivateBuffer",
 326   "true",
 327   "Enable private/scratch buffer sizes greater than 128 GB"
 328 >;
 329
 330 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
 331   "EnableVGPRSpilling",
 332   "true",
 333   "Enable spilling of VGPRs to scratch memory"
 334 >;
 335
 336 def FeatureDumpCode : SubtargetFeature <"DumpCode",
 337   "DumpCode",
 338   "true",
 339   "Dump MachineInstrs in the CodeEmitter"
 340 >;
 341
 342 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
 343   "DumpCode",
 344   "true",
 345   "Dump MachineInstrs in the CodeEmitter"
 346 >;
 347
 348 // XXX - This should probably be removed once enabled by default
 349 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
 350   "EnableLoadStoreOpt",
 351   "true",
 352   "Enable SI load/store optimizer pass"
 353 >;
 354
 355 // Performance debugging feature. Allow using DS instruction immediate
 356 // offsets even if the base pointer can't be proven to be base. On SI,
 357 // base pointer values that won't give the same result as a 16-bit add
 358 // are not safe to fold, but this will override the conservative test
 359 // for the base pointer.
 360 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
 361   "unsafe-ds-offset-folding",
 362   "EnableUnsafeDSOffsetFolding",
 363   "true",
 364   "Force using DS instruction immediate offsets on SI"
 365 >;
 366
 367 def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
 368   "EnableSIScheduler",
 369   "true",
 370   "Enable SI Machine Scheduler"
 371 >;
 372
 373 def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
 374   "EnableDS128",
 375   "true",
 376   "Use ds_{read|write}_b128"
 377 >;
 378
 379 // Unless +-flat-for-global is specified, turn on FlatForGlobal for
 380 // all OS-es on VI and newer hardware to avoid assertion failures due
 381 // to missing ADDR64 variants of MUBUF instructions.
 382 // FIXME: moveToVALU should be able to handle converting addr64 MUBUF
 383 // instructions.
 384
 385 def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
 386   "FlatForGlobal",
 387   "true",
 388   "Force to generate flat instruction for global"
 389 >;
 390
 391 def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
 392   "auto-waitcnt-before-barrier",
 393   "AutoWaitcntBeforeBarrier",
 394   "true",
 395   "Hardware automatically inserts waitcnt before barrier"
 396 >;
 397
 398 def FeatureCodeObjectV3 : SubtargetFeature <
 399   "code-object-v3",
 400   "CodeObjectV3",
 401   "true",
 402   "Generate code object version 3"
 403 >;
 404
 405 def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
 406   "HasTrigReducedRange",
 407   "true",
 408   "Requires use of fract on arguments to trig instructions"
 409 >;
 410
 411 // Dummy feature used to disable assembler instructions.
 412 def FeatureDisable : SubtargetFeature<"",
 413   "FeatureDisable","true",
 414   "Dummy feature to disable assembler instructions"
 415 >;
 416
 417 def FeatureGCN : SubtargetFeature<"gcn",
 418   "IsGCN",
 419   "true",
 420   "GCN or newer GPU"
 421 >;
 422
 423 class GCNSubtargetFeatureGeneration <string Value,
 424                                   list<SubtargetFeature> Implies> :
 425         SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
 426
 427 def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 428   [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
 429   FeatureWavefrontSize64, FeatureGCN,
 430   FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
 431 >;
 432
 433 def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
 434   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 435   FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
 436   FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
 437 >;
 438
 439 def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 440   [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
 441    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 442    FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
 443    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
 444    FeatureScalarStores, FeatureInv2PiInlineImm,
 445    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
 446    FeatureIntClamp, FeatureTrigReducedRange
 447   ]
 448 >;
 449
 450 def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
 451   [FeatureFP64, FeatureLocalMemorySize65536,
 452    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
 453    FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
 454    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
 455    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
 456    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
 457    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
 458    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
 459    FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
 460   ]
 461 >;
 462
 463 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
 464                                   list<SubtargetFeature> Implies>
 465                                  : SubtargetFeature <
 466   "isaver"#Major#"."#Minor#"."#Stepping,
 467   "IsaVersion",
 468   "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
 469   "Instruction set version number",
 470   Implies
 471 >;
 472
 473 def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
 474   [FeatureSouthernIslands,
 475    FeatureFastFMAF32,
 476    HalfRate64Ops,
 477    FeatureLDSBankCount32]>;
 478
 479 def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
 480   [FeatureSouthernIslands,
 481    FeatureLDSBankCount32]>;
 482
 483 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
 484   [FeatureSeaIslands,
 485    FeatureLDSBankCount32]>;
 486
 487 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
 488   [FeatureSeaIslands,
 489    HalfRate64Ops,
 490    FeatureLDSBankCount32,
 491    FeatureFastFMAF32]>;
 492
 493 def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
 494   [FeatureSeaIslands,
 495    FeatureLDSBankCount16,
 496    FeatureFastFMAF32]>;
 497
 498 def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
 499   [FeatureSeaIslands,
 500    FeatureLDSBankCount16]>;
 501
 502 def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
 503   [FeatureSeaIslands,
 504    FeatureLDSBankCount32]>;
 505
 506 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
 507   [FeatureVolcanicIslands,
 508    FeatureFastFMAF32,
 509    HalfRate64Ops,
 510    FeatureLDSBankCount32,
 511    FeatureXNACK,
 512    FeatureUnpackedD16VMem]>;
 513
 514 def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
 515   [FeatureVolcanicIslands,
 516    FeatureLDSBankCount32,
 517    FeatureSGPRInitBug,
 518    FeatureUnpackedD16VMem]>;
 519
 520 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
 521   [FeatureVolcanicIslands,
 522    FeatureLDSBankCount32,
 523    FeatureUnpackedD16VMem]>;
 524
 525 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
 526   [FeatureVolcanicIslands,
 527    FeatureLDSBankCount16,
 528    FeatureXNACK]>;
 529
 530 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
 531   [FeatureGFX9,
 532    FeatureMadMixInsts,
 533    FeatureLDSBankCount32,
 534    FeatureD16PreservesUnusedBits]>;
 535
 536 def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
 537   [FeatureGFX9,
 538    FeatureMadMixInsts,
 539    FeatureLDSBankCount32,
 540    FeatureXNACK,
 541    FeatureD16PreservesUnusedBits]>;
 542
 543 def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
 544   [FeatureGFX9,
 545    FeatureLDSBankCount32,
 546    FeatureFmaMixInsts,
 547    FeatureD16PreservesUnusedBits]>;
 548
 549 def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
 550   [FeatureGFX9,
 551    HalfRate64Ops,
 552    FeatureFmaMixInsts,
 553    FeatureLDSBankCount32,
 554    FeatureDLInsts]>;
 555
 556 //===----------------------------------------------------------------------===//
 557 // Debugger related subtarget features.
 558 //===----------------------------------------------------------------------===//
 559
 560 def FeatureDebuggerInsertNops : SubtargetFeature<
 561   "amdgpu-debugger-insert-nops",
 562   "DebuggerInsertNops",
 563   "true",
 564   "Insert one nop instruction for each high level source statement"
 565 >;
 566
 567 def FeatureDebuggerEmitPrologue : SubtargetFeature<
 568   "amdgpu-debugger-emit-prologue",
 569   "DebuggerEmitPrologue",
 570   "true",
 571   "Emit debugger prologue"
 572 >;
 573
 574 //===----------------------------------------------------------------------===//
 575
 576 def AMDGPUInstrInfo : InstrInfo {
 577   let guessInstructionProperties = 1;
 578   let noNamedPositionallyEncodedOperands = 1;
 579 }
 580
 581 def AMDGPUAsmParser : AsmParser {
 582   // Some of the R600 registers have the same name, so this crashes.
 583   // For example T0_XYZW and T0_XY both have the asm name T0.
 584   let ShouldEmitMatchRegisterName = 0;
 585 }
 586
 587 def AMDGPUAsmWriter : AsmWriter {
 588   int PassSubtarget = 1;
 589 }
 590
 591 def AMDGPUAsmVariants {
 592   string Default = "Default";
 593   int Default_ID = 0;
 594   string VOP3 = "VOP3";
 595   int VOP3_ID = 1;
 596   string SDWA = "SDWA";
 597   int SDWA_ID = 2;
 598   string SDWA9 = "SDWA9";
 599   int SDWA9_ID = 3;
 600   string DPP = "DPP";
 601   int DPP_ID = 4;
 602   string Disable = "Disable";
 603   int Disable_ID = 5;
 604 }
 605
 606 def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
 607   let Variant = AMDGPUAsmVariants.Default_ID;
 608   let Name = AMDGPUAsmVariants.Default;
 609 }
 610
 611 def VOP3AsmParserVariant : AsmParserVariant {
 612   let Variant = AMDGPUAsmVariants.VOP3_ID;
 613   let Name = AMDGPUAsmVariants.VOP3;
 614 }
 615
 616 def SDWAAsmParserVariant : AsmParserVariant {
 617   let Variant = AMDGPUAsmVariants.SDWA_ID;
 618   let Name = AMDGPUAsmVariants.SDWA;
 619 }
 620
 621 def SDWA9AsmParserVariant : AsmParserVariant {
 622   let Variant = AMDGPUAsmVariants.SDWA9_ID;
 623   let Name = AMDGPUAsmVariants.SDWA9;
 624 }
 625
 626
 627 def DPPAsmParserVariant : AsmParserVariant {
 628   let Variant = AMDGPUAsmVariants.DPP_ID;
 629   let Name = AMDGPUAsmVariants.DPP;
 630 }
 631
 632 def AMDGPU : Target {
 633   // Pull in Instruction Info:
 634   let InstructionSet = AMDGPUInstrInfo;
 635   let AssemblyParsers = [AMDGPUAsmParser];
 636   let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
 637                                 VOP3AsmParserVariant,
 638                                 SDWAAsmParserVariant,
 639                                 SDWA9AsmParserVariant,
 640                                 DPPAsmParserVariant];
 641   let AssemblyWriters = [AMDGPUAsmWriter];
 642   let AllowRegisterRenaming = 1;
 643 }
 644
 645 // Dummy Instruction itineraries for pseudo instructions
 646 def ALU_NULL : FuncUnit;
 647 def NullALU : InstrItinClass;
 648
 649 //===----------------------------------------------------------------------===//
 650 // Predicate helper class
 651 //===----------------------------------------------------------------------===//
 652
 653 def isSICI : Predicate<
 654   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
 655   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
 656 >, AssemblerPredicate<"!FeatureGCN3Encoding">;
 657
 658 def isVI : Predicate <
 659   "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
 660   AssemblerPredicate<"FeatureGCN3Encoding">;
 661
 662 def isGFX9 : Predicate <
 663   "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 664   AssemblerPredicate<"FeatureGFX9Insts">;
 665
 666 // TODO: Either the name to be changed or we simply use IsCI!
 667 def isCIVI : Predicate <
 668   "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
 669   AssemblerPredicate<"FeatureCIInsts">;
 670
 671 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
 672   AssemblerPredicate<"FeatureFlatAddressSpace">;
 673
 674 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
 675   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 676 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
 677   AssemblerPredicate<"FeatureFlatScratchInsts">;
 678 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
 679   AssemblerPredicate<"FeatureGFX9Insts">;
 680
 681 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
 682   AssemblerPredicate<"FeatureUnpackedD16VMem">;
 683 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
 684   AssemblerPredicate<"!FeatureUnpackedD16VMem">;
 685
 686 def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">,
 687   AssemblerPredicate<"FeatureD16PreservesUnusedBits">;
 688
 689 def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
 690 def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
 691
 692 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
 693   AssemblerPredicate<"FeatureGFX9Insts">;
 694
 695 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
 696   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 697
 698 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
 699   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 700
 701 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
 702   AssemblerPredicate<"Feature16BitInsts">;
 703 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
 704   AssemblerPredicate<"FeatureVOP3P">;
 705
 706 def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
 707   AssemblerPredicate<"!FeatureVOP3P">;
 708
 709 def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
 710   AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
 711
 712 def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
 713   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 714
 715 def HasDPP : Predicate<"Subtarget->hasDPP()">,
 716   AssemblerPredicate<"FeatureDPP">;
 717
 718 def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
 719   AssemblerPredicate<"FeatureR128A16">;
 720
 721 def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
 722   AssemblerPredicate<"FeatureIntClamp">;
 723
 724 def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
 725   AssemblerPredicate<"FeatureMadMixInsts">;
 726
 727 def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
 728   AssemblerPredicate<"FeatureScalarAtomics">;
 729
 730 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
 731 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
 732 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
 733                       AssemblerPredicate<"FeatureVGPRIndexMode">;
 734 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
 735                 AssemblerPredicate<"FeatureMovrel">;
 736
 737 def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
 738   AssemblerPredicate<"FeatureFmaMixInsts">;
 739
 740 def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
 741   AssemblerPredicate<"FeatureDLInsts">;
 742
 743
 744 def EnableLateCFGStructurize : Predicate<
 745   "EnableLateStructurizeCFG">;
 746
 747 // Include AMDGPU TD files
 748 include "SISchedule.td"
 749 include "GCNProcessors.td"
 750 include "AMDGPUInstrInfo.td"
 751 include "AMDGPUIntrinsics.td"
 752 include "SIIntrinsics.td"
 753 include "AMDGPURegisterInfo.td"
 754 include "AMDGPURegisterBanks.td"
 755 include "AMDGPUInstructions.td"
 756 include "SIInstrInfo.td"
 757 include "AMDGPUCallingConv.td"
 758 include "AMDGPUSearchableTables.td"