[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
[llvm-core.git] / lib / Target / AMDGPU / AMDGPUInstrInfo.h
blob2f8166da0d3375caed68b685a03dd45c64b5bea2
1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// Contains the definition of a TargetInstrInfo class that is common
12 /// to all AMD GPUs.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
19 #include "AMDGPU.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
23 namespace llvm {
25 class GCNSubtarget;
26 class MachineFunction;
27 class MachineInstr;
28 class MachineInstrBuilder;
30 class AMDGPUInstrInfo {
31 public:
32 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
34 static bool isUniformMMO(const MachineMemOperand *MMO);
37 namespace AMDGPU {
39 struct RsrcIntrinsic {
40 unsigned Intr;
41 uint8_t RsrcArg;
42 bool IsImage;
44 const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
46 struct D16ImageDimIntrinsic {
47 unsigned Intr;
48 unsigned D16HelperIntr;
50 const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
52 struct ImageDimIntrinsicInfo {
53 unsigned Intr;
54 unsigned BaseOpcode;
55 MIMGDim Dim;
57 const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
59 } // end AMDGPU namespace
60 } // End llvm namespace
62 #endif