lib/Target/AMDGPU/R600AsmPrinter.cpp

   1 //===-- R600AsmPrinter.cpp - R600 Assebly printer  ------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The R600AsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17
  18 #include "R600AsmPrinter.h"
  19 #include "AMDGPUSubtarget.h"
  20 #include "R600Defines.h"
  21 #include "R600MachineFunctionInfo.h"
  22 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  23 #include "llvm/BinaryFormat/ELF.h"
  24 #include "llvm/MC/MCContext.h"
  25 #include "llvm/MC/MCSectionELF.h"
  26 #include "llvm/MC/MCStreamer.h"
  27 #include "llvm/Target/TargetLoweringObjectFile.h"
  28
  29 using namespace llvm;
  30
  31 AsmPrinter *
  32 llvm::createR600AsmPrinterPass(TargetMachine &TM,
  33                                std::unique_ptr<MCStreamer> &&Streamer) {
  34   return new R600AsmPrinter(TM, std::move(Streamer));
  35 }
  36
  37 R600AsmPrinter::R600AsmPrinter(TargetMachine &TM,
  38                                std::unique_ptr<MCStreamer> Streamer)
  39   : AsmPrinter(TM, std::move(Streamer)) { }
  40
  41 StringRef R600AsmPrinter::getPassName() const {
  42   return "R600 Assembly Printer";
  43 }
  44
  45 void R600AsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
  46   unsigned MaxGPR = 0;
  47   bool killPixel = false;
  48   const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>();
  49   const R600RegisterInfo *RI = STM.getRegisterInfo();
  50   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
  51
  52   for (const MachineBasicBlock &MBB : MF) {
  53     for (const MachineInstr &MI : MBB) {
  54       if (MI.getOpcode() == R600::KILLGT)
  55         killPixel = true;
  56       unsigned numOperands = MI.getNumOperands();
  57       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
  58         const MachineOperand &MO = MI.getOperand(op_idx);
  59         if (!MO.isReg())
  60           continue;
  61         unsigned HWReg = RI->getHWRegIndex(MO.getReg());
  62
  63         // Register with value > 127 aren't GPR
  64         if (HWReg > 127)
  65           continue;
  66         MaxGPR = std::max(MaxGPR, HWReg);
  67       }
  68     }
  69   }
  70
  71   unsigned RsrcReg;
  72   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
  73     // Evergreen / Northern Islands
  74     switch (MF.getFunction().getCallingConv()) {
  75     default: LLVM_FALLTHROUGH;
  76     case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
  77     case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
  78     case CallingConv::AMDGPU_PS: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
  79     case CallingConv::AMDGPU_VS: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
  80     }
  81   } else {
  82     // R600 / R700
  83     switch (MF.getFunction().getCallingConv()) {
  84     default: LLVM_FALLTHROUGH;
  85     case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
  86     case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
  87     case CallingConv::AMDGPU_VS: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
  88     case CallingConv::AMDGPU_PS: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
  89     }
  90   }
  91
  92   OutStreamer->EmitIntValue(RsrcReg, 4);
  93   OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
  94                            S_STACK_SIZE(MFI->CFStackSize), 4);
  95   OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
  96   OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
  97
  98   if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
  99     OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 100     OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
 101   }
 102 }
 103
 104 bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
 105
 106
 107   // Functions needs to be cacheline (256B) aligned.
 108   MF.ensureAlignment(8);
 109
 110   SetupMachineFunction(MF);
 111
 112   MCContext &Context = getObjFileLowering().getContext();
 113   MCSectionELF *ConfigSection =
 114       Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
 115   OutStreamer->SwitchSection(ConfigSection);
 116
 117   EmitProgramInfoR600(MF);
 118
 119   EmitFunctionBody();
 120
 121   if (isVerbose()) {
 122     MCSectionELF *CommentSection =
 123         Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
 124     OutStreamer->SwitchSection(CommentSection);
 125
 126     R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 127     OutStreamer->emitRawComment(
 128       Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->CFStackSize)));
 129   }
 130
 131   return false;
 132 }
 133