lib/Target/AMDGPU/R600Defines.h

   1 //===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 /// \file
   9 //===----------------------------------------------------------------------===//
  10
  11 #ifndef LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
  12 #define LLVM_LIB_TARGET_AMDGPU_R600DEFINES_H
  13
  14 #include "llvm/MC/MCRegisterInfo.h"
  15
  16 // Operand Flags
  17 #define MO_FLAG_CLAMP (1 << 0)
  18 #define MO_FLAG_NEG   (1 << 1)
  19 #define MO_FLAG_ABS   (1 << 2)
  20 #define MO_FLAG_MASK  (1 << 3)
  21 #define MO_FLAG_PUSH  (1 << 4)
  22 #define MO_FLAG_NOT_LAST  (1 << 5)
  23 #define MO_FLAG_LAST  (1 << 6)
  24 #define NUM_MO_FLAGS 7
  25
  26 /// Helper for getting the operand index for the instruction flags
  27 /// operand.
  28 #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
  29
  30 namespace R600_InstFlag {
  31   enum TIF {
  32     TRANS_ONLY = (1 << 0),
  33     TEX = (1 << 1),
  34     REDUCTION = (1 << 2),
  35     FC = (1 << 3),
  36     TRIG = (1 << 4),
  37     OP3 = (1 << 5),
  38     VECTOR = (1 << 6),
  39     //FlagOperand bits 7, 8
  40     NATIVE_OPERANDS = (1 << 9),
  41     OP1 = (1 << 10),
  42     OP2 = (1 << 11),
  43     VTX_INST  = (1 << 12),
  44     TEX_INST = (1 << 13),
  45     ALU_INST = (1 << 14),
  46     LDS_1A = (1 << 15),
  47     LDS_1A1D = (1 << 16),
  48     IS_EXPORT = (1 << 17),
  49     LDS_1A2D = (1 << 18)
  50   };
  51 }
  52
  53 #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
  54
  55 /// Defines for extracting register information from register encoding
  56 #define HW_REG_MASK 0x1ff
  57 #define HW_CHAN_SHIFT 9
  58
  59 #define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
  60 #define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
  61
  62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
  63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
  64
  65 namespace OpName {
  66
  67   enum VecOps {
  68     UPDATE_EXEC_MASK_X,
  69     UPDATE_PREDICATE_X,
  70     WRITE_X,
  71     OMOD_X,
  72     DST_REL_X,
  73     CLAMP_X,
  74     SRC0_X,
  75     SRC0_NEG_X,
  76     SRC0_REL_X,
  77     SRC0_ABS_X,
  78     SRC0_SEL_X,
  79     SRC1_X,
  80     SRC1_NEG_X,
  81     SRC1_REL_X,
  82     SRC1_ABS_X,
  83     SRC1_SEL_X,
  84     PRED_SEL_X,
  85     UPDATE_EXEC_MASK_Y,
  86     UPDATE_PREDICATE_Y,
  87     WRITE_Y,
  88     OMOD_Y,
  89     DST_REL_Y,
  90     CLAMP_Y,
  91     SRC0_Y,
  92     SRC0_NEG_Y,
  93     SRC0_REL_Y,
  94     SRC0_ABS_Y,
  95     SRC0_SEL_Y,
  96     SRC1_Y,
  97     SRC1_NEG_Y,
  98     SRC1_REL_Y,
  99     SRC1_ABS_Y,
 100     SRC1_SEL_Y,
 101     PRED_SEL_Y,
 102     UPDATE_EXEC_MASK_Z,
 103     UPDATE_PREDICATE_Z,
 104     WRITE_Z,
 105     OMOD_Z,
 106     DST_REL_Z,
 107     CLAMP_Z,
 108     SRC0_Z,
 109     SRC0_NEG_Z,
 110     SRC0_REL_Z,
 111     SRC0_ABS_Z,
 112     SRC0_SEL_Z,
 113     SRC1_Z,
 114     SRC1_NEG_Z,
 115     SRC1_REL_Z,
 116     SRC1_ABS_Z,
 117     SRC1_SEL_Z,
 118     PRED_SEL_Z,
 119     UPDATE_EXEC_MASK_W,
 120     UPDATE_PREDICATE_W,
 121     WRITE_W,
 122     OMOD_W,
 123     DST_REL_W,
 124     CLAMP_W,
 125     SRC0_W,
 126     SRC0_NEG_W,
 127     SRC0_REL_W,
 128     SRC0_ABS_W,
 129     SRC0_SEL_W,
 130     SRC1_W,
 131     SRC1_NEG_W,
 132     SRC1_REL_W,
 133     SRC1_ABS_W,
 134     SRC1_SEL_W,
 135     PRED_SEL_W,
 136     IMM_0,
 137     IMM_1,
 138     VEC_COUNT
 139  };
 140
 141 }
 142
 143 //===----------------------------------------------------------------------===//
 144 // Config register definitions
 145 //===----------------------------------------------------------------------===//
 146
 147 #define R_02880C_DB_SHADER_CONTROL                    0x02880C
 148 #define   S_02880C_KILL_ENABLE(x)                      (((x) & 0x1) << 6)
 149
 150 // These fields are the same for all shader types and families.
 151 #define   S_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
 152 #define   S_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
 153 //===----------------------------------------------------------------------===//
 154 // R600, R700 Registers
 155 //===----------------------------------------------------------------------===//
 156
 157 #define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
 158 #define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
 159
 160 //===----------------------------------------------------------------------===//
 161 // Evergreen, Northern Islands Registers
 162 //===----------------------------------------------------------------------===//
 163
 164 #define R_028844_SQ_PGM_RESOURCES_PS                 0x028844
 165 #define R_028860_SQ_PGM_RESOURCES_VS                 0x028860
 166 #define R_028878_SQ_PGM_RESOURCES_GS                 0x028878
 167 #define R_0288D4_SQ_PGM_RESOURCES_LS                 0x0288d4
 168
 169 #define R_0288E8_SQ_LDS_ALLOC                        0x0288E8
 170
 171 #endif