lib/Target/AVR/AVRISelLowering.h

   1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that AVR uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_AVR_ISEL_LOWERING_H
  16 #define LLVM_AVR_ISEL_LOWERING_H
  17
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/TargetLowering.h"
  20
  21 namespace llvm {
  22
  23 namespace AVRISD {
  24
  25 /// AVR Specific DAG Nodes
  26 enum NodeType {
  27   /// Start the numbering where the builtin ops leave off.
  28   FIRST_NUMBER = ISD::BUILTIN_OP_END,
  29   /// Return from subroutine.
  30   RET_FLAG,
  31   /// Return from ISR.
  32   RETI_FLAG,
  33   /// Represents an abstract call instruction,
  34   /// which includes a bunch of information.
  35   CALL,
  36   /// A wrapper node for TargetConstantPool,
  37   /// TargetExternalSymbol, and TargetGlobalAddress.
  38   WRAPPER,
  39   LSL,     ///< Logical shift left.
  40   LSR,     ///< Logical shift right.
  41   ASR,     ///< Arithmetic shift right.
  42   ROR,     ///< Bit rotate right.
  43   ROL,     ///< Bit rotate left.
  44   LSLLOOP, ///< A loop of single logical shift left instructions.
  45   LSRLOOP, ///< A loop of single logical shift right instructions.
  46   ROLLOOP, ///< A loop of single left bit rotate instructions.
  47   RORLOOP, ///< A loop of single right bit rotate instructions.
  48   ASRLOOP, ///< A loop of single arithmetic shift right instructions.
  49   /// AVR conditional branches. Operand 0 is the chain operand, operand 1
  50   /// is the block to branch if condition is true, operand 2 is the
  51   /// condition code, and operand 3 is the flag operand produced by a CMP
  52   /// or TEST instruction.
  53   BRCOND,
  54   /// Compare instruction.
  55   CMP,
  56   /// Compare with carry instruction.
  57   CMPC,
  58   /// Test for zero or minus instruction.
  59   TST,
  60   /// Operand 0 and operand 1 are selection variable, operand 2
  61   /// is condition code and operand 3 is flag operand.
  62   SELECT_CC
  63 };
  64
  65 } // end of namespace AVRISD
  66
  67 class AVRTargetMachine;
  68
  69 /// Performs target lowering for the AVR.
  70 class AVRTargetLowering : public TargetLowering {
  71 public:
  72   explicit AVRTargetLowering(AVRTargetMachine &TM);
  73
  74 public:
  75   MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
  76     return MVT::i8;
  77   }
  78
  79   MVT::SimpleValueType getCmpLibcallReturnType() const override {
  80     return MVT::i8;
  81   }
  82
  83   const char *getTargetNodeName(unsigned Opcode) const override;
  84
  85   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  86
  87   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
  88                           SelectionDAG &DAG) const override;
  89
  90   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
  91                              unsigned AS,
  92                              Instruction *I = nullptr) const override;
  93
  94   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
  95                                  ISD::MemIndexedMode &AM,
  96                                  SelectionDAG &DAG) const override;
  97
  98   bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
  99                                   SDValue &Offset, ISD::MemIndexedMode &AM,
 100                                   SelectionDAG &DAG) const override;
 101
 102   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 103
 104   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 105                          EVT VT) const override;
 106
 107   MachineBasicBlock *
 108   EmitInstrWithCustomInserter(MachineInstr &MI,
 109                               MachineBasicBlock *MBB) const override;
 110
 111   ConstraintType getConstraintType(StringRef Constraint) const override;
 112
 113   ConstraintWeight
 114   getSingleConstraintMatchWeight(AsmOperandInfo &info,
 115                                  const char *constraint) const override;
 116
 117   std::pair<unsigned, const TargetRegisterClass *>
 118   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 119                                StringRef Constraint, MVT VT) const override;
 120
 121   unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
 122
 123   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
 124                                     std::vector<SDValue> &Ops,
 125                                     SelectionDAG &DAG) const override;
 126
 127   unsigned getRegisterByName(const char* RegName, EVT VT,
 128                              SelectionDAG &DAG) const override;
 129
 130 private:
 131   SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
 132                     SelectionDAG &DAG, SDLoc dl) const;
 133   SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
 134   SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
 135   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 136   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 137   SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 138   SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
 139   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 140   SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 141   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 142
 143   CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
 144
 145   bool CanLowerReturn(CallingConv::ID CallConv,
 146                       MachineFunction &MF, bool isVarArg,
 147                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 148                       LLVMContext &Context) const override;
 149
 150   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 151                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 152                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
 153                       SelectionDAG &DAG) const override;
 154   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
 155                                bool isVarArg,
 156                                const SmallVectorImpl<ISD::InputArg> &Ins,
 157                                const SDLoc &dl, SelectionDAG &DAG,
 158                                SmallVectorImpl<SDValue> &InVals) const override;
 159   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 160                     SmallVectorImpl<SDValue> &InVals) const override;
 161   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 162                           CallingConv::ID CallConv, bool isVarArg,
 163                           const SmallVectorImpl<ISD::InputArg> &Ins,
 164                           const SDLoc &dl, SelectionDAG &DAG,
 165                           SmallVectorImpl<SDValue> &InVals) const;
 166
 167 private:
 168   MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
 169   MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
 170 };
 171
 172 } // end namespace llvm
 173
 174 #endif // LLVM_AVR_ISEL_LOWERING_H