lib/Target/AVR/AVRInstrInfo.h

   1 //===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the AVR implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_AVR_INSTR_INFO_H
  15 #define LLVM_AVR_INSTR_INFO_H
  16
  17 #include "llvm/CodeGen/TargetInstrInfo.h"
  18
  19 #include "AVRRegisterInfo.h"
  20
  21 #define GET_INSTRINFO_HEADER
  22 #include "AVRGenInstrInfo.inc"
  23 #undef GET_INSTRINFO_HEADER
  24
  25 namespace llvm {
  26
  27 namespace AVRCC {
  28
  29 /// AVR specific condition codes.
  30 /// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
  31 /// They must be kept in synch.
  32 enum CondCodes {
  33   COND_EQ, //!< Equal
  34   COND_NE, //!< Not equal
  35   COND_GE, //!< Greater than or equal
  36   COND_LT, //!< Less than
  37   COND_SH, //!< Unsigned same or higher
  38   COND_LO, //!< Unsigned lower
  39   COND_MI, //!< Minus
  40   COND_PL, //!< Plus
  41   COND_INVALID
  42 };
  43
  44 } // end of namespace AVRCC
  45
  46 namespace AVRII {
  47
  48 /// Specifies a target operand flag.
  49 enum TOF {
  50   MO_NO_FLAG,
  51
  52   /// On a symbol operand, this represents the lo part.
  53   MO_LO = (1 << 1),
  54
  55   /// On a symbol operand, this represents the hi part.
  56   MO_HI = (1 << 2),
  57
  58   /// On a symbol operand, this represents it has to be negated.
  59   MO_NEG = (1 << 3)
  60 };
  61
  62 } // end of namespace AVRII
  63
  64 /// Utilities related to the AVR instruction set.
  65 class AVRInstrInfo : public AVRGenInstrInfo {
  66 public:
  67   explicit AVRInstrInfo();
  68
  69   const AVRRegisterInfo &getRegisterInfo() const { return RI; }
  70   const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
  71   AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
  72   AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
  73   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
  74
  75   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  76                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
  77                    bool KillSrc) const override;
  78   void storeRegToStackSlot(MachineBasicBlock &MBB,
  79                            MachineBasicBlock::iterator MI, unsigned SrcReg,
  80                            bool isKill, int FrameIndex,
  81                            const TargetRegisterClass *RC,
  82                            const TargetRegisterInfo *TRI) const override;
  83   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  84                             MachineBasicBlock::iterator MI, unsigned DestReg,
  85                             int FrameIndex, const TargetRegisterClass *RC,
  86                             const TargetRegisterInfo *TRI) const override;
  87   unsigned isLoadFromStackSlot(const MachineInstr &MI,
  88                                int &FrameIndex) const override;
  89   unsigned isStoreToStackSlot(const MachineInstr &MI,
  90                               int &FrameIndex) const override;
  91
  92   // Branch analysis.
  93   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
  94                      MachineBasicBlock *&FBB,
  95                      SmallVectorImpl<MachineOperand> &Cond,
  96                      bool AllowModify = false) const override;
  97   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  98                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
  99                         const DebugLoc &DL,
 100                         int *BytesAdded = nullptr) const override;
 101   unsigned removeBranch(MachineBasicBlock &MBB,
 102                         int *BytesRemoved = nullptr) const override;
 103   bool
 104   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 105
 106   MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
 107
 108   bool isBranchOffsetInRange(unsigned BranchOpc,
 109                              int64_t BrOffset) const override;
 110
 111   unsigned insertIndirectBranch(MachineBasicBlock &MBB,
 112                                 MachineBasicBlock &NewDestBB,
 113                                 const DebugLoc &DL,
 114                                 int64_t BrOffset,
 115                                 RegScavenger *RS) const override;
 116 private:
 117   const AVRRegisterInfo RI;
 118 };
 119
 120 } // end namespace llvm
 121
 122 #endif // LLVM_AVR_INSTR_INFO_H