[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
[llvm-core.git] / lib / Target / NVPTX / NVPTX.h
blob02b8d8fff64702ca668dd4107504c40d11a6ec68
1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the entry points for global functions defined in
11 // the LLVM NVPTX back-end.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
16 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H
18 #include "MCTargetDesc/NVPTXBaseInfo.h"
19 #include "llvm/ADT/StringMap.h"
20 #include "llvm/IR/Module.h"
21 #include "llvm/IR/Value.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include <cassert>
25 #include <iosfwd>
27 namespace llvm {
28 class NVPTXTargetMachine;
29 class FunctionPass;
30 class MachineFunctionPass;
31 class formatted_raw_ostream;
33 namespace NVPTXCC {
34 enum CondCodes {
35 EQ,
36 NE,
37 LT,
38 LE,
39 GT,
44 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
45 llvm::CodeGenOpt::Level OptLevel);
46 ModulePass *createNVPTXAssignValidGlobalNamesPass();
47 ModulePass *createGenericToNVVMPass();
48 FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion);
49 FunctionPass *createNVVMReflectPass(unsigned int SmVersion);
50 MachineFunctionPass *createNVPTXPrologEpilogPass();
51 MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
52 FunctionPass *createNVPTXImageOptimizerPass();
53 FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM);
54 BasicBlockPass *createNVPTXLowerAllocaPass();
55 MachineFunctionPass *createNVPTXPeephole();
57 Target &getTheNVPTXTarget32();
58 Target &getTheNVPTXTarget64();
60 namespace NVPTX {
61 enum DrvInterface {
62 NVCL,
63 CUDA
66 // A field inside TSFlags needs a shift and a mask. The usage is
67 // always as follows :
68 // ((TSFlags & fieldMask) >> fieldShift)
69 // The enum keeps the mask, the shift, and all valid values of the
70 // field in one place.
71 enum VecInstType {
72 VecInstTypeShift = 0,
73 VecInstTypeMask = 0xF,
75 VecNOP = 0,
76 VecLoad = 1,
77 VecStore = 2,
78 VecBuild = 3,
79 VecShuffle = 4,
80 VecExtract = 5,
81 VecInsert = 6,
82 VecDest = 7,
83 VecOther = 15
86 enum SimpleMove {
87 SimpleMoveMask = 0x10,
88 SimpleMoveShift = 4
90 enum LoadStore {
91 isLoadMask = 0x20,
92 isLoadShift = 5,
93 isStoreMask = 0x40,
94 isStoreShift = 6
97 namespace PTXLdStInstCode {
98 enum AddressSpace {
99 GENERIC = 0,
100 GLOBAL = 1,
101 CONSTANT = 2,
102 SHARED = 3,
103 PARAM = 4,
104 LOCAL = 5
106 enum FromType {
107 Unsigned = 0,
108 Signed,
109 Float,
110 Untyped
112 enum VecType {
113 Scalar = 1,
114 V2 = 2,
115 V4 = 4
119 /// PTXCvtMode - Conversion code enumeration
120 namespace PTXCvtMode {
121 enum CvtMode {
122 NONE = 0,
123 RNI,
124 RZI,
125 RMI,
126 RPI,
132 BASE_MASK = 0x0F,
133 FTZ_FLAG = 0x10,
134 SAT_FLAG = 0x20
138 /// PTXCmpMode - Comparison mode enumeration
139 namespace PTXCmpMode {
140 enum CmpMode {
141 EQ = 0,
151 EQU,
152 NEU,
153 LTU,
154 LEU,
155 GTU,
156 GEU,
157 NUM,
158 // NAN is a MACRO
159 NotANumber,
161 BASE_MASK = 0xFF,
162 FTZ_FLAG = 0x100
166 } // end namespace llvm;
168 // Defines symbolic names for NVPTX registers. This defines a mapping from
169 // register name to register number.
170 #define GET_REGINFO_ENUM
171 #include "NVPTXGenRegisterInfo.inc"
173 // Defines symbolic names for the NVPTX instructions.
174 #define GET_INSTRINFO_ENUM
175 #include "NVPTXGenInstrInfo.inc"
177 #endif