[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
[llvm-core.git] / lib / Target / NVPTX / NVPTXTargetMachine.h
blobca540b8e0389c5f386db69d33ca0bf6d31517f73
1 //===-- NVPTXTargetMachine.h - Define TargetMachine for NVPTX ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the NVPTX specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
17 #include "ManagedStringPool.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/Target/TargetMachine.h"
23 namespace llvm {
25 /// NVPTXTargetMachine
26 ///
27 class NVPTXTargetMachine : public LLVMTargetMachine {
28 bool is64bit;
29 // Use 32-bit pointers for accessing const/local/short AS.
30 bool UseShortPointers;
31 std::unique_ptr<TargetLoweringObjectFile> TLOF;
32 NVPTX::DrvInterface drvInterface;
33 NVPTXSubtarget Subtarget;
35 // Hold Strings that can be free'd all together with NVPTXTargetMachine
36 ManagedStringPool ManagedStrPool;
38 public:
39 NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
40 StringRef FS, const TargetOptions &Options,
41 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
42 CodeGenOpt::Level OP, bool is64bit);
44 ~NVPTXTargetMachine() override;
45 const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
46 return &Subtarget;
48 const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
49 bool is64Bit() const { return is64bit; }
50 bool useShortPointers() const { return UseShortPointers; }
51 NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }
52 ManagedStringPool *getManagedStrPool() const {
53 return const_cast<ManagedStringPool *>(&ManagedStrPool);
56 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
58 // Emission of machine code through MCJIT is not supported.
59 bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_pwrite_stream &,
60 bool = true) override {
61 return true;
63 TargetLoweringObjectFile *getObjFileLowering() const override {
64 return TLOF.get();
67 void adjustPassManager(PassManagerBuilder &) override;
69 TargetTransformInfo getTargetTransformInfo(const Function &F) override;
71 bool isMachineVerifierClean() const override {
72 return false;
74 }; // NVPTXTargetMachine.
76 class NVPTXTargetMachine32 : public NVPTXTargetMachine {
77 virtual void anchor();
78 public:
79 NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
80 StringRef FS, const TargetOptions &Options,
81 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
82 CodeGenOpt::Level OL, bool JIT);
85 class NVPTXTargetMachine64 : public NVPTXTargetMachine {
86 virtual void anchor();
87 public:
88 NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
89 StringRef FS, const TargetOptions &Options,
90 Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
91 CodeGenOpt::Level OL, bool JIT);
94 } // end namespace llvm
96 #endif