[PowerPC] Do not emit record-form rotates when record-form andi/andis suffices
[llvm-core.git] / lib / Target / SystemZ / SystemZTargetTransformInfo.h
blobbfa942357c55979989660516c9b2d194a73f60f6
1 //===-- SystemZTargetTransformInfo.h - SystemZ-specific TTI ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETTRANSFORMINFO_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETTRANSFORMINFO_H
13 #include "SystemZTargetMachine.h"
14 #include "llvm/Analysis/TargetTransformInfo.h"
15 #include "llvm/CodeGen/BasicTTIImpl.h"
17 namespace llvm {
19 class SystemZTTIImpl : public BasicTTIImplBase<SystemZTTIImpl> {
20 typedef BasicTTIImplBase<SystemZTTIImpl> BaseT;
21 typedef TargetTransformInfo TTI;
22 friend BaseT;
24 const SystemZSubtarget *ST;
25 const SystemZTargetLowering *TLI;
27 const SystemZSubtarget *getST() const { return ST; }
28 const SystemZTargetLowering *getTLI() const { return TLI; }
30 unsigned const LIBCALL_COST = 30;
32 public:
33 explicit SystemZTTIImpl(const SystemZTargetMachine *TM, const Function &F)
34 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
35 TLI(ST->getTargetLowering()) {}
37 /// \name Scalar TTI Implementations
38 /// @{
40 unsigned getInliningThresholdMultiplier() { return 3; }
42 int getIntImmCost(const APInt &Imm, Type *Ty);
44 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
45 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
46 Type *Ty);
48 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
50 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
51 TTI::UnrollingPreferences &UP);
53 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
54 TargetTransformInfo::LSRCost &C2);
55 /// @}
57 /// \name Vector TTI Implementations
58 /// @{
60 unsigned getNumberOfRegisters(bool Vector);
61 unsigned getRegisterBitWidth(bool Vector) const;
63 unsigned getCacheLineSize() { return 256; }
64 unsigned getPrefetchDistance() { return 2000; }
65 unsigned getMinPrefetchStride() { return 2048; }
67 bool hasDivRemOp(Type *DataType, bool IsSigned);
68 bool prefersVectorizedAddressing() { return false; }
69 bool LSRWithInstrQueries() { return true; }
70 bool supportsEfficientVectorElementLoadStore() { return true; }
71 bool enableInterleavedAccessVectorization() { return true; }
73 int getArithmeticInstrCost(
74 unsigned Opcode, Type *Ty,
75 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
76 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
77 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
78 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
79 ArrayRef<const Value *> Args = ArrayRef<const Value *>());
80 int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
81 unsigned getVectorTruncCost(Type *SrcTy, Type *DstTy);
82 unsigned getVectorBitmaskConversionCost(Type *SrcTy, Type *DstTy);
83 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
84 const Instruction *I = nullptr);
85 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
86 const Instruction *I = nullptr);
87 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
88 int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
89 unsigned AddressSpace, const Instruction *I = nullptr);
91 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
92 unsigned Factor,
93 ArrayRef<unsigned> Indices,
94 unsigned Alignment,
95 unsigned AddressSpace);
96 /// @}
99 } // end namespace llvm
101 #endif