lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  35                                       "Enable X87 float instructions">;
  36
  37 def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
  38                                       "Enable NOPL instruction">;
  39
  40 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  41                                       "Enable conditional move instructions">;
  42
  43 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  44                                        "Support POPCNT instruction">;
  45
  46 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  47                                       "Support fxsave/fxrestore instructions">;
  48
  49 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  50                                        "Support xsave instructions">;
  51
  52 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  53                                        "Support xsaveopt instructions">;
  54
  55 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  56                                        "Support xsavec instructions">;
  57
  58 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  59                                        "Support xsaves instructions">;
  60
  61 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  62                                       "Enable SSE instructions">;
  63 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  64                                       "Enable SSE2 instructions",
  65                                       [FeatureSSE1]>;
  66 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  67                                       "Enable SSE3 instructions",
  68                                       [FeatureSSE2]>;
  69 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  70                                       "Enable SSSE3 instructions",
  71                                       [FeatureSSE3]>;
  72 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  73                                       "Enable SSE 4.1 instructions",
  74                                       [FeatureSSSE3]>;
  75 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  76                                       "Enable SSE 4.2 instructions",
  77                                       [FeatureSSE41]>;
  78 // The MMX subtarget feature is separate from the rest of the SSE features
  79 // because it's important (for odd compatibility reasons) to be able to
  80 // turn it off explicitly while allowing SSE+ to be on.
  81 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  82                                       "Enable MMX instructions">;
  83 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  84                                       "Enable 3DNow! instructions",
  85                                       [FeatureMMX]>;
  86 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  87                                       "Enable 3DNow! Athlon instructions",
  88                                       [Feature3DNow]>;
  89 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  90 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  91 // without disabling 64-bit mode. Nothing should imply this feature bit. It
  92 // is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
  93 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  94                                       "Support 64-bit instructions">;
  95 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  96                                       "64-bit with cmpxchg16b">;
  97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  98                                        "SHLD instruction is slow">;
  99 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 100                                         "PMULLD instruction is slow">;
 101 // FIXME: This should not apply to CPUs that do not have SSE.
 102 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 103                                 "IsUAMem16Slow", "true",
 104                                 "Slow unaligned 16-byte memory access">;
 105 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 106                                 "IsUAMem32Slow", "true",
 107                                 "Slow unaligned 32-byte memory access">;
 108 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 109                                       "Support SSE 4a instructions",
 110                                       [FeatureSSE3]>;
 111
 112 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 113                                       "Enable AVX instructions",
 114                                       [FeatureSSE42]>;
 115 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 116                                       "Enable AVX2 instructions",
 117                                       [FeatureAVX]>;
 118 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 119                                       "Enable three-operand fused multiple-add",
 120                                       [FeatureAVX]>;
 121 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 122                        "Support 16-bit floating point conversion instructions",
 123                        [FeatureAVX]>;
 124 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 125                                       "Enable AVX-512 instructions",
 126                                       [FeatureAVX2, FeatureFMA, FeatureF16C]>;
 127 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 128                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 129                                       [FeatureAVX512]>;
 130 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 131                       "Enable AVX-512 Conflict Detection Instructions",
 132                                       [FeatureAVX512]>;
 133 def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
 134                        "true", "Enable AVX-512 Population Count Instructions",
 135                                       [FeatureAVX512]>;
 136 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 137                       "Enable AVX-512 PreFetch Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
 140                                    "true",
 141                                    "Prefetch with Intent to Write and T1 Hint">;
 142 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 143                       "Enable AVX-512 Doubleword and Quadword Instructions",
 144                                       [FeatureAVX512]>;
 145 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 146                       "Enable AVX-512 Byte and Word Instructions",
 147                                       [FeatureAVX512]>;
 148 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 149                       "Enable AVX-512 Vector Length eXtensions",
 150                                       [FeatureAVX512]>;
 151 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 152                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 153                                       [FeatureBWI]>;
 154 def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
 155                       "Enable AVX-512 further Vector Byte Manipulation Instructions",
 156                                       [FeatureBWI]>;
 157 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 158                       "Enable AVX-512 Integer Fused Multiple-Add",
 159                                       [FeatureAVX512]>;
 160 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 161                       "Enable protection keys">;
 162 def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
 163                           "Enable AVX-512 Vector Neural Network Instructions",
 164                                       [FeatureAVX512]>;
 165 def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
 166                        "Enable AVX-512 Bit Algorithms",
 167                         [FeatureBWI]>;
 168 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 169                          "Enable packed carry-less multiplication instructions",
 170                                [FeatureSSE2]>;
 171 def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
 172                          "Enable Galois Field Arithmetic Instructions",
 173                                [FeatureSSE2]>;
 174 def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
 175                                          "Enable vpclmulqdq instructions",
 176                                          [FeatureAVX, FeaturePCLMUL]>;
 177 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 178                                       "Enable four-operand fused multiple-add",
 179                                       [FeatureAVX, FeatureSSE4A]>;
 180 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 181                                       "Enable XOP instructions",
 182                                       [FeatureFMA4]>;
 183 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 184                                           "HasSSEUnalignedMem", "true",
 185                       "Allow unaligned memory operands with SSE instructions">;
 186 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 187                                       "Enable AES instructions",
 188                                       [FeatureSSE2]>;
 189 def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
 190                        "Promote selected AES instructions to AVX512/AVX registers",
 191                         [FeatureAVX, FeatureAES]>;
 192 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 193                                       "Enable TBM instructions">;
 194 def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
 195                                       "Enable LWP instructions">;
 196 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 197                                       "Support MOVBE instruction">;
 198 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 199                                       "Support RDRAND instruction">;
 200 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 201                                        "Support FS/GS Base instructions">;
 202 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 203                                       "Support LZCNT instruction">;
 204 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 205                                       "Support BMI instructions">;
 206 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 207                                       "Support BMI2 instructions">;
 208 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 209                                       "Support RTM instructions">;
 210 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 211                                       "Support ADX instructions">;
 212 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 213                                       "Enable SHA instructions",
 214                                       [FeatureSSE2]>;
 215 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
 216                        "Support CET Shadow-Stack instructions">;
 217 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 218                                       "Support PRFCHW instructions">;
 219 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 220                                       "Support RDSEED instruction">;
 221 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 222                                        "Support LAHF and SAHF instructions">;
 223 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 224                                       "Enable MONITORX/MWAITX timer functionality">;
 225 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 226                                       "Enable Cache Line Zero">;
 227 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
 228                                       "Enable Cache Demote">;
 229 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
 230                                       "Support ptwrite instruction">;
 231 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 232                                       "Support MPX instructions">;
 233 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 234                                      "Use LEA for adjusting the stack pointer">;
 235 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 236                                      "HasSlowDivide32", "true",
 237                                      "Use 8-bit divide for positive values less than 256">;
 238 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 239                                      "HasSlowDivide64", "true",
 240                                      "Use 32-bit divide for positive values less than 2^32">;
 241 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 242                                      "PadShortFunctions", "true",
 243                                      "Pad short functions">;
 244 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
 245                                       "Invalidate Process-Context Identifier">;
 246 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 247                                       "Enable Software Guard Extensions">;
 248 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 249                                       "Flush A Cache Line Optimized">;
 250 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 251                                       "Cache Line Write Back">;
 252 def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
 253                                       "Write Back No Invalidate">;
 254 def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
 255                                     "Support RDPID instructions">;
 256 def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
 257                                       "Wait and pause enhancements">;
 258 // On some processors, instructions that implicitly take two memory operands are
 259 // slow. In practice, this means that CALL, PUSH, and POP with memory operands
 260 // should be avoided in favor of a MOV + register CALL/PUSH/POP.
 261 def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
 262                                      "SlowTwoMemOps", "true",
 263                                      "Two memory operand instructions are slow">;
 264 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 265                                    "LEA instruction needs inputs at AG stage">;
 266 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 267                                    "LEA instruction with certain arguments is slow">;
 268 def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
 269                                    "LEA instruction with 3 ops or certain registers is slow">;
 270 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 271                                    "INC and DEC instructions are slower than ADD and SUB">;
 272 def FeatureSoftFloat
 273     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 274                        "Use software floating point features.">;
 275 def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
 276                                      "HasPOPCNTFalseDeps", "true",
 277                                      "POPCNT has a false dependency on dest register">;
 278 def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
 279                                      "HasLZCNTFalseDeps", "true",
 280                                      "LZCNT/TZCNT have a false dependency on dest register">;
 281 def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
 282                                       "platform configuration instruction">;
 283 // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
 284 // using a variable mask over multiple fixed shuffles.
 285 def FeatureFastVariableShuffle
 286     : SubtargetFeature<"fast-variable-shuffle",
 287                        "HasFastVariableShuffle",
 288                        "true", "Shuffles with variable masks are fast">;
 289 // On some X86 processors, there is no performance hazard to writing only the
 290 // lower parts of a YMM or ZMM register without clearing the upper part.
 291 def FeatureFastPartialYMMorZMMWrite
 292     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 293                        "HasFastPartialYMMorZMMWrite",
 294                        "true", "Partial writes to YMM/ZMM registers are fast">;
 295 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 296 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 297 // vector FSQRT has higher throughput than the corresponding NR code.
 298 // The idea is that throughput bound code is likely to be vectorized, so for
 299 // vectorized code we should care about the throughput of SQRT operations.
 300 // But if the code is scalar that probably means that the code has some kind of
 301 // dependency and we should care more about reducing the latency.
 302 def FeatureFastScalarFSQRT
 303     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 304                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 305 def FeatureFastVectorFSQRT
 306     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 307                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 308 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 309 // be used to replace test/set sequences.
 310 def FeatureFastLZCNT
 311     : SubtargetFeature<
 312           "fast-lzcnt", "HasFastLZCNT", "true",
 313           "LZCNT instructions are as fast as most simple integer ops">;
 314 // If the target can efficiently decode NOPs upto 11-bytes in length.
 315 def FeatureFast11ByteNOP
 316     : SubtargetFeature<
 317           "fast-11bytenop", "HasFast11ByteNOP", "true",
 318           "Target can quickly decode up to 11 byte NOPs">;
 319 // If the target can efficiently decode NOPs upto 15-bytes in length.
 320 def FeatureFast15ByteNOP
 321     : SubtargetFeature<
 322           "fast-15bytenop", "HasFast15ByteNOP", "true",
 323           "Target can quickly decode up to 15 byte NOPs">;
 324 // Sandy Bridge and newer processors can use SHLD with the same source on both
 325 // inputs to implement rotate to avoid the partial flag update of the normal
 326 // rotate instructions.
 327 def FeatureFastSHLDRotate
 328     : SubtargetFeature<
 329           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 330           "SHLD can be used as a faster rotate">;
 331
 332 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 333 // "string operations"). See "REP String Enhancement" in the Intel Software
 334 // Development Manual. This feature essentially means that REP MOVSB will copy
 335 // using the largest available size instead of copying bytes one by one, making
 336 // it at least as fast as REPMOVS{W,D,Q}.
 337 def FeatureERMSB
 338     : SubtargetFeature<
 339           "ermsb", "HasERMSB", "true",
 340           "REP MOVS/STOS are fast">;
 341
 342 // Sandy Bridge and newer processors have many instructions that can be
 343 // fused with conditional branches and pass through the CPU as a single
 344 // operation.
 345 def FeatureMacroFusion
 346     : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
 347                  "Various instructions can be fused with conditional branches">;
 348
 349 // Gather is available since Haswell (AVX2 set). So technically, we can
 350 // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
 351 // Skylake Client processor has faster Gathers than HSW and performance is
 352 // similar to Skylake Server (AVX-512).
 353 def FeatureHasFastGather
 354     : SubtargetFeature<"fast-gather", "HasFastGather", "true",
 355                        "Indicates if gather is reasonably fast.">;
 356
 357 def FeaturePrefer256Bit
 358     : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
 359                        "Prefer 256-bit AVX instructions">;
 360
 361 // Lower indirect calls using a special construct called a `retpoline` to
 362 // mitigate potential Spectre v2 attacks against them.
 363 def FeatureRetpolineIndirectCalls
 364     : SubtargetFeature<
 365           "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
 366           "Remove speculation of indirect calls from the generated code.">;
 367
 368 // Lower indirect branches and switches either using conditional branch trees
 369 // or using a special construct called a `retpoline` to mitigate potential
 370 // Spectre v2 attacks against them.
 371 def FeatureRetpolineIndirectBranches
 372     : SubtargetFeature<
 373           "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
 374           "Remove speculation of indirect branches from the generated code.">;
 375
 376 // Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
 377 // `retpoline-indirect-branches` above.
 378 def FeatureRetpoline
 379     : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
 380                        "Remove speculation of indirect branches from the "
 381                        "generated code, either by avoiding them entirely or "
 382                        "lowering them with a speculation blocking construct.",
 383                        [FeatureRetpolineIndirectCalls,
 384                         FeatureRetpolineIndirectBranches]>;
 385
 386 // Rely on external thunks for the emitted retpoline calls. This allows users
 387 // to provide their own custom thunk definitions in highly specialized
 388 // environments such as a kernel that does boot-time hot patching.
 389 def FeatureRetpolineExternalThunk
 390     : SubtargetFeature<
 391           "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
 392           "When lowering an indirect call or branch using a `retpoline`, rely "
 393           "on the specified user provided thunk rather than emitting one "
 394           "ourselves. Only has effect when combined with some other retpoline "
 395           "feature.", [FeatureRetpolineIndirectCalls]>;
 396
 397 // Direct Move instructions.
 398 def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
 399                                        "Support movdiri instruction">;
 400 def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
 401                                         "Support movdir64b instruction">;
 402
 403 //===----------------------------------------------------------------------===//
 404 // Register File Description
 405 //===----------------------------------------------------------------------===//
 406
 407 include "X86RegisterInfo.td"
 408 include "X86RegisterBanks.td"
 409
 410 //===----------------------------------------------------------------------===//
 411 // Instruction Descriptions
 412 //===----------------------------------------------------------------------===//
 413
 414 include "X86Schedule.td"
 415 include "X86InstrInfo.td"
 416 include "X86SchedPredicates.td"
 417
 418 def X86InstrInfo : InstrInfo;
 419
 420 //===----------------------------------------------------------------------===//
 421 // X86 processors supported.
 422 //===----------------------------------------------------------------------===//
 423
 424 include "X86ScheduleAtom.td"
 425 include "X86SchedSandyBridge.td"
 426 include "X86SchedHaswell.td"
 427 include "X86SchedBroadwell.td"
 428 include "X86ScheduleSLM.td"
 429 include "X86ScheduleZnver1.td"
 430 include "X86ScheduleBtVer2.td"
 431 include "X86SchedSkylakeClient.td"
 432 include "X86SchedSkylakeServer.td"
 433
 434 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 435                     "Intel Atom processors">;
 436 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 437                     "Intel Silvermont processors">;
 438 def ProcIntelGLM  : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM",
 439                     "Intel Goldmont processors">;
 440 def ProcIntelGLP  : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP",
 441                     "Intel Goldmont Plus processors">;
 442 def ProcIntelTRM  : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM",
 443                     "Intel Tremont processors">;
 444 def ProcIntelHSW  : SubtargetFeature<"haswell", "X86ProcFamily",
 445                     "IntelHaswell", "Intel Haswell processors">;
 446 def ProcIntelBDW  : SubtargetFeature<"broadwell", "X86ProcFamily",
 447                     "IntelBroadwell", "Intel Broadwell processors">;
 448 def ProcIntelSKL  : SubtargetFeature<"skylake", "X86ProcFamily",
 449                     "IntelSkylake", "Intel Skylake processors">;
 450 def ProcIntelKNL  : SubtargetFeature<"knl", "X86ProcFamily",
 451                     "IntelKNL", "Intel Knights Landing processors">;
 452 def ProcIntelSKX  : SubtargetFeature<"skx", "X86ProcFamily",
 453                     "IntelSKX", "Intel Skylake Server processors">;
 454 def ProcIntelCNL  : SubtargetFeature<"cannonlake", "X86ProcFamily",
 455                     "IntelCannonlake", "Intel Cannonlake processors">;
 456 def ProcIntelICL  : SubtargetFeature<"icelake-client", "X86ProcFamily",
 457                     "IntelIcelakeClient", "Intel Icelake processors">;
 458 def ProcIntelICX  : SubtargetFeature<"icelake-server", "X86ProcFamily",
 459                     "IntelIcelakeServer", "Intel Icelake Server processors">;
 460
 461 class Proc<string Name, list<SubtargetFeature> Features>
 462  : ProcessorModel<Name, GenericModel, Features>;
 463
 464 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 465 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 466 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 467 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 468 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 469 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 470
 471 def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
 472 def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
 473                           FeatureNOPL]>;
 474
 475 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 476                                FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
 477
 478 foreach P = ["pentium3", "pentium3m"] in {
 479   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 480                  FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 481 }
 482
 483 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 484 // The intent is to enable it for pentium4 which is the current default
 485 // processor in a vanilla 32-bit clang compilation when no specific
 486 // architecture is specified.  This generally gives a nice performance
 487 // increase on silvermont, with largely neutral behavior on other
 488 // contemporary large core processors.
 489 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 490 // measure to avoid performance surprises, in case clang's default cpu
 491 // changes slightly.
 492
 493 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 494                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 495                       FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 496
 497 foreach P = ["pentium4", "pentium4m"] in {
 498   def : ProcessorModel<P, GenericPostRAModel,
 499                        [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
 500                         FeatureSSE2, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 501 }
 502
 503 // Intel Quark.
 504 def : Proc<"lakemont",        []>;
 505
 506 // Intel Core Duo.
 507 def : ProcessorModel<"yonah", SandyBridgeModel,
 508                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 509                       FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 510
 511 // NetBurst.
 512 def : ProcessorModel<"prescott", GenericPostRAModel,
 513                      [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
 514                       FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 515 def : ProcessorModel<"nocona", GenericPostRAModel, [
 516   FeatureX87,
 517   FeatureSlowUAMem16,
 518   FeatureCMOV,
 519   FeatureMMX,
 520   FeatureSSE3,
 521   FeatureFXSR,
 522   FeatureNOPL,
 523   Feature64Bit,
 524   FeatureCMPXCHG16B
 525 ]>;
 526
 527 // Intel Core 2 Solo/Duo.
 528 def : ProcessorModel<"core2", SandyBridgeModel, [
 529   FeatureX87,
 530   FeatureSlowUAMem16,
 531   FeatureCMOV,
 532   FeatureMMX,
 533   FeatureSSSE3,
 534   FeatureFXSR,
 535   FeatureNOPL,
 536   Feature64Bit,
 537   FeatureCMPXCHG16B,
 538   FeatureLAHFSAHF,
 539   FeatureMacroFusion
 540 ]>;
 541 def : ProcessorModel<"penryn", SandyBridgeModel, [
 542   FeatureX87,
 543   FeatureSlowUAMem16,
 544   FeatureCMOV,
 545   FeatureMMX,
 546   FeatureSSE41,
 547   FeatureFXSR,
 548   FeatureNOPL,
 549   Feature64Bit,
 550   FeatureCMPXCHG16B,
 551   FeatureLAHFSAHF,
 552   FeatureMacroFusion
 553 ]>;
 554
 555 // Atom CPUs.
 556 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 557   ProcIntelAtom,
 558   FeatureX87,
 559   FeatureSlowUAMem16,
 560   FeatureCMOV,
 561   FeatureMMX,
 562   FeatureSSSE3,
 563   FeatureFXSR,
 564   FeatureNOPL,
 565   Feature64Bit,
 566   FeatureCMPXCHG16B,
 567   FeatureMOVBE,
 568   FeatureLEAForSP,
 569   FeatureSlowDivide32,
 570   FeatureSlowDivide64,
 571   FeatureSlowTwoMemOps,
 572   FeatureLEAUsesAG,
 573   FeaturePadShortFunctions,
 574   FeatureLAHFSAHF
 575 ]>;
 576 def : BonnellProc<"bonnell">;
 577 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 578
 579 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 580   ProcIntelSLM,
 581   FeatureX87,
 582   FeatureCMOV,
 583   FeatureMMX,
 584   FeatureSSE42,
 585   FeatureFXSR,
 586   FeatureNOPL,
 587   Feature64Bit,
 588   FeatureCMPXCHG16B,
 589   FeatureMOVBE,
 590   FeaturePOPCNT,
 591   FeaturePCLMUL,
 592   FeatureSlowDivide64,
 593   FeatureSlowTwoMemOps,
 594   FeaturePRFCHW,
 595   FeatureSlowLEA,
 596   FeatureSlowIncDec,
 597   FeatureSlowPMULLD,
 598   FeatureRDRAND,
 599   FeatureLAHFSAHF,
 600   FeaturePOPCNTFalseDeps
 601 ]>;
 602 def : SilvermontProc<"silvermont">;
 603 def : SilvermontProc<"slm">; // Legacy alias.
 604
 605 class ProcessorFeatures<list<SubtargetFeature> Inherited,
 606                         list<SubtargetFeature> NewFeatures> {
 607   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 608 }
 609
 610 class ProcModel<string Name, SchedMachineModel Model,
 611                 list<SubtargetFeature> ProcFeatures,
 612                 list<SubtargetFeature> OtherFeatures> :
 613   ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
 614
 615 def GLMFeatures : ProcessorFeatures<[], [
 616   FeatureX87,
 617   FeatureCMOV,
 618   FeatureMMX,
 619   FeatureSSE42,
 620   FeatureFXSR,
 621   FeatureNOPL,
 622   Feature64Bit,
 623   FeatureCMPXCHG16B,
 624   FeatureMOVBE,
 625   FeaturePOPCNT,
 626   FeaturePCLMUL,
 627   FeatureAES,
 628   FeaturePRFCHW,
 629   FeatureSlowTwoMemOps,
 630   FeatureSlowLEA,
 631   FeatureSlowIncDec,
 632   FeatureLAHFSAHF,
 633   FeatureMPX,
 634   FeatureSHA,
 635   FeatureRDRAND,
 636   FeatureRDSEED,
 637   FeatureXSAVE,
 638   FeatureXSAVEOPT,
 639   FeatureXSAVEC,
 640   FeatureXSAVES,
 641   FeatureCLFLUSHOPT,
 642   FeatureFSGSBase
 643 ]>;
 644
 645 class GoldmontProc<string Name> : ProcModel<Name, SLMModel,
 646       GLMFeatures.Value, [
 647   ProcIntelGLM,
 648   FeaturePOPCNTFalseDeps
 649 ]>;
 650 def : GoldmontProc<"goldmont">;
 651
 652 def GLPFeatures : ProcessorFeatures<GLMFeatures.Value, [
 653   FeaturePTWRITE,
 654   FeatureRDPID,
 655   FeatureSGX
 656 ]>;
 657
 658 class GoldmontPlusProc<string Name> : ProcModel<Name, SLMModel,
 659       GLPFeatures.Value, [
 660   ProcIntelGLP
 661 ]>;
 662 def : GoldmontPlusProc<"goldmont-plus">;
 663
 664 class TremontProc<string Name> : ProcModel<Name, SLMModel,
 665       GLPFeatures.Value, [
 666   ProcIntelTRM,
 667   FeatureCLDEMOTE,
 668   FeatureGFNI,
 669   FeatureMOVDIRI,
 670   FeatureMOVDIR64B,
 671   FeatureWAITPKG
 672 ]>;
 673 def : TremontProc<"tremont">;
 674
 675 // "Arrandale" along with corei3 and corei5
 676 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 677   FeatureX87,
 678   FeatureCMOV,
 679   FeatureMMX,
 680   FeatureSSE42,
 681   FeatureFXSR,
 682   FeatureNOPL,
 683   Feature64Bit,
 684   FeatureCMPXCHG16B,
 685   FeaturePOPCNT,
 686   FeatureLAHFSAHF,
 687   FeatureMacroFusion
 688 ]>;
 689 def : NehalemProc<"nehalem">;
 690 def : NehalemProc<"corei7">;
 691
 692 // Westmere is a similar machine to nehalem with some additional features.
 693 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 694 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 695   FeatureX87,
 696   FeatureCMOV,
 697   FeatureMMX,
 698   FeatureSSE42,
 699   FeatureFXSR,
 700   FeatureNOPL,
 701   Feature64Bit,
 702   FeatureCMPXCHG16B,
 703   FeaturePOPCNT,
 704   FeaturePCLMUL,
 705   FeatureLAHFSAHF,
 706   FeatureMacroFusion
 707 ]>;
 708 def : WestmereProc<"westmere">;
 709
 710 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 711 // rather than a superset.
 712 def SNBFeatures : ProcessorFeatures<[], [
 713   FeatureX87,
 714   FeatureCMOV,
 715   FeatureMMX,
 716   FeatureAVX,
 717   FeatureFXSR,
 718   FeatureNOPL,
 719   Feature64Bit,
 720   FeatureCMPXCHG16B,
 721   FeaturePOPCNT,
 722   FeatureSlowDivide64,
 723   FeaturePCLMUL,
 724   FeatureXSAVE,
 725   FeatureXSAVEOPT,
 726   FeatureLAHFSAHF,
 727   FeatureSlow3OpsLEA,
 728   FeatureFastScalarFSQRT,
 729   FeatureFastSHLDRotate,
 730   FeatureSlowIncDec,
 731   FeatureMacroFusion
 732 ]>;
 733
 734 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 735                                                SNBFeatures.Value, [
 736   FeatureSlowUAMem32,
 737   FeaturePOPCNTFalseDeps
 738 ]>;
 739 def : SandyBridgeProc<"sandybridge">;
 740 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 741
 742 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
 743   FeatureRDRAND,
 744   FeatureF16C,
 745   FeatureFSGSBase
 746 ]>;
 747
 748 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
 749                                              IVBFeatures.Value, [
 750   FeatureSlowUAMem32,
 751   FeaturePOPCNTFalseDeps
 752 ]>;
 753 def : IvyBridgeProc<"ivybridge">;
 754 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 755
 756 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
 757   FeatureAVX2,
 758   FeatureBMI,
 759   FeatureBMI2,
 760   FeatureERMSB,
 761   FeatureFMA,
 762   FeatureINVPCID,
 763   FeatureLZCNT,
 764   FeatureMOVBE,
 765   FeatureFastVariableShuffle
 766 ]>;
 767
 768 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
 769                                            HSWFeatures.Value, [
 770   ProcIntelHSW,
 771   FeaturePOPCNTFalseDeps,
 772   FeatureLZCNTFalseDeps
 773 ]>;
 774 def : HaswellProc<"haswell">;
 775 def : HaswellProc<"core-avx2">; // Legacy alias.
 776
 777 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
 778   FeatureADX,
 779   FeatureRDSEED,
 780   FeaturePRFCHW
 781 ]>;
 782 class BroadwellProc<string Name> : ProcModel<Name, BroadwellModel,
 783                                              BDWFeatures.Value, [
 784   ProcIntelBDW,
 785   FeaturePOPCNTFalseDeps,
 786   FeatureLZCNTFalseDeps
 787 ]>;
 788 def : BroadwellProc<"broadwell">;
 789
 790 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
 791   FeatureAES,
 792   FeatureMPX,
 793   FeatureRTM,
 794   FeatureXSAVEC,
 795   FeatureXSAVES,
 796   FeatureCLFLUSHOPT,
 797   FeatureFastVectorFSQRT
 798 ]>;
 799
 800 class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
 801                                                  SKLFeatures.Value, [
 802   ProcIntelSKL,
 803   FeatureHasFastGather,
 804   FeaturePOPCNTFalseDeps,
 805   FeatureSGX
 806 ]>;
 807 def : SkylakeClientProc<"skylake">;
 808
 809 def KNLFeatures : ProcessorFeatures<IVBFeatures.Value, [
 810   FeatureAVX512,
 811   FeatureERI,
 812   FeatureCDI,
 813   FeaturePFI,
 814   FeaturePREFETCHWT1,
 815   FeatureADX,
 816   FeatureRDSEED,
 817   FeatureMOVBE,
 818   FeatureLZCNT,
 819   FeatureBMI,
 820   FeatureBMI2,
 821   FeatureFMA,
 822   FeaturePRFCHW
 823 ]>;
 824
 825 // FIXME: define KNL model
 826 class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel,
 827                                                   KNLFeatures.Value, [
 828   ProcIntelKNL,
 829   FeatureSlowTwoMemOps,
 830   FeatureFastPartialYMMorZMMWrite,
 831   FeatureHasFastGather
 832 ]>;
 833 def : KnightsLandingProc<"knl">;
 834
 835 class KnightsMillProc<string Name> : ProcModel<Name, HaswellModel,
 836                                                KNLFeatures.Value, [
 837   ProcIntelKNL,
 838   FeatureSlowTwoMemOps,
 839   FeatureFastPartialYMMorZMMWrite,
 840   FeatureHasFastGather,
 841   FeatureVPOPCNTDQ
 842 ]>;
 843 def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features
 844
 845 def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
 846   FeatureAVX512,
 847   FeatureCDI,
 848   FeatureDQI,
 849   FeatureBWI,
 850   FeatureVLX,
 851   FeaturePKU,
 852   FeatureCLWB
 853 ]>;
 854
 855 class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
 856                                                  SKXFeatures.Value, [
 857   ProcIntelSKX,
 858   FeatureHasFastGather,
 859   FeaturePOPCNTFalseDeps
 860 ]>;
 861 def : SkylakeServerProc<"skylake-avx512">;
 862 def : SkylakeServerProc<"skx">; // Legacy alias.
 863
 864 def CNLFeatures : ProcessorFeatures<SKLFeatures.Value, [
 865   FeatureAVX512,
 866   FeatureCDI,
 867   FeatureDQI,
 868   FeatureBWI,
 869   FeatureVLX,
 870   FeaturePKU,
 871   FeatureVBMI,
 872   FeatureIFMA,
 873   FeatureSHA,
 874   FeatureSGX
 875 ]>;
 876
 877 class CannonlakeProc<string Name> : ProcModel<Name, SkylakeServerModel,
 878                                               CNLFeatures.Value, [
 879   ProcIntelCNL,
 880   FeatureHasFastGather
 881 ]>;
 882 def : CannonlakeProc<"cannonlake">;
 883
 884 def ICLFeatures : ProcessorFeatures<CNLFeatures.Value, [
 885   FeatureBITALG,
 886   FeatureVAES,
 887   FeatureVBMI2,
 888   FeatureVNNI,
 889   FeatureVPCLMULQDQ,
 890   FeatureVPOPCNTDQ,
 891   FeatureGFNI,
 892   FeatureCLWB,
 893   FeatureRDPID
 894 ]>;
 895
 896 class IcelakeClientProc<string Name> : ProcModel<Name, SkylakeServerModel,
 897                                                  ICLFeatures.Value, [
 898   ProcIntelICL,
 899   FeatureHasFastGather
 900 ]>;
 901 def : IcelakeClientProc<"icelake-client">;
 902
 903 class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
 904                                                  ICLFeatures.Value, [
 905   ProcIntelICX,
 906   FeaturePCONFIG,
 907   FeatureWBNOINVD,
 908   FeatureHasFastGather
 909 ]>;
 910 def : IcelakeServerProc<"icelake-server">;
 911
 912 // AMD CPUs.
 913
 914 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 915 def : Proc<"k6-2",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 916 def : Proc<"k6-3",            [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
 917
 918 foreach P = ["athlon", "athlon-tbird"] in {
 919   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, Feature3DNowA,
 920                  FeatureNOPL, FeatureSlowSHLD]>;
 921 }
 922
 923 foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
 924   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV, FeatureSSE1,
 925                  Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
 926 }
 927
 928 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
 929   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 930                  FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD,
 931                  FeatureCMOV]>;
 932 }
 933
 934 foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
 935   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
 936                  FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD,
 937                  FeatureCMOV, Feature64Bit]>;
 938 }
 939
 940 foreach P = ["amdfam10", "barcelona"] in {
 941   def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 942                  FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 943                  FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV, Feature64Bit]>;
 944 }
 945
 946 // Bobcat
 947 def : Proc<"btver1", [
 948   FeatureX87,
 949   FeatureCMOV,
 950   FeatureMMX,
 951   FeatureSSSE3,
 952   FeatureSSE4A,
 953   FeatureFXSR,
 954   FeatureNOPL,
 955   Feature64Bit,
 956   FeatureCMPXCHG16B,
 957   FeaturePRFCHW,
 958   FeatureLZCNT,
 959   FeaturePOPCNT,
 960   FeatureSlowSHLD,
 961   FeatureLAHFSAHF,
 962   FeatureFast15ByteNOP
 963 ]>;
 964
 965 // Jaguar
 966 def : ProcessorModel<"btver2", BtVer2Model, [
 967   FeatureX87,
 968   FeatureCMOV,
 969   FeatureMMX,
 970   FeatureAVX,
 971   FeatureFXSR,
 972   FeatureNOPL,
 973   FeatureSSE4A,
 974   Feature64Bit,
 975   FeatureCMPXCHG16B,
 976   FeaturePRFCHW,
 977   FeatureAES,
 978   FeaturePCLMUL,
 979   FeatureBMI,
 980   FeatureF16C,
 981   FeatureMOVBE,
 982   FeatureLZCNT,
 983   FeatureFastLZCNT,
 984   FeaturePOPCNT,
 985   FeatureXSAVE,
 986   FeatureXSAVEOPT,
 987   FeatureSlowSHLD,
 988   FeatureLAHFSAHF,
 989   FeatureFast15ByteNOP,
 990   FeatureFastPartialYMMorZMMWrite
 991 ]>;
 992
 993 // Bulldozer
 994 def : Proc<"bdver1", [
 995   FeatureX87,
 996   FeatureCMOV,
 997   FeatureXOP,
 998   FeatureFMA4,
 999   Feature64Bit,
1000   FeatureCMPXCHG16B,
1001   FeatureAES,
1002   FeaturePRFCHW,
1003   FeaturePCLMUL,
1004   FeatureMMX,
1005   FeatureAVX,
1006   FeatureFXSR,
1007   FeatureNOPL,
1008   FeatureSSE4A,
1009   FeatureLZCNT,
1010   FeaturePOPCNT,
1011   FeatureXSAVE,
1012   FeatureLWP,
1013   FeatureSlowSHLD,
1014   FeatureLAHFSAHF,
1015   FeatureFast11ByteNOP,
1016   FeatureMacroFusion
1017 ]>;
1018 // Piledriver
1019 def : Proc<"bdver2", [
1020   FeatureX87,
1021   FeatureCMOV,
1022   FeatureXOP,
1023   FeatureFMA4,
1024   Feature64Bit,
1025   FeatureCMPXCHG16B,
1026   FeatureAES,
1027   FeaturePRFCHW,
1028   FeaturePCLMUL,
1029   FeatureMMX,
1030   FeatureAVX,
1031   FeatureFXSR,
1032   FeatureNOPL,
1033   FeatureSSE4A,
1034   FeatureF16C,
1035   FeatureLZCNT,
1036   FeaturePOPCNT,
1037   FeatureXSAVE,
1038   FeatureBMI,
1039   FeatureTBM,
1040   FeatureLWP,
1041   FeatureFMA,
1042   FeatureSlowSHLD,
1043   FeatureLAHFSAHF,
1044   FeatureFast11ByteNOP,
1045   FeatureMacroFusion
1046 ]>;
1047
1048 // Steamroller
1049 def : Proc<"bdver3", [
1050   FeatureX87,
1051   FeatureCMOV,
1052   FeatureXOP,
1053   FeatureFMA4,
1054   Feature64Bit,
1055   FeatureCMPXCHG16B,
1056   FeatureAES,
1057   FeaturePRFCHW,
1058   FeaturePCLMUL,
1059   FeatureMMX,
1060   FeatureAVX,
1061   FeatureFXSR,
1062   FeatureNOPL,
1063   FeatureSSE4A,
1064   FeatureF16C,
1065   FeatureLZCNT,
1066   FeaturePOPCNT,
1067   FeatureXSAVE,
1068   FeatureBMI,
1069   FeatureTBM,
1070   FeatureLWP,
1071   FeatureFMA,
1072   FeatureXSAVEOPT,
1073   FeatureSlowSHLD,
1074   FeatureFSGSBase,
1075   FeatureLAHFSAHF,
1076   FeatureFast11ByteNOP,
1077   FeatureMacroFusion
1078 ]>;
1079
1080 // Excavator
1081 def : Proc<"bdver4", [
1082   FeatureX87,
1083   FeatureCMOV,
1084   FeatureMMX,
1085   FeatureAVX2,
1086   FeatureFXSR,
1087   FeatureNOPL,
1088   FeatureXOP,
1089   FeatureFMA4,
1090   Feature64Bit,
1091   FeatureCMPXCHG16B,
1092   FeatureAES,
1093   FeaturePRFCHW,
1094   FeaturePCLMUL,
1095   FeatureF16C,
1096   FeatureLZCNT,
1097   FeaturePOPCNT,
1098   FeatureXSAVE,
1099   FeatureBMI,
1100   FeatureBMI2,
1101   FeatureTBM,
1102   FeatureLWP,
1103   FeatureFMA,
1104   FeatureXSAVEOPT,
1105   FeatureSlowSHLD,
1106   FeatureFSGSBase,
1107   FeatureLAHFSAHF,
1108   FeatureFast11ByteNOP,
1109   FeatureMWAITX,
1110   FeatureMacroFusion
1111 ]>;
1112
1113 // Znver1
1114 def: ProcessorModel<"znver1", Znver1Model, [
1115   FeatureADX,
1116   FeatureAES,
1117   FeatureAVX2,
1118   FeatureBMI,
1119   FeatureBMI2,
1120   FeatureCLFLUSHOPT,
1121   FeatureCLZERO,
1122   FeatureCMOV,
1123   Feature64Bit,
1124   FeatureCMPXCHG16B,
1125   FeatureF16C,
1126   FeatureFMA,
1127   FeatureFSGSBase,
1128   FeatureFXSR,
1129   FeatureNOPL,
1130   FeatureFastLZCNT,
1131   FeatureLAHFSAHF,
1132   FeatureLZCNT,
1133   FeatureFast15ByteNOP,
1134   FeatureMacroFusion,
1135   FeatureMMX,
1136   FeatureMOVBE,
1137   FeatureMWAITX,
1138   FeaturePCLMUL,
1139   FeaturePOPCNT,
1140   FeaturePRFCHW,
1141   FeatureRDRAND,
1142   FeatureRDSEED,
1143   FeatureSHA,
1144   FeatureSSE4A,
1145   FeatureSlowSHLD,
1146   FeatureX87,
1147   FeatureXSAVE,
1148   FeatureXSAVEC,
1149   FeatureXSAVEOPT,
1150   FeatureXSAVES]>;
1151
1152 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>;
1153
1154 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
1155 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1156 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1157 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
1158                                FeatureSSE1, FeatureFXSR, FeatureCMOV]>;
1159
1160 // We also provide a generic 64-bit specific x86 processor model which tries to
1161 // be good for modern chips without enabling instruction set encodings past the
1162 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1163 // modern 64-bit x86 chip, and enables features that are generally beneficial.
1164 //
1165 // We currently use the Sandy Bridge model as the default scheduling model as
1166 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1167 // covers a huge swath of x86 processors. If there are specific scheduling
1168 // knobs which need to be tuned differently for AMD chips, we might consider
1169 // forming a common base for them.
1170 def : ProcessorModel<"x86-64", SandyBridgeModel, [
1171   FeatureX87,
1172   FeatureCMOV,
1173   FeatureMMX,
1174   FeatureSSE2,
1175   FeatureFXSR,
1176   FeatureNOPL,
1177   Feature64Bit,
1178   FeatureSlow3OpsLEA,
1179   FeatureSlowIncDec,
1180   FeatureMacroFusion
1181 ]>;
1182
1183 //===----------------------------------------------------------------------===//
1184 // Calling Conventions
1185 //===----------------------------------------------------------------------===//
1186
1187 include "X86CallingConv.td"
1188
1189
1190 //===----------------------------------------------------------------------===//
1191 // Assembly Parser
1192 //===----------------------------------------------------------------------===//
1193
1194 def ATTAsmParserVariant : AsmParserVariant {
1195   int Variant = 0;
1196
1197   // Variant name.
1198   string Name = "att";
1199
1200   // Discard comments in assembly strings.
1201   string CommentDelimiter = "#";
1202
1203   // Recognize hard coded registers.
1204   string RegisterPrefix = "%";
1205 }
1206
1207 def IntelAsmParserVariant : AsmParserVariant {
1208   int Variant = 1;
1209
1210   // Variant name.
1211   string Name = "intel";
1212
1213   // Discard comments in assembly strings.
1214   string CommentDelimiter = ";";
1215
1216   // Recognize hard coded registers.
1217   string RegisterPrefix = "";
1218 }
1219
1220 //===----------------------------------------------------------------------===//
1221 // Assembly Printers
1222 //===----------------------------------------------------------------------===//
1223
1224 // The X86 target supports two different syntaxes for emitting machine code.
1225 // This is controlled by the -x86-asm-syntax={att|intel}
1226 def ATTAsmWriter : AsmWriter {
1227   string AsmWriterClassName  = "ATTInstPrinter";
1228   int Variant = 0;
1229 }
1230 def IntelAsmWriter : AsmWriter {
1231   string AsmWriterClassName  = "IntelInstPrinter";
1232   int Variant = 1;
1233 }
1234
1235 def X86 : Target {
1236   // Information about the instructions...
1237   let InstructionSet = X86InstrInfo;
1238   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1239   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1240   let AllowRegisterRenaming = 1;
1241 }
1242
1243 //===----------------------------------------------------------------------===//
1244 // Pfm Counters
1245 //===----------------------------------------------------------------------===//
1246
1247 include "X86PfmCounters.td"