lib/Target/X86/X86InstrBuilder.h

   1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file exposes functions that may be used with BuildMI from the
  11 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
  12 //
  13 // The BuildMem function may be used with the BuildMI function to add entire
  14 // memory references in a single, typed, function call.  X86 memory references
  15 // can be very complex expressions (described in the README), so wrapping them
  16 // up behind an easier to use interface makes sense.  Descriptions of the
  17 // functions are included below.
  18 //
  19 // For reference, the order of operands for memory references is:
  20 // (Operand), Base, Scale, Index, Displacement.
  21 //
  22 //===----------------------------------------------------------------------===//
  23
  24 #ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
  25 #define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
  26
  27 #include "llvm/ADT/SmallVector.h"
  28 #include "llvm/CodeGen/MachineFrameInfo.h"
  29 #include "llvm/CodeGen/MachineFunction.h"
  30 #include "llvm/CodeGen/MachineInstr.h"
  31 #include "llvm/CodeGen/MachineInstrBuilder.h"
  32 #include "llvm/CodeGen/MachineMemOperand.h"
  33 #include "llvm/CodeGen/MachineOperand.h"
  34 #include "llvm/MC/MCInstrDesc.h"
  35 #include <cassert>
  36
  37 namespace llvm {
  38
  39 /// X86AddressMode - This struct holds a generalized full x86 address mode.
  40 /// The base register can be a frame index, which will eventually be replaced
  41 /// with BP or SP and Disp being offsetted accordingly.  The displacement may
  42 /// also include the offset of a global value.
  43 struct X86AddressMode {
  44   enum {
  45     RegBase,
  46     FrameIndexBase
  47   } BaseType;
  48
  49   union {
  50     unsigned Reg;
  51     int FrameIndex;
  52   } Base;
  53
  54   unsigned Scale;
  55   unsigned IndexReg;
  56   int Disp;
  57   const GlobalValue *GV;
  58   unsigned GVOpFlags;
  59
  60   X86AddressMode()
  61     : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
  62       GVOpFlags(0) {
  63     Base.Reg = 0;
  64   }
  65
  66   void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
  67     assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
  68
  69     if (BaseType == X86AddressMode::RegBase)
  70       MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
  71                                              false, false, false, 0, false));
  72     else {
  73       assert(BaseType == X86AddressMode::FrameIndexBase);
  74       MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
  75     }
  76
  77     MO.push_back(MachineOperand::CreateImm(Scale));
  78     MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
  79                                            false, false, 0, false));
  80
  81     if (GV)
  82       MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
  83     else
  84       MO.push_back(MachineOperand::CreateImm(Disp));
  85
  86     MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
  87                                            false, 0, false));
  88   }
  89 };
  90
  91 /// Compute the addressing mode from an machine instruction starting with the
  92 /// given operand.
  93 static inline X86AddressMode getAddressFromInstr(const MachineInstr *MI,
  94                                                  unsigned Operand) {
  95   X86AddressMode AM;
  96   const MachineOperand &Op0 = MI->getOperand(Operand);
  97   if (Op0.isReg()) {
  98     AM.BaseType = X86AddressMode::RegBase;
  99     AM.Base.Reg = Op0.getReg();
 100   } else {
 101     AM.BaseType = X86AddressMode::FrameIndexBase;
 102     AM.Base.FrameIndex = Op0.getIndex();
 103   }
 104
 105   const MachineOperand &Op1 = MI->getOperand(Operand + 1);
 106   AM.Scale = Op1.getImm();
 107
 108   const MachineOperand &Op2 = MI->getOperand(Operand + 2);
 109   AM.IndexReg = Op2.getReg();
 110
 111   const MachineOperand &Op3 = MI->getOperand(Operand + 3);
 112   if (Op3.isGlobal())
 113     AM.GV = Op3.getGlobal();
 114   else
 115     AM.Disp = Op3.getImm();
 116
 117   return AM;
 118 }
 119
 120 /// addDirectMem - This function is used to add a direct memory reference to the
 121 /// current instruction -- that is, a dereference of an address in a register,
 122 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
 123 ///
 124 static inline const MachineInstrBuilder &
 125 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
 126   // Because memory references are always represented with five
 127   // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
 128   return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
 129 }
 130
 131 /// Replace the address used in the instruction with the direct memory
 132 /// reference.
 133 static inline void setDirectAddressInInstr(MachineInstr *MI, unsigned Operand,
 134                                            unsigned Reg) {
 135   // Direct memory address is in a form of: Reg, 1 (Scale), NoReg, 0, NoReg.
 136   MI->getOperand(Operand).setReg(Reg);
 137   MI->getOperand(Operand + 1).setImm(1);
 138   MI->getOperand(Operand + 2).setReg(0);
 139   MI->getOperand(Operand + 3).setImm(0);
 140   MI->getOperand(Operand + 4).setReg(0);
 141 }
 142
 143 static inline const MachineInstrBuilder &
 144 addOffset(const MachineInstrBuilder &MIB, int Offset) {
 145   return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
 146 }
 147
 148 static inline const MachineInstrBuilder &
 149 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
 150   return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
 151 }
 152
 153 /// addRegOffset - This function is used to add a memory reference of the form
 154 /// [Reg + Offset], i.e., one with no scale or index, but with a
 155 /// displacement. An example is: DWORD PTR [EAX + 4].
 156 ///
 157 static inline const MachineInstrBuilder &
 158 addRegOffset(const MachineInstrBuilder &MIB,
 159              unsigned Reg, bool isKill, int Offset) {
 160   return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
 161 }
 162
 163 /// addRegReg - This function is used to add a memory reference of the form:
 164 /// [Reg + Reg].
 165 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
 166                                             unsigned Reg1, bool isKill1,
 167                                             unsigned Reg2, bool isKill2) {
 168   return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
 169     .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
 170 }
 171
 172 static inline const MachineInstrBuilder &
 173 addFullAddress(const MachineInstrBuilder &MIB,
 174                const X86AddressMode &AM) {
 175   assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
 176
 177   if (AM.BaseType == X86AddressMode::RegBase)
 178     MIB.addReg(AM.Base.Reg);
 179   else {
 180     assert(AM.BaseType == X86AddressMode::FrameIndexBase);
 181     MIB.addFrameIndex(AM.Base.FrameIndex);
 182   }
 183
 184   MIB.addImm(AM.Scale).addReg(AM.IndexReg);
 185   if (AM.GV)
 186     MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
 187   else
 188     MIB.addImm(AM.Disp);
 189
 190   return MIB.addReg(0);
 191 }
 192
 193 /// addFrameReference - This function is used to add a reference to the base of
 194 /// an abstract object on the stack frame of the current function.  This
 195 /// reference has base register as the FrameIndex offset until it is resolved.
 196 /// This allows a constant offset to be specified as well...
 197 ///
 198 static inline const MachineInstrBuilder &
 199 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
 200   MachineInstr *MI = MIB;
 201   MachineFunction &MF = *MI->getParent()->getParent();
 202   MachineFrameInfo &MFI = MF.getFrameInfo();
 203   const MCInstrDesc &MCID = MI->getDesc();
 204   auto Flags = MachineMemOperand::MONone;
 205   if (MCID.mayLoad())
 206     Flags |= MachineMemOperand::MOLoad;
 207   if (MCID.mayStore())
 208     Flags |= MachineMemOperand::MOStore;
 209   MachineMemOperand *MMO = MF.getMachineMemOperand(
 210       MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
 211       MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
 212   return addOffset(MIB.addFrameIndex(FI), Offset)
 213             .addMemOperand(MMO);
 214 }
 215
 216 /// addConstantPoolReference - This function is used to add a reference to the
 217 /// base of a constant value spilled to the per-function constant pool.  The
 218 /// reference uses the abstract ConstantPoolIndex which is retained until
 219 /// either machine code emission or assembly output. In PIC mode on x86-32,
 220 /// the GlobalBaseReg parameter can be used to make this a
 221 /// GlobalBaseReg-relative reference.
 222 ///
 223 static inline const MachineInstrBuilder &
 224 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
 225                          unsigned GlobalBaseReg, unsigned char OpFlags) {
 226   //FIXME: factor this
 227   return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
 228     .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
 229 }
 230
 231 } // end namespace llvm
 232
 233 #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H