lib/Target/X86/X86LegalizerInfo.cpp

   1 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 /// \file
  10 /// This file implements the targeting of the Machinelegalizer class for X86.
  11 /// \todo This should be generated by TableGen.
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86LegalizerInfo.h"
  15 #include "X86Subtarget.h"
  16 #include "X86TargetMachine.h"
  17 #include "llvm/CodeGen/TargetOpcodes.h"
  18 #include "llvm/CodeGen/ValueTypes.h"
  19 #include "llvm/IR/DerivedTypes.h"
  20 #include "llvm/IR/Type.h"
  21
  22 using namespace llvm;
  23 using namespace TargetOpcode;
  24 using namespace LegalizeActions;
  25
  26 /// FIXME: The following static functions are SizeChangeStrategy functions
  27 /// that are meant to temporarily mimic the behaviour of the old legalization
  28 /// based on doubling/halving non-legal types as closely as possible. This is
  29 /// not entirly possible as only legalizing the types that are exactly a power
  30 /// of 2 times the size of the legal types would require specifying all those
  31 /// sizes explicitly.
  32 /// In practice, not specifying those isn't a problem, and the below functions
  33 /// should disappear quickly as we add support for legalizing non-power-of-2
  34 /// sized types further.
  35 static void
  36 addAndInterleaveWithUnsupported(LegalizerInfo::SizeAndActionsVec &result,
  37                                 const LegalizerInfo::SizeAndActionsVec &v) {
  38   for (unsigned i = 0; i < v.size(); ++i) {
  39     result.push_back(v[i]);
  40     if (i + 1 < v[i].first && i + 1 < v.size() &&
  41         v[i + 1].first != v[i].first + 1)
  42       result.push_back({v[i].first + 1, Unsupported});
  43   }
  44 }
  45
  46 static LegalizerInfo::SizeAndActionsVec
  47 widen_1(const LegalizerInfo::SizeAndActionsVec &v) {
  48   assert(v.size() >= 1);
  49   assert(v[0].first > 1);
  50   LegalizerInfo::SizeAndActionsVec result = {{1, WidenScalar},
  51                                              {2, Unsupported}};
  52   addAndInterleaveWithUnsupported(result, v);
  53   auto Largest = result.back().first;
  54   result.push_back({Largest + 1, Unsupported});
  55   return result;
  56 }
  57
  58 X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
  59                                    const X86TargetMachine &TM)
  60     : Subtarget(STI), TM(TM) {
  61
  62   setLegalizerInfo32bit();
  63   setLegalizerInfo64bit();
  64   setLegalizerInfoSSE1();
  65   setLegalizerInfoSSE2();
  66   setLegalizerInfoSSE41();
  67   setLegalizerInfoAVX();
  68   setLegalizerInfoAVX2();
  69   setLegalizerInfoAVX512();
  70   setLegalizerInfoAVX512DQ();
  71   setLegalizerInfoAVX512BW();
  72
  73   setLegalizeScalarToDifferentSizeStrategy(G_PHI, 0, widen_1);
  74   for (unsigned BinOp : {G_SUB, G_MUL, G_AND, G_OR, G_XOR})
  75     setLegalizeScalarToDifferentSizeStrategy(BinOp, 0, widen_1);
  76   for (unsigned MemOp : {G_LOAD, G_STORE})
  77     setLegalizeScalarToDifferentSizeStrategy(MemOp, 0,
  78        narrowToSmallerAndWidenToSmallest);
  79   setLegalizeScalarToDifferentSizeStrategy(
  80       G_GEP, 1, widenToLargerTypesUnsupportedOtherwise);
  81   setLegalizeScalarToDifferentSizeStrategy(
  82       G_CONSTANT, 0, widenToLargerTypesAndNarrowToLargest);
  83
  84   computeTables();
  85   verify(*STI.getInstrInfo());
  86 }
  87
  88 void X86LegalizerInfo::setLegalizerInfo32bit() {
  89
  90   const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
  91   const LLT s1 = LLT::scalar(1);
  92   const LLT s8 = LLT::scalar(8);
  93   const LLT s16 = LLT::scalar(16);
  94   const LLT s32 = LLT::scalar(32);
  95   const LLT s64 = LLT::scalar(64);
  96   const LLT s128 = LLT::scalar(128);
  97
  98   for (auto Ty : {p0, s1, s8, s16, s32})
  99     setAction({G_IMPLICIT_DEF, Ty}, Legal);
 100
 101   for (auto Ty : {s8, s16, s32, p0})
 102     setAction({G_PHI, Ty}, Legal);
 103
 104   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
 105     for (auto Ty : {s8, s16, s32})
 106       setAction({BinOp, Ty}, Legal);
 107
 108   for (unsigned Op : {G_UADDE}) {
 109     setAction({Op, s32}, Legal);
 110     setAction({Op, 1, s1}, Legal);
 111   }
 112
 113   for (unsigned MemOp : {G_LOAD, G_STORE}) {
 114     for (auto Ty : {s8, s16, s32, p0})
 115       setAction({MemOp, Ty}, Legal);
 116
 117     // And everything's fine in addrspace 0.
 118     setAction({MemOp, 1, p0}, Legal);
 119   }
 120
 121   // Pointer-handling
 122   setAction({G_FRAME_INDEX, p0}, Legal);
 123   setAction({G_GLOBAL_VALUE, p0}, Legal);
 124
 125   setAction({G_GEP, p0}, Legal);
 126   setAction({G_GEP, 1, s32}, Legal);
 127
 128   if (!Subtarget.is64Bit()) {
 129     getActionDefinitionsBuilder(G_PTRTOINT)
 130         .legalForCartesianProduct({s1, s8, s16, s32}, {p0})
 131         .maxScalar(0, s32)
 132         .widenScalarToNextPow2(0, /*Min*/ 8);
 133     getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
 134
 135     // Shifts and SDIV
 136     getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
 137         .legalFor({s8, s16, s32})
 138         .clampScalar(0, s8, s32);
 139   }
 140
 141   // Control-flow
 142   setAction({G_BRCOND, s1}, Legal);
 143
 144   // Constants
 145   for (auto Ty : {s8, s16, s32, p0})
 146     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
 147
 148   // Extensions
 149   for (auto Ty : {s8, s16, s32}) {
 150     setAction({G_ZEXT, Ty}, Legal);
 151     setAction({G_SEXT, Ty}, Legal);
 152     setAction({G_ANYEXT, Ty}, Legal);
 153   }
 154   setAction({G_ANYEXT, s128}, Legal);
 155
 156   // Comparison
 157   setAction({G_ICMP, s1}, Legal);
 158
 159   for (auto Ty : {s8, s16, s32, p0})
 160     setAction({G_ICMP, 1, Ty}, Legal);
 161
 162   // Merge/Unmerge
 163   for (const auto &Ty : {s16, s32, s64}) {
 164     setAction({G_MERGE_VALUES, Ty}, Legal);
 165     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
 166   }
 167   for (const auto &Ty : {s8, s16, s32}) {
 168     setAction({G_MERGE_VALUES, 1, Ty}, Legal);
 169     setAction({G_UNMERGE_VALUES, Ty}, Legal);
 170   }
 171 }
 172
 173 void X86LegalizerInfo::setLegalizerInfo64bit() {
 174
 175   if (!Subtarget.is64Bit())
 176     return;
 177
 178   const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
 179   const LLT s1 = LLT::scalar(1);
 180   const LLT s8 = LLT::scalar(8);
 181   const LLT s16 = LLT::scalar(16);
 182   const LLT s32 = LLT::scalar(32);
 183   const LLT s64 = LLT::scalar(64);
 184   const LLT s128 = LLT::scalar(128);
 185
 186   setAction({G_IMPLICIT_DEF, s64}, Legal);
 187   // Need to have that, as tryFoldImplicitDef will create this pattern:
 188   // s128 = EXTEND (G_IMPLICIT_DEF s32/s64) -> s128 = G_IMPLICIT_DEF
 189   setAction({G_IMPLICIT_DEF, s128}, Legal);
 190
 191   setAction({G_PHI, s64}, Legal);
 192
 193   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
 194     setAction({BinOp, s64}, Legal);
 195
 196   for (unsigned MemOp : {G_LOAD, G_STORE})
 197     setAction({MemOp, s64}, Legal);
 198
 199   // Pointer-handling
 200   setAction({G_GEP, 1, s64}, Legal);
 201   getActionDefinitionsBuilder(G_PTRTOINT)
 202       .legalForCartesianProduct({s1, s8, s16, s32, s64}, {p0})
 203       .maxScalar(0, s64)
 204       .widenScalarToNextPow2(0, /*Min*/ 8);
 205   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s64}});
 206
 207   // Constants
 208   setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
 209
 210   // Extensions
 211   for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
 212     setAction({extOp, s64}, Legal);
 213   }
 214
 215   getActionDefinitionsBuilder(G_SITOFP)
 216     .legalForCartesianProduct({s32, s64})
 217       .clampScalar(1, s32, s64)
 218       .widenScalarToNextPow2(1)
 219       .clampScalar(0, s32, s64)
 220       .widenScalarToNextPow2(0);
 221
 222   getActionDefinitionsBuilder(G_FPTOSI)
 223       .legalForCartesianProduct({s32, s64})
 224       .clampScalar(1, s32, s64)
 225       .widenScalarToNextPow2(0)
 226       .clampScalar(0, s32, s64)
 227       .widenScalarToNextPow2(1);
 228
 229   // Comparison
 230   setAction({G_ICMP, 1, s64}, Legal);
 231
 232   getActionDefinitionsBuilder(G_FCMP)
 233       .legalForCartesianProduct({s8}, {s32, s64})
 234       .clampScalar(0, s8, s8)
 235       .clampScalar(1, s32, s64)
 236       .widenScalarToNextPow2(1);
 237
 238   // Shifts and SDIV
 239   getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
 240     .legalFor({s8, s16, s32, s64})
 241     .clampScalar(0, s8, s64);
 242
 243   // Merge/Unmerge
 244   setAction({G_MERGE_VALUES, s128}, Legal);
 245   setAction({G_UNMERGE_VALUES, 1, s128}, Legal);
 246   setAction({G_MERGE_VALUES, 1, s128}, Legal);
 247   setAction({G_UNMERGE_VALUES, s128}, Legal);
 248 }
 249
 250 void X86LegalizerInfo::setLegalizerInfoSSE1() {
 251   if (!Subtarget.hasSSE1())
 252     return;
 253
 254   const LLT s32 = LLT::scalar(32);
 255   const LLT s64 = LLT::scalar(64);
 256   const LLT v4s32 = LLT::vector(4, 32);
 257   const LLT v2s64 = LLT::vector(2, 64);
 258
 259   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
 260     for (auto Ty : {s32, v4s32})
 261       setAction({BinOp, Ty}, Legal);
 262
 263   for (unsigned MemOp : {G_LOAD, G_STORE})
 264     for (auto Ty : {v4s32, v2s64})
 265       setAction({MemOp, Ty}, Legal);
 266
 267   // Constants
 268   setAction({TargetOpcode::G_FCONSTANT, s32}, Legal);
 269
 270   // Merge/Unmerge
 271   for (const auto &Ty : {v4s32, v2s64}) {
 272     setAction({G_MERGE_VALUES, Ty}, Legal);
 273     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
 274   }
 275   setAction({G_MERGE_VALUES, 1, s64}, Legal);
 276   setAction({G_UNMERGE_VALUES, s64}, Legal);
 277 }
 278
 279 void X86LegalizerInfo::setLegalizerInfoSSE2() {
 280   if (!Subtarget.hasSSE2())
 281     return;
 282
 283   const LLT s32 = LLT::scalar(32);
 284   const LLT s64 = LLT::scalar(64);
 285   const LLT v16s8 = LLT::vector(16, 8);
 286   const LLT v8s16 = LLT::vector(8, 16);
 287   const LLT v4s32 = LLT::vector(4, 32);
 288   const LLT v2s64 = LLT::vector(2, 64);
 289
 290   const LLT v32s8 = LLT::vector(32, 8);
 291   const LLT v16s16 = LLT::vector(16, 16);
 292   const LLT v8s32 = LLT::vector(8, 32);
 293   const LLT v4s64 = LLT::vector(4, 64);
 294
 295   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
 296     for (auto Ty : {s64, v2s64})
 297       setAction({BinOp, Ty}, Legal);
 298
 299   for (unsigned BinOp : {G_ADD, G_SUB})
 300     for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
 301       setAction({BinOp, Ty}, Legal);
 302
 303   setAction({G_MUL, v8s16}, Legal);
 304
 305   setAction({G_FPEXT, s64}, Legal);
 306   setAction({G_FPEXT, 1, s32}, Legal);
 307
 308   setAction({G_FPTRUNC, s32}, Legal);
 309   setAction({G_FPTRUNC, 1, s64}, Legal);
 310
 311   // Constants
 312   setAction({TargetOpcode::G_FCONSTANT, s64}, Legal);
 313
 314   // Merge/Unmerge
 315   for (const auto &Ty :
 316        {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
 317     setAction({G_MERGE_VALUES, Ty}, Legal);
 318     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
 319   }
 320   for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
 321     setAction({G_MERGE_VALUES, 1, Ty}, Legal);
 322     setAction({G_UNMERGE_VALUES, Ty}, Legal);
 323   }
 324 }
 325
 326 void X86LegalizerInfo::setLegalizerInfoSSE41() {
 327   if (!Subtarget.hasSSE41())
 328     return;
 329
 330   const LLT v4s32 = LLT::vector(4, 32);
 331
 332   setAction({G_MUL, v4s32}, Legal);
 333 }
 334
 335 void X86LegalizerInfo::setLegalizerInfoAVX() {
 336   if (!Subtarget.hasAVX())
 337     return;
 338
 339   const LLT v16s8 = LLT::vector(16, 8);
 340   const LLT v8s16 = LLT::vector(8, 16);
 341   const LLT v4s32 = LLT::vector(4, 32);
 342   const LLT v2s64 = LLT::vector(2, 64);
 343
 344   const LLT v32s8 = LLT::vector(32, 8);
 345   const LLT v64s8 = LLT::vector(64, 8);
 346   const LLT v16s16 = LLT::vector(16, 16);
 347   const LLT v32s16 = LLT::vector(32, 16);
 348   const LLT v8s32 = LLT::vector(8, 32);
 349   const LLT v16s32 = LLT::vector(16, 32);
 350   const LLT v4s64 = LLT::vector(4, 64);
 351   const LLT v8s64 = LLT::vector(8, 64);
 352
 353   for (unsigned MemOp : {G_LOAD, G_STORE})
 354     for (auto Ty : {v8s32, v4s64})
 355       setAction({MemOp, Ty}, Legal);
 356
 357   for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
 358     setAction({G_INSERT, Ty}, Legal);
 359     setAction({G_EXTRACT, 1, Ty}, Legal);
 360   }
 361   for (auto Ty : {v16s8, v8s16, v4s32, v2s64}) {
 362     setAction({G_INSERT, 1, Ty}, Legal);
 363     setAction({G_EXTRACT, Ty}, Legal);
 364   }
 365   // Merge/Unmerge
 366   for (const auto &Ty :
 367        {v32s8, v64s8, v16s16, v32s16, v8s32, v16s32, v4s64, v8s64}) {
 368     setAction({G_MERGE_VALUES, Ty}, Legal);
 369     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
 370   }
 371   for (const auto &Ty :
 372        {v16s8, v32s8, v8s16, v16s16, v4s32, v8s32, v2s64, v4s64}) {
 373     setAction({G_MERGE_VALUES, 1, Ty}, Legal);
 374     setAction({G_UNMERGE_VALUES, Ty}, Legal);
 375   }
 376 }
 377
 378 void X86LegalizerInfo::setLegalizerInfoAVX2() {
 379   if (!Subtarget.hasAVX2())
 380     return;
 381
 382   const LLT v32s8 = LLT::vector(32, 8);
 383   const LLT v16s16 = LLT::vector(16, 16);
 384   const LLT v8s32 = LLT::vector(8, 32);
 385   const LLT v4s64 = LLT::vector(4, 64);
 386
 387   const LLT v64s8 = LLT::vector(64, 8);
 388   const LLT v32s16 = LLT::vector(32, 16);
 389   const LLT v16s32 = LLT::vector(16, 32);
 390   const LLT v8s64 = LLT::vector(8, 64);
 391
 392   for (unsigned BinOp : {G_ADD, G_SUB})
 393     for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
 394       setAction({BinOp, Ty}, Legal);
 395
 396   for (auto Ty : {v16s16, v8s32})
 397     setAction({G_MUL, Ty}, Legal);
 398
 399   // Merge/Unmerge
 400   for (const auto &Ty : {v64s8, v32s16, v16s32, v8s64}) {
 401     setAction({G_MERGE_VALUES, Ty}, Legal);
 402     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
 403   }
 404   for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
 405     setAction({G_MERGE_VALUES, 1, Ty}, Legal);
 406     setAction({G_UNMERGE_VALUES, Ty}, Legal);
 407   }
 408 }
 409
 410 void X86LegalizerInfo::setLegalizerInfoAVX512() {
 411   if (!Subtarget.hasAVX512())
 412     return;
 413
 414   const LLT v16s8 = LLT::vector(16, 8);
 415   const LLT v8s16 = LLT::vector(8, 16);
 416   const LLT v4s32 = LLT::vector(4, 32);
 417   const LLT v2s64 = LLT::vector(2, 64);
 418
 419   const LLT v32s8 = LLT::vector(32, 8);
 420   const LLT v16s16 = LLT::vector(16, 16);
 421   const LLT v8s32 = LLT::vector(8, 32);
 422   const LLT v4s64 = LLT::vector(4, 64);
 423
 424   const LLT v64s8 = LLT::vector(64, 8);
 425   const LLT v32s16 = LLT::vector(32, 16);
 426   const LLT v16s32 = LLT::vector(16, 32);
 427   const LLT v8s64 = LLT::vector(8, 64);
 428
 429   for (unsigned BinOp : {G_ADD, G_SUB})
 430     for (auto Ty : {v16s32, v8s64})
 431       setAction({BinOp, Ty}, Legal);
 432
 433   setAction({G_MUL, v16s32}, Legal);
 434
 435   for (unsigned MemOp : {G_LOAD, G_STORE})
 436     for (auto Ty : {v16s32, v8s64})
 437       setAction({MemOp, Ty}, Legal);
 438
 439   for (auto Ty : {v64s8, v32s16, v16s32, v8s64}) {
 440     setAction({G_INSERT, Ty}, Legal);
 441     setAction({G_EXTRACT, 1, Ty}, Legal);
 442   }
 443   for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64}) {
 444     setAction({G_INSERT, 1, Ty}, Legal);
 445     setAction({G_EXTRACT, Ty}, Legal);
 446   }
 447
 448   /************ VLX *******************/
 449   if (!Subtarget.hasVLX())
 450     return;
 451
 452   for (auto Ty : {v4s32, v8s32})
 453     setAction({G_MUL, Ty}, Legal);
 454 }
 455
 456 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
 457   if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
 458     return;
 459
 460   const LLT v8s64 = LLT::vector(8, 64);
 461
 462   setAction({G_MUL, v8s64}, Legal);
 463
 464   /************ VLX *******************/
 465   if (!Subtarget.hasVLX())
 466     return;
 467
 468   const LLT v2s64 = LLT::vector(2, 64);
 469   const LLT v4s64 = LLT::vector(4, 64);
 470
 471   for (auto Ty : {v2s64, v4s64})
 472     setAction({G_MUL, Ty}, Legal);
 473 }
 474
 475 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
 476   if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
 477     return;
 478
 479   const LLT v64s8 = LLT::vector(64, 8);
 480   const LLT v32s16 = LLT::vector(32, 16);
 481
 482   for (unsigned BinOp : {G_ADD, G_SUB})
 483     for (auto Ty : {v64s8, v32s16})
 484       setAction({BinOp, Ty}, Legal);
 485
 486   setAction({G_MUL, v32s16}, Legal);
 487
 488   /************ VLX *******************/
 489   if (!Subtarget.hasVLX())
 490     return;
 491
 492   const LLT v8s16 = LLT::vector(8, 16);
 493   const LLT v16s16 = LLT::vector(16, 16);
 494
 495   for (auto Ty : {v8s16, v16s16})
 496     setAction({G_MUL, Ty}, Legal);
 497 }