lib/Target/X86/X86MacroFusion.cpp

   1 //===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file This file contains the X86 implementation of the DAG scheduling
  11 /// mutation to pair instructions back to back.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86MacroFusion.h"
  16 #include "X86Subtarget.h"
  17 #include "llvm/CodeGen/MacroFusion.h"
  18 #include "llvm/CodeGen/TargetInstrInfo.h"
  19
  20 using namespace llvm;
  21
  22 /// Check if the instr pair, FirstMI and SecondMI, should be fused
  23 /// together. Given SecondMI, when FirstMI is unspecified, then check if
  24 /// SecondMI may be part of a fused pair at all.
  25 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
  26                                    const TargetSubtargetInfo &TSI,
  27                                    const MachineInstr *FirstMI,
  28                                    const MachineInstr &SecondMI) {
  29   const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
  30   // Check if this processor supports macro-fusion.
  31   if (!ST.hasMacroFusion())
  32     return false;
  33
  34   enum {
  35     FuseTest,
  36     FuseCmp,
  37     FuseInc
  38   } FuseKind;
  39
  40   unsigned FirstOpcode = FirstMI
  41                          ? FirstMI->getOpcode()
  42                          : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
  43   unsigned SecondOpcode = SecondMI.getOpcode();
  44
  45   switch (SecondOpcode) {
  46   default:
  47     return false;
  48   case X86::JE_1:
  49   case X86::JNE_1:
  50   case X86::JL_1:
  51   case X86::JLE_1:
  52   case X86::JG_1:
  53   case X86::JGE_1:
  54     FuseKind = FuseInc;
  55     break;
  56   case X86::JB_1:
  57   case X86::JBE_1:
  58   case X86::JA_1:
  59   case X86::JAE_1:
  60     FuseKind = FuseCmp;
  61     break;
  62   case X86::JS_1:
  63   case X86::JNS_1:
  64   case X86::JP_1:
  65   case X86::JNP_1:
  66   case X86::JO_1:
  67   case X86::JNO_1:
  68     FuseKind = FuseTest;
  69     break;
  70   }
  71
  72   switch (FirstOpcode) {
  73   default:
  74     return false;
  75   case X86::TEST8rr:
  76   case X86::TEST16rr:
  77   case X86::TEST32rr:
  78   case X86::TEST64rr:
  79   case X86::TEST8ri:
  80   case X86::TEST16ri:
  81   case X86::TEST32ri:
  82   case X86::TEST64ri32:
  83   case X86::TEST8mr:
  84   case X86::TEST16mr:
  85   case X86::TEST32mr:
  86   case X86::TEST64mr:
  87   case X86::AND16ri:
  88   case X86::AND16ri8:
  89   case X86::AND16rm:
  90   case X86::AND16rr:
  91   case X86::AND32ri:
  92   case X86::AND32ri8:
  93   case X86::AND32rm:
  94   case X86::AND32rr:
  95   case X86::AND64ri32:
  96   case X86::AND64ri8:
  97   case X86::AND64rm:
  98   case X86::AND64rr:
  99   case X86::AND8ri:
 100   case X86::AND8rm:
 101   case X86::AND8rr:
 102     return true;
 103   case X86::CMP16ri:
 104   case X86::CMP16ri8:
 105   case X86::CMP16rm:
 106   case X86::CMP16rr:
 107   case X86::CMP16mr:
 108   case X86::CMP32ri:
 109   case X86::CMP32ri8:
 110   case X86::CMP32rm:
 111   case X86::CMP32rr:
 112   case X86::CMP32mr:
 113   case X86::CMP64ri32:
 114   case X86::CMP64ri8:
 115   case X86::CMP64rm:
 116   case X86::CMP64rr:
 117   case X86::CMP64mr:
 118   case X86::CMP8ri:
 119   case X86::CMP8rm:
 120   case X86::CMP8rr:
 121   case X86::CMP8mr:
 122   case X86::ADD16ri:
 123   case X86::ADD16ri8:
 124   case X86::ADD16ri8_DB:
 125   case X86::ADD16ri_DB:
 126   case X86::ADD16rm:
 127   case X86::ADD16rr:
 128   case X86::ADD16rr_DB:
 129   case X86::ADD32ri:
 130   case X86::ADD32ri8:
 131   case X86::ADD32ri8_DB:
 132   case X86::ADD32ri_DB:
 133   case X86::ADD32rm:
 134   case X86::ADD32rr:
 135   case X86::ADD32rr_DB:
 136   case X86::ADD64ri32:
 137   case X86::ADD64ri32_DB:
 138   case X86::ADD64ri8:
 139   case X86::ADD64ri8_DB:
 140   case X86::ADD64rm:
 141   case X86::ADD64rr:
 142   case X86::ADD64rr_DB:
 143   case X86::ADD8ri:
 144   case X86::ADD8rm:
 145   case X86::ADD8rr:
 146   case X86::SUB16ri:
 147   case X86::SUB16ri8:
 148   case X86::SUB16rm:
 149   case X86::SUB16rr:
 150   case X86::SUB32ri:
 151   case X86::SUB32ri8:
 152   case X86::SUB32rm:
 153   case X86::SUB32rr:
 154   case X86::SUB64ri32:
 155   case X86::SUB64ri8:
 156   case X86::SUB64rm:
 157   case X86::SUB64rr:
 158   case X86::SUB8ri:
 159   case X86::SUB8rm:
 160   case X86::SUB8rr:
 161     return FuseKind == FuseCmp || FuseKind == FuseInc;
 162   case X86::INC16r:
 163   case X86::INC32r:
 164   case X86::INC64r:
 165   case X86::INC8r:
 166   case X86::DEC16r:
 167   case X86::DEC32r:
 168   case X86::DEC64r:
 169   case X86::DEC8r:
 170     return FuseKind == FuseInc;
 171   case X86::INSTRUCTION_LIST_END:
 172     return true;
 173   }
 174 }
 175
 176 namespace llvm {
 177
 178 std::unique_ptr<ScheduleDAGMutation>
 179 createX86MacroFusionDAGMutation () {
 180   return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent);
 181 }
 182
 183 } // end namespace llvm