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1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the machine model for Skylake Server to support
11 // instruction scheduling and other instruction cost heuristics.
12 //
13 //===----------------------------------------------------------------------===//
15 def SkylakeServerModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and SKylake can
17 // decode 6 instructions per cycle.
18 let IssueWidth = 6;
19 let MicroOpBufferSize = 224; // Based on the reorder buffer.
20 let LoadLatency = 5;
21 let MispredictPenalty = 14;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // This flag is set to allow the scheduler to assign a default model to
27 // unrecognized opcodes.
28 let CompleteModel = 0;
29 }
31 let SchedModel = SkylakeServerModel in {
33 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
38 // ignore that.
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def SKXPort0 : ProcResource<1>;
42 def SKXPort1 : ProcResource<1>;
43 def SKXPort2 : ProcResource<1>;
44 def SKXPort3 : ProcResource<1>;
45 def SKXPort4 : ProcResource<1>;
46 def SKXPort5 : ProcResource<1>;
47 def SKXPort6 : ProcResource<1>;
48 def SKXPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>;
52 def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>;
53 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
54 def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>;
55 def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>;
56 def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>;
57 def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>;
58 def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>;
59 def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>;
60 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
61 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
62 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
64 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
65 // FP division and sqrt on port 0.
66 def SKXFPDivider : ProcResource<1>;
68 // 60 Entry Unified Scheduler
69 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
70 SKXPort5, SKXPort6, SKXPort7]> {
71 let BufferSize=60;
72 }
74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
75 // cycles after the memory operand.
76 def : ReadAdvance<ReadAfterLd, 5>;
78 // Many SchedWrites are defined in pairs with and without a folded load.
79 // Instructions with folded loads are usually micro-fused, so they only appear
80 // as two micro-ops when queued in the reservation station.
81 // This multiclass defines the resource usage for variants with and without
82 // folded loads.
83 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
84 list<ProcResourceKind> ExePorts,
85 int Lat, list<int> Res = [1], int UOps = 1,
86 int LoadLat = 5> {
87 // Register variant is using a single cycle on ExePort.
88 def : WriteRes<SchedRW, ExePorts> {
89 let Latency = Lat;
90 let ResourceCycles = Res;
91 let NumMicroOps = UOps;
92 }
94 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
95 // the latency (default = 5).
96 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
97 let Latency = !add(Lat, LoadLat);
98 let ResourceCycles = !listconcat([1], Res);
99 let NumMicroOps = !add(UOps, 1);
100 }
101 }
103 // A folded store needs a cycle on port 4 for the store data, and an extra port
104 // 2/3/7 cycle to recompute the address.
105 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
107 // Arithmetic.
108 defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op.
109 defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op.
110 defm : SKXWriteResPair<WriteIMul, [SKXPort1], 3>; // Integer multiplication.
111 defm : SKXWriteResPair<WriteIMul64, [SKXPort1], 3>; // Integer 64-bit multiplication.
113 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
114 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
115 defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>;
116 defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>;
117 defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>;
119 defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
120 defm : SKXWriteResPair<WriteDiv16, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
121 defm : SKXWriteResPair<WriteDiv32, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
122 defm : SKXWriteResPair<WriteDiv64, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
123 defm : SKXWriteResPair<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
124 defm : SKXWriteResPair<WriteIDiv16, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
125 defm : SKXWriteResPair<WriteIDiv32, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
126 defm : SKXWriteResPair<WriteIDiv64, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
128 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
131 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
133 defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move.
134 defm : SKXWriteResPair<WriteCMOV2, [SKXPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
135 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
136 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
137 def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
138 let Latency = 2;
139 let NumMicroOps = 3;
140 }
141 def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
142 def : WriteRes<WriteBitTest,[SKXPort06]>; //
144 // Integer shifts and rotates.
145 defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
147 // SHLD/SHRD.
148 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
149 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
150 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
151 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
153 // Bit counts.
154 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
155 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
156 defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>;
157 defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>;
158 defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>;
160 // BMI1 BEXTR/BLS, BMI2 BZHI
161 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
162 defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>;
163 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
165 // Loads, stores, and moves, not folded with other operations.
166 defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>;
167 defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>;
168 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
169 defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>;
171 // Idioms that clear a register, like xorps %xmm0, %xmm0.
172 // These can often bypass execution ports completely.
173 def : WriteRes<WriteZero, []>;
175 // Branches don't produce values, so they have no latency, but they still
176 // consume resources. Indirect branches can fold loads.
177 defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>;
179 // Floating point. This covers both scalar and vector operations.
180 defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>;
181 defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>;
182 defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>;
183 defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>;
184 defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>;
185 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
186 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
187 defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
188 defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
189 defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
190 defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
191 defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
192 defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
193 defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
194 defm : X86WriteRes<WriteFMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>;
195 defm : X86WriteRes<WriteFMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
196 defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>;
197 defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>;
198 defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>;
199 defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>;
201 defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub.
202 defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>;
203 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
204 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
205 defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub.
206 defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>;
207 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
208 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
210 defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare.
211 defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>;
212 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
213 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
214 defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare.
215 defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>;
216 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
217 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
219 defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
221 defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication.
222 defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>;
223 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
224 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
225 defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication.
226 defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>;
227 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
228 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
230 defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
231 //defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
232 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
233 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
234 //defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
235 //defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
236 //defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
237 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
239 defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
240 defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
241 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
242 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
243 defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
244 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
245 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
246 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
247 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
249 defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
250 defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>;
251 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
252 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
254 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
255 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>;
256 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
257 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
259 defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add.
260 defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>;
261 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
262 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
263 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product.
264 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
265 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
266 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
267 defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
268 defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
269 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
270 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
271 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
272 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
273 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
274 defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
275 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
276 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
277 defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
278 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
279 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
280 defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
281 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
282 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
283 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
284 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
285 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
286 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
287 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
288 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
290 // FMA Scheduling helper class.
291 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
293 // Vector integer operations.
294 defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>;
295 defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>;
296 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
297 defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>;
298 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>;
299 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
300 defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>;
301 defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>;
302 defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>;
303 defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
304 defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>;
305 defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>;
306 defm : X86WriteRes<WriteVecMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>;
307 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
308 defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>;
309 defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>;
310 defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>;
311 defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>;
312 defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>;
314 defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
315 defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>;
316 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
317 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
318 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor.
319 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
320 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
321 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
322 defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
323 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
324 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
325 defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 4, [1], 1, 5>; // Vector integer multiply.
326 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 4, [1], 1, 6>;
327 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 4, [1], 1, 7>;
328 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 4, [1], 1, 7>;
329 defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
330 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
331 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
332 defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
333 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
334 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
335 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
336 defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
337 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
338 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
339 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
340 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
341 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
342 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
343 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
344 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
345 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>;
346 defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
347 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
348 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
349 defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
350 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
351 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
352 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
353 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
355 // Vector integer shifts.
356 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
357 defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>;
358 defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>;
359 defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>;
360 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
361 defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>;
362 defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>;
364 defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>;
365 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
366 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
367 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
368 defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
369 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
370 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
372 // Vector insert/extract operations.
373 def : WriteRes<WriteVecInsert, [SKXPort5]> {
374 let Latency = 2;
375 let NumMicroOps = 2;
376 let ResourceCycles = [2];
377 }
378 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
379 let Latency = 6;
380 let NumMicroOps = 2;
381 }
382 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
384 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
385 let Latency = 3;
386 let NumMicroOps = 2;
387 }
388 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
389 let Latency = 2;
390 let NumMicroOps = 3;
391 }
393 // Conversion between integer and float.
394 defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
395 defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>;
396 defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>;
397 defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>;
398 defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>;
399 defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>;
400 defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>;
401 defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>;
403 defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>;
404 defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>;
405 defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>;
406 defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ.
407 defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>;
408 defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>;
409 defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>;
410 defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>;
412 defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>;
413 defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>;
414 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
415 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
416 defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>;
417 defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>;
418 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
419 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
421 defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>;
422 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
423 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
424 defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>;
425 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
426 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
428 defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>;
429 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
430 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
431 defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
432 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
433 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
435 // Strings instructions.
437 // Packed Compare Implicit Length Strings, Return Mask
438 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
439 let Latency = 10;
440 let NumMicroOps = 3;
441 let ResourceCycles = [3];
442 }
443 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
444 let Latency = 16;
445 let NumMicroOps = 4;
446 let ResourceCycles = [3,1];
447 }
449 // Packed Compare Explicit Length Strings, Return Mask
450 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
451 let Latency = 19;
452 let NumMicroOps = 9;
453 let ResourceCycles = [4,3,1,1];
454 }
455 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
456 let Latency = 25;
457 let NumMicroOps = 10;
458 let ResourceCycles = [4,3,1,1,1];
459 }
461 // Packed Compare Implicit Length Strings, Return Index
462 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
463 let Latency = 10;
464 let NumMicroOps = 3;
465 let ResourceCycles = [3];
466 }
467 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
468 let Latency = 16;
469 let NumMicroOps = 4;
470 let ResourceCycles = [3,1];
471 }
473 // Packed Compare Explicit Length Strings, Return Index
474 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
475 let Latency = 18;
476 let NumMicroOps = 8;
477 let ResourceCycles = [4,3,1];
478 }
479 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
480 let Latency = 24;
481 let NumMicroOps = 9;
482 let ResourceCycles = [4,3,1,1];
483 }
485 // MOVMSK Instructions.
486 def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
487 def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
488 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
489 def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
491 // AES instructions.
492 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
493 let Latency = 4;
494 let NumMicroOps = 1;
495 let ResourceCycles = [1];
496 }
497 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
498 let Latency = 10;
499 let NumMicroOps = 2;
500 let ResourceCycles = [1,1];
501 }
503 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
504 let Latency = 8;
505 let NumMicroOps = 2;
506 let ResourceCycles = [2];
507 }
508 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
509 let Latency = 14;
510 let NumMicroOps = 3;
511 let ResourceCycles = [2,1];
512 }
514 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
515 let Latency = 20;
516 let NumMicroOps = 11;
517 let ResourceCycles = [3,6,2];
518 }
519 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
520 let Latency = 25;
521 let NumMicroOps = 11;
522 let ResourceCycles = [3,6,1,1];
523 }
525 // Carry-less multiplication instructions.
526 def : WriteRes<WriteCLMul, [SKXPort5]> {
527 let Latency = 6;
528 let NumMicroOps = 1;
529 let ResourceCycles = [1];
530 }
531 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
532 let Latency = 12;
533 let NumMicroOps = 2;
534 let ResourceCycles = [1,1];
535 }
537 // Catch-all for expensive system instructions.
538 def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
540 // AVX2.
541 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
542 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
543 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles.
544 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles.
546 // Old microcoded instructions that nobody use.
547 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
549 // Fence instructions.
550 def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>;
552 // Load/store MXCSR.
553 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
554 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
556 // Nop, not very useful expect it provides a model for nops!
557 def : WriteRes<WriteNop, []>;
559 ////////////////////////////////////////////////////////////////////////////////
560 // Horizontal add/sub instructions.
561 ////////////////////////////////////////////////////////////////////////////////
563 defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
564 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
565 defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>;
566 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
567 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
569 // Remaining instrs.
571 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
572 let Latency = 1;
573 let NumMicroOps = 1;
574 let ResourceCycles = [1];
575 }
576 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
577 "KANDN(B|D|Q|W)rr",
578 "KMOV(B|D|Q|W)kk",
579 "KNOT(B|D|Q|W)rr",
580 "KOR(B|D|Q|W)rr",
581 "KXNOR(B|D|Q|W)rr",
582 "KXOR(B|D|Q|W)rr",
583 "MMX_PADDS(B|W)irr",
584 "MMX_PADDUS(B|W)irr",
585 "MMX_PAVG(B|W)irr",
586 "MMX_PCMPEQ(B|D|W)irr",
587 "MMX_PCMPGT(B|D|W)irr",
588 "MMX_P(MAX|MIN)SWirr",
589 "MMX_P(MAX|MIN)UBirr",
590 "MMX_PSUBS(B|W)irr",
591 "MMX_PSUBUS(B|W)irr",
592 "VPMOVB2M(Z|Z128|Z256)rr",
593 "VPMOVD2M(Z|Z128|Z256)rr",
594 "VPMOVQ2M(Z|Z128|Z256)rr",
595 "VPMOVW2M(Z|Z128|Z256)rr")>;
597 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
598 let Latency = 1;
599 let NumMicroOps = 1;
600 let ResourceCycles = [1];
601 }
602 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
603 "KMOV(B|D|Q|W)kr",
604 "UCOM_F(P?)r")>;
606 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
607 let Latency = 1;
608 let NumMicroOps = 1;
609 let ResourceCycles = [1];
610 }
611 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
613 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
614 let Latency = 1;
615 let NumMicroOps = 1;
616 let ResourceCycles = [1];
617 }
618 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
620 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
621 let Latency = 1;
622 let NumMicroOps = 1;
623 let ResourceCycles = [1];
624 }
625 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
627 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
628 let Latency = 1;
629 let NumMicroOps = 1;
630 let ResourceCycles = [1];
631 }
632 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>;
634 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
635 let Latency = 1;
636 let NumMicroOps = 1;
637 let ResourceCycles = [1];
638 }
639 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
640 "VBLENDMPS(Z128|Z256)rr",
641 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
642 "(V?)PADD(B|D|Q|W)rr",
643 "VPBLENDD(Y?)rri",
644 "VPBLENDMB(Z128|Z256)rr",
645 "VPBLENDMD(Z128|Z256)rr",
646 "VPBLENDMQ(Z128|Z256)rr",
647 "VPBLENDMW(Z128|Z256)rr",
648 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr",
649 "(V?)PSUB(B|D|Q|W)rr",
650 "VPTERNLOGD(Z|Z128|Z256)rri",
651 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
653 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
654 let Latency = 1;
655 let NumMicroOps = 1;
656 let ResourceCycles = [1];
657 }
658 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
659 CMC, STC,
660 SGDT64m,
661 SIDT64m,
662 SMSW16m,
663 STRm,
664 SYSCALL)>;
666 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
667 let Latency = 1;
668 let NumMicroOps = 2;
669 let ResourceCycles = [1,1];
670 }
671 def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
672 def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk",
673 "ST_FP(32|64|80)m")>;
675 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
676 let Latency = 2;
677 let NumMicroOps = 2;
678 let ResourceCycles = [2];
679 }
680 def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
682 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
683 let Latency = 2;
684 let NumMicroOps = 2;
685 let ResourceCycles = [2];
686 }
687 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP,
688 MMX_MOVDQ2Qrr)>;
690 def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
691 let Latency = 2;
692 let NumMicroOps = 2;
693 let ResourceCycles = [2];
694 }
695 def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r(1|i)",
696 "ROR(8|16|32|64)r(1|i)",
697 "SET(A|BE)r")>;
699 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
700 let Latency = 2;
701 let NumMicroOps = 2;
702 let ResourceCycles = [2];
703 }
704 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
705 WAIT,
706 XGETBV)>;
708 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
709 let Latency = 2;
710 let NumMicroOps = 2;
711 let ResourceCycles = [1,1];
712 }
713 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
715 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
716 let Latency = 2;
717 let NumMicroOps = 2;
718 let ResourceCycles = [1,1];
719 }
720 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
722 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
723 let Latency = 2;
724 let NumMicroOps = 2;
725 let ResourceCycles = [1,1];
726 }
727 def: InstRW<[SKXWriteResGroup23], (instrs CWD,
728 JCXZ, JECXZ, JRCXZ,
729 ADC8i8, SBB8i8)>;
730 def: InstRW<[SKXWriteResGroup23], (instregex "ADC8ri",
731 "SBB8ri")>;
733 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
734 let Latency = 2;
735 let NumMicroOps = 3;
736 let ResourceCycles = [1,1,1];
737 }
738 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
740 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
741 let Latency = 2;
742 let NumMicroOps = 3;
743 let ResourceCycles = [1,1,1];
744 }
745 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
747 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
748 let Latency = 2;
749 let NumMicroOps = 3;
750 let ResourceCycles = [1,1,1];
751 }
752 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
753 STOSB, STOSL, STOSQ, STOSW)>;
754 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
756 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
757 let Latency = 2;
758 let NumMicroOps = 5;
759 let ResourceCycles = [2,2,1];
760 }
761 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
763 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
764 let Latency = 3;
765 let NumMicroOps = 1;
766 let ResourceCycles = [1];
767 }
768 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
769 "KORTEST(B|D|Q|W)rr",
770 "KTEST(B|D|Q|W)rr")>;
772 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
773 let Latency = 3;
774 let NumMicroOps = 1;
775 let ResourceCycles = [1];
776 }
777 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
778 "PEXT(32|64)rr")>;
780 def SKXWriteResGroup31_16i : SchedWriteRes<[SKXPort1, SKXPort0156]> {
781 let Latency = 4;
782 let NumMicroOps = 2;
783 let ResourceCycles = [1,1];
784 }
785 def: InstRW<[SKXWriteResGroup31_16i], (instrs IMUL16rri, IMUL16rri8)>;
788 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
789 let Latency = 3;
790 let NumMicroOps = 1;
791 let ResourceCycles = [1];
792 }
793 def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined.
794 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
795 "KADD(B|D|Q|W)rr",
796 "KSHIFTL(B|D|Q|W)ri",
797 "KSHIFTR(B|D|Q|W)ri",
798 "KUNPCK(BW|DQ|WD)rr",
799 "VALIGND(Z|Z128|Z256)rri",
800 "VALIGNQ(Z|Z128|Z256)rri",
801 "VCMPPD(Z|Z128|Z256)rri",
802 "VCMPPS(Z|Z128|Z256)rri",
803 "VCMP(SD|SS)Zrr",
804 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
805 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
806 "VFPCLASS(SD|SS)Zrr",
807 "VPBROADCAST(B|W)rr",
808 "VPCMPB(Z|Z128|Z256)rri",
809 "VPCMPD(Z|Z128|Z256)rri",
810 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
811 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
812 "(V?)PCMPGTQ(Y?)rr",
813 "VPCMPQ(Z|Z128|Z256)rri",
814 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
815 "VPCMPW(Z|Z128|Z256)rri",
816 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
817 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
819 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
820 let Latency = 3;
821 let NumMicroOps = 2;
822 let ResourceCycles = [1,1];
823 }
824 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
826 def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> {
827 let Latency = 3;
828 let NumMicroOps = 3;
829 let ResourceCycles = [3];
830 }
831 def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL",
832 "ROR(8|16|32|64)rCL",
833 "SAR(8|16|32|64)rCL",
834 "SHL(8|16|32|64)rCL",
835 "SHR(8|16|32|64)rCL")>;
837 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
838 let Latency = 3;
839 let NumMicroOps = 3;
840 let ResourceCycles = [1,2];
841 }
842 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
844 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
845 let Latency = 3;
846 let NumMicroOps = 3;
847 let ResourceCycles = [2,1];
848 }
849 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
851 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
852 let Latency = 3;
853 let NumMicroOps = 3;
854 let ResourceCycles = [2,1];
855 }
856 def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr,
857 MMX_PACKSSWBirr,
858 MMX_PACKUSWBirr)>;
860 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
861 let Latency = 3;
862 let NumMicroOps = 3;
863 let ResourceCycles = [1,2];
864 }
865 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
867 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
868 let Latency = 3;
869 let NumMicroOps = 3;
870 let ResourceCycles = [1,2];
871 }
872 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
874 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
875 let Latency = 3;
876 let NumMicroOps = 3;
877 let ResourceCycles = [1,2];
878 }
879 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
880 "RCR(8|16|32|64)r(1|i)")>;
882 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
883 let Latency = 3;
884 let NumMicroOps = 3;
885 let ResourceCycles = [1,1,1];
886 }
887 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
889 def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
890 let Latency = 3;
891 let NumMicroOps = 4;
892 let ResourceCycles = [1,1,2];
893 }
894 def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>;
896 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
897 let Latency = 3;
898 let NumMicroOps = 4;
899 let ResourceCycles = [1,1,1,1];
900 }
901 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
903 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
904 let Latency = 3;
905 let NumMicroOps = 4;
906 let ResourceCycles = [1,1,1,1];
907 }
908 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
910 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
911 let Latency = 4;
912 let NumMicroOps = 1;
913 let ResourceCycles = [1];
914 }
915 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
917 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
918 let Latency = 4;
919 let NumMicroOps = 1;
920 let ResourceCycles = [1];
921 }
922 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
923 "(V?)CVTDQ2PSrr",
924 "VCVTPD2QQ(Z128|Z256)rr",
925 "VCVTPD2UQQ(Z128|Z256)rr",
926 "VCVTPS2DQ(Y|Z128|Z256)rr",
927 "(V?)CVTPS2DQrr",
928 "VCVTPS2UDQ(Z128|Z256)rr",
929 "VCVTQQ2PD(Z128|Z256)rr",
930 "VCVTTPD2QQ(Z128|Z256)rr",
931 "VCVTTPD2UQQ(Z128|Z256)rr",
932 "VCVTTPS2DQ(Z128|Z256)rr",
933 "(V?)CVTTPS2DQrr",
934 "VCVTTPS2UDQ(Z128|Z256)rr",
935 "VCVTUDQ2PS(Z128|Z256)rr",
936 "VCVTUQQ2PD(Z128|Z256)rr")>;
938 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
939 let Latency = 4;
940 let NumMicroOps = 1;
941 let ResourceCycles = [1];
942 }
943 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
944 VCVTPD2QQZrr,
945 VCVTPD2UQQZrr,
946 VCVTPS2DQZrr,
947 VCVTPS2UDQZrr,
948 VCVTQQ2PDZrr,
949 VCVTTPD2QQZrr,
950 VCVTTPD2UQQZrr,
951 VCVTTPS2DQZrr,
952 VCVTTPS2UDQZrr,
953 VCVTUDQ2PSZrr,
954 VCVTUQQ2PDZrr)>;
956 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
957 let Latency = 4;
958 let NumMicroOps = 2;
959 let ResourceCycles = [2];
960 }
961 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
962 "VEXPANDPS(Z|Z128|Z256)rr",
963 "VPEXPANDD(Z|Z128|Z256)rr",
964 "VPEXPANDQ(Z|Z128|Z256)rr",
965 "VPMOVDB(Z|Z128|Z256)rr",
966 "VPMOVDW(Z|Z128|Z256)rr",
967 "VPMOVQB(Z|Z128|Z256)rr",
968 "VPMOVQW(Z|Z128|Z256)rr",
969 "VPMOVSDB(Z|Z128|Z256)rr",
970 "VPMOVSDW(Z|Z128|Z256)rr",
971 "VPMOVSQB(Z|Z128|Z256)rr",
972 "VPMOVSQD(Z|Z128|Z256)rr",
973 "VPMOVSQW(Z|Z128|Z256)rr",
974 "VPMOVSWB(Z|Z128|Z256)rr",
975 "VPMOVUSDB(Z|Z128|Z256)rr",
976 "VPMOVUSDW(Z|Z128|Z256)rr",
977 "VPMOVUSQB(Z|Z128|Z256)rr",
978 "VPMOVUSQD(Z|Z128|Z256)rr",
979 "VPMOVUSWB(Z|Z128|Z256)rr",
980 "VPMOVWB(Z|Z128|Z256)rr")>;
982 def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> {
983 let Latency = 4;
984 let NumMicroOps = 2;
985 let ResourceCycles = [1,1];
986 }
987 def: InstRW<[SKXWriteResGroup52], (instrs IMUL64r, MUL64r, MULX64rr)>;
989 def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
990 let Latency = 4;
991 let NumMicroOps = 4;
992 let ResourceCycles = [1,1,2];
993 }
994 def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r, MUL16r)>;
996 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
997 let Latency = 4;
998 let NumMicroOps = 3;
999 let ResourceCycles = [1,1,1];
1000 }
1001 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1002 "IST_F(16|32)m",
1003 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1005 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1006 let Latency = 4;
1007 let NumMicroOps = 4;
1008 let ResourceCycles = [4];
1009 }
1010 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1012 def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> {
1013 let Latency = 4;
1014 let NumMicroOps = 4;
1015 let ResourceCycles = [1,3];
1016 }
1017 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1019 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1020 let Latency = 4;
1021 let NumMicroOps = 4;
1022 let ResourceCycles = [1,1,2];
1023 }
1024 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1026 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1027 let Latency = 5;
1028 let NumMicroOps = 1;
1029 let ResourceCycles = [1];
1030 }
1031 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
1032 "MOVZX(16|32|64)rm(8|16)",
1033 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71?
1035 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1036 let Latency = 5;
1037 let NumMicroOps = 2;
1038 let ResourceCycles = [1,1];
1039 }
1040 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1041 "MMX_CVT(T?)PS2PIirr",
1042 "VCVTDQ2PDZ128rr",
1043 "VCVTPD2DQZ128rr",
1044 "(V?)CVT(T?)PD2DQrr",
1045 "VCVTPD2PSZ128rr",
1046 "(V?)CVTPD2PSrr",
1047 "VCVTPD2UDQZ128rr",
1048 "VCVTPS2PDZ128rr",
1049 "(V?)CVTPS2PDrr",
1050 "VCVTPS2QQZ128rr",
1051 "VCVTPS2UQQZ128rr",
1052 "VCVTQQ2PSZ128rr",
1053 "(V?)CVTSD2SS(Z?)rr",
1054 "(V?)CVTSI(64)?2SDrr",
1055 "VCVTSI2SSZrr",
1056 "(V?)CVTSI2SSrr",
1057 "VCVTSI(64)?2SDZrr",
1058 "VCVTSS2SDZrr",
1059 "(V?)CVTSS2SDrr",
1060 "VCVTTPD2DQZ128rr",
1061 "VCVTTPD2UDQZ128rr",
1062 "VCVTTPS2QQZ128rr",
1063 "VCVTTPS2UQQZ128rr",
1064 "VCVTUDQ2PDZ128rr",
1065 "VCVTUQQ2PSZ128rr",
1066 "VCVTUSI2SSZrr",
1067 "VCVTUSI(64)?2SDZrr")>;
1069 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1070 let Latency = 5;
1071 let NumMicroOps = 3;
1072 let ResourceCycles = [2,1];
1073 }
1074 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1076 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1077 let Latency = 5;
1078 let NumMicroOps = 3;
1079 let ResourceCycles = [1,1,1];
1080 }
1081 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1083 def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1084 let Latency = 4;
1085 let NumMicroOps = 3;
1086 let ResourceCycles = [1,1,1];
1087 }
1088 def: InstRW<[SKXWriteResGroup64], (instrs IMUL32r, MUL32r, MULX32rr)>;
1090 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1091 let Latency = 5;
1092 let NumMicroOps = 3;
1093 let ResourceCycles = [1,1,1];
1094 }
1095 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1096 "VCVTPS2PHZ256mr(b?)",
1097 "VCVTPS2PHZmr(b?)")>;
1099 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1100 let Latency = 5;
1101 let NumMicroOps = 4;
1102 let ResourceCycles = [1,2,1];
1103 }
1104 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1105 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1106 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1107 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1108 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1109 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1110 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1111 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1112 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1113 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1114 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1115 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1116 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1117 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1118 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1119 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1120 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1122 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1123 let Latency = 5;
1124 let NumMicroOps = 5;
1125 let ResourceCycles = [1,4];
1126 }
1127 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1129 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1130 let Latency = 5;
1131 let NumMicroOps = 6;
1132 let ResourceCycles = [1,1,4];
1133 }
1134 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1136 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1137 let Latency = 6;
1138 let NumMicroOps = 1;
1139 let ResourceCycles = [1];
1140 }
1141 def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm,
1142 VPBROADCASTDrm,
1143 VPBROADCASTQrm,
1144 VMOVSHDUPrm,
1145 VMOVSLDUPrm,
1146 MOVSHDUPrm,
1147 MOVSLDUPrm)>;
1149 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1150 let Latency = 6;
1151 let NumMicroOps = 2;
1152 let ResourceCycles = [2];
1153 }
1154 def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1155 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1156 "VCOMPRESSPS(Z|Z128|Z256)rr",
1157 "VPCOMPRESSD(Z|Z128|Z256)rr",
1158 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1159 "VPERMW(Z|Z128|Z256)rr")>;
1161 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1162 let Latency = 6;
1163 let NumMicroOps = 2;
1164 let ResourceCycles = [1,1];
1165 }
1166 def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm,
1167 MMX_PADDSWirm,
1168 MMX_PADDUSBirm,
1169 MMX_PADDUSWirm,
1170 MMX_PAVGBirm,
1171 MMX_PAVGWirm,
1172 MMX_PCMPEQBirm,
1173 MMX_PCMPEQDirm,
1174 MMX_PCMPEQWirm,
1175 MMX_PCMPGTBirm,
1176 MMX_PCMPGTDirm,
1177 MMX_PCMPGTWirm,
1178 MMX_PMAXSWirm,
1179 MMX_PMAXUBirm,
1180 MMX_PMINSWirm,
1181 MMX_PMINUBirm,
1182 MMX_PSUBSBirm,
1183 MMX_PSUBSWirm,
1184 MMX_PSUBUSBirm,
1185 MMX_PSUBUSWirm)>;
1187 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1188 let Latency = 6;
1189 let NumMicroOps = 2;
1190 let ResourceCycles = [1,1];
1191 }
1192 def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
1193 def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
1195 def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
1196 let Latency = 6;
1197 let NumMicroOps = 2;
1198 let ResourceCycles = [1,1];
1199 }
1200 def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
1202 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1203 let Latency = 6;
1204 let NumMicroOps = 2;
1205 let ResourceCycles = [1,1];
1206 }
1207 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1208 "MOVBE(16|32|64)rm")>;
1210 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1211 let Latency = 6;
1212 let NumMicroOps = 2;
1213 let ResourceCycles = [1,1];
1214 }
1215 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>;
1216 def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>;
1218 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1219 let Latency = 6;
1220 let NumMicroOps = 2;
1221 let ResourceCycles = [1,1];
1222 }
1223 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1224 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1226 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1227 let Latency = 6;
1228 let NumMicroOps = 3;
1229 let ResourceCycles = [2,1];
1230 }
1231 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1232 "VCVTSI642SSZrr",
1233 "VCVTUSI642SSZrr")>;
1235 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1236 let Latency = 6;
1237 let NumMicroOps = 4;
1238 let ResourceCycles = [1,1,1,1];
1239 }
1240 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1242 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1243 let Latency = 6;
1244 let NumMicroOps = 4;
1245 let ResourceCycles = [1,1,1,1];
1246 }
1247 def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8",
1248 "BTR(16|32|64)mi8",
1249 "BTS(16|32|64)mi8",
1250 "SAR(8|16|32|64)m(1|i)",
1251 "SHL(8|16|32|64)m(1|i)",
1252 "SHR(8|16|32|64)m(1|i)")>;
1254 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1255 let Latency = 6;
1256 let NumMicroOps = 4;
1257 let ResourceCycles = [1,1,1,1];
1258 }
1259 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1260 "PUSH(16|32|64)rmm")>;
1262 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1263 let Latency = 6;
1264 let NumMicroOps = 6;
1265 let ResourceCycles = [1,5];
1266 }
1267 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1269 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1270 let Latency = 7;
1271 let NumMicroOps = 1;
1272 let ResourceCycles = [1];
1273 }
1274 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1275 def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1276 VBROADCASTI128,
1277 VBROADCASTSDYrm,
1278 VBROADCASTSSYrm,
1279 VMOVDDUPYrm,
1280 VMOVSHDUPYrm,
1281 VMOVSLDUPYrm,
1282 VPBROADCASTDYrm,
1283 VPBROADCASTQYrm)>;
1285 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1286 let Latency = 7;
1287 let NumMicroOps = 2;
1288 let ResourceCycles = [1,1];
1289 }
1290 def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>;
1292 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1293 let Latency = 7;
1294 let NumMicroOps = 2;
1295 let ResourceCycles = [1,1];
1296 }
1297 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1298 "VMOVSSZrm(b?)")>;
1300 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1301 let Latency = 6;
1302 let NumMicroOps = 2;
1303 let ResourceCycles = [1,1];
1304 }
1305 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1306 "(V?)PMOV(SX|ZX)BQrm",
1307 "(V?)PMOV(SX|ZX)BWrm",
1308 "(V?)PMOV(SX|ZX)DQrm",
1309 "(V?)PMOV(SX|ZX)WDrm",
1310 "(V?)PMOV(SX|ZX)WQrm")>;
1312 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1313 let Latency = 7;
1314 let NumMicroOps = 2;
1315 let ResourceCycles = [1,1];
1316 }
1317 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1318 "VCVTPD2DQ(Y|Z256)rr",
1319 "VCVTPD2PS(Y|Z256)rr",
1320 "VCVTPD2UDQZ256rr",
1321 "VCVTPS2PD(Y|Z256)rr",
1322 "VCVTPS2QQZ256rr",
1323 "VCVTPS2UQQZ256rr",
1324 "VCVTQQ2PSZ256rr",
1325 "VCVTTPD2DQ(Y|Z256)rr",
1326 "VCVTTPD2UDQZ256rr",
1327 "VCVTTPS2QQZ256rr",
1328 "VCVTTPS2UQQZ256rr",
1329 "VCVTUDQ2PDZ256rr",
1330 "VCVTUQQ2PSZ256rr")>;
1332 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1333 let Latency = 7;
1334 let NumMicroOps = 2;
1335 let ResourceCycles = [1,1];
1336 }
1337 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1338 VCVTPD2DQZrr,
1339 VCVTPD2PSZrr,
1340 VCVTPD2UDQZrr,
1341 VCVTPS2PDZrr,
1342 VCVTPS2QQZrr,
1343 VCVTPS2UQQZrr,
1344 VCVTQQ2PSZrr,
1345 VCVTTPD2DQZrr,
1346 VCVTTPD2UDQZrr,
1347 VCVTTPS2QQZrr,
1348 VCVTTPS2UQQZrr,
1349 VCVTUDQ2PDZrr,
1350 VCVTUQQ2PSZrr)>;
1352 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1353 let Latency = 7;
1354 let NumMicroOps = 2;
1355 let ResourceCycles = [1,1];
1356 }
1357 def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm,
1358 VPBLENDDrmi)>;
1359 def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)",
1360 "VBLENDMPSZ128rm(b?)",
1361 "VBROADCASTI32X2Z128m(b?)",
1362 "VBROADCASTSSZ128m(b?)",
1363 "VINSERT(F|I)128rm",
1364 "VMOVAPDZ128rm(b?)",
1365 "VMOVAPSZ128rm(b?)",
1366 "VMOVDDUPZ128rm(b?)",
1367 "VMOVDQA32Z128rm(b?)",
1368 "VMOVDQA64Z128rm(b?)",
1369 "VMOVDQU16Z128rm(b?)",
1370 "VMOVDQU32Z128rm(b?)",
1371 "VMOVDQU64Z128rm(b?)",
1372 "VMOVDQU8Z128rm(b?)",
1373 "VMOVSHDUPZ128rm(b?)",
1374 "VMOVSLDUPZ128rm(b?)",
1375 "VMOVUPDZ128rm(b?)",
1376 "VMOVUPSZ128rm(b?)",
1377 "VPADD(B|D|Q|W)Z128rm(b?)",
1378 "(V?)PADD(B|D|Q|W)rm",
1379 "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1380 "VPBROADCASTDZ128m(b?)",
1381 "VPBROADCASTQZ128m(b?)",
1382 "VPSUB(B|D|Q|W)Z128rm(b?)",
1383 "(V?)PSUB(B|D|Q|W)rm",
1384 "VPTERNLOGDZ128rm(b?)i",
1385 "VPTERNLOGQZ128rm(b?)i")>;
1387 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1388 let Latency = 7;
1389 let NumMicroOps = 3;
1390 let ResourceCycles = [2,1];
1391 }
1392 def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm,
1393 MMX_PACKSSWBirm,
1394 MMX_PACKUSWBirm)>;
1396 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1397 let Latency = 7;
1398 let NumMicroOps = 3;
1399 let ResourceCycles = [2,1];
1400 }
1401 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1402 "VPERMI2W256rr",
1403 "VPERMI2Wrr",
1404 "VPERMT2W128rr",
1405 "VPERMT2W256rr",
1406 "VPERMT2Wrr")>;
1408 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1409 let Latency = 7;
1410 let NumMicroOps = 3;
1411 let ResourceCycles = [1,2];
1412 }
1413 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1414 SCASB, SCASL, SCASQ, SCASW)>;
1416 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1417 let Latency = 7;
1418 let NumMicroOps = 3;
1419 let ResourceCycles = [1,1,1];
1420 }
1421 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1422 "(V?)CVTSS2SI64(Z?)rr",
1423 "(V?)CVTTSS2SI64(Z?)rr",
1424 "VCVTTSS2USI64Zrr")>;
1426 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1427 let Latency = 7;
1428 let NumMicroOps = 3;
1429 let ResourceCycles = [1,1,1];
1430 }
1431 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1433 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1434 let Latency = 7;
1435 let NumMicroOps = 3;
1436 let ResourceCycles = [1,1,1];
1437 }
1438 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1440 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1441 let Latency = 7;
1442 let NumMicroOps = 3;
1443 let ResourceCycles = [1,1,1];
1444 }
1445 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1447 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1448 let Latency = 7;
1449 let NumMicroOps = 4;
1450 let ResourceCycles = [1,2,1];
1451 }
1452 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1453 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1454 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1455 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1457 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1458 let Latency = 7;
1459 let NumMicroOps = 5;
1460 let ResourceCycles = [1,1,1,2];
1461 }
1462 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
1463 "ROR(8|16|32|64)m(1|i)")>;
1465 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1466 let Latency = 7;
1467 let NumMicroOps = 5;
1468 let ResourceCycles = [1,1,1,2];
1469 }
1470 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1472 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1473 let Latency = 7;
1474 let NumMicroOps = 5;
1475 let ResourceCycles = [1,1,1,1,1];
1476 }
1477 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>;
1478 def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64)>;
1480 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1481 let Latency = 7;
1482 let NumMicroOps = 7;
1483 let ResourceCycles = [1,2,2,2];
1484 }
1485 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1486 VPSCATTERQQZ128mr,
1487 VSCATTERDPDZ128mr,
1488 VSCATTERQPDZ128mr)>;
1490 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1491 let Latency = 7;
1492 let NumMicroOps = 7;
1493 let ResourceCycles = [1,3,1,2];
1494 }
1495 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1497 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1498 let Latency = 7;
1499 let NumMicroOps = 11;
1500 let ResourceCycles = [1,4,4,2];
1501 }
1502 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1503 VPSCATTERQQZ256mr,
1504 VSCATTERDPDZ256mr,
1505 VSCATTERQPDZ256mr)>;
1507 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1508 let Latency = 7;
1509 let NumMicroOps = 19;
1510 let ResourceCycles = [1,8,8,2];
1511 }
1512 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1513 VPSCATTERQQZmr,
1514 VSCATTERDPDZmr,
1515 VSCATTERQPDZmr)>;
1517 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1518 let Latency = 7;
1519 let NumMicroOps = 36;
1520 let ResourceCycles = [1,16,1,16,2];
1521 }
1522 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1524 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1525 let Latency = 8;
1526 let NumMicroOps = 2;
1527 let ResourceCycles = [1,1];
1528 }
1529 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1530 "PEXT(32|64)rm")>;
1532 def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> {
1533 let Latency = 8;
1534 let NumMicroOps = 3;
1535 let ResourceCycles = [1,1,1];
1536 }
1537 def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
1539 def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort06, SKXPort0156, SKXPort23]> {
1540 let Latency = 9;
1541 let NumMicroOps = 5;
1542 let ResourceCycles = [1,1,2,1];
1543 }
1544 def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m, MUL16m)>;
1546 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1547 let Latency = 8;
1548 let NumMicroOps = 2;
1549 let ResourceCycles = [1,1];
1550 }
1551 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1552 "VFPCLASSSDZrm(b?)",
1553 "VPBROADCASTB(Z|Z256)m(b?)",
1554 "VPBROADCASTW(Z|Z256)m(b?)")>;
1555 def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm,
1556 VPBROADCASTWYrm,
1557 VPMOVSXBDYrm,
1558 VPMOVSXBQYrm,
1559 VPMOVSXWQYrm)>;
1561 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1562 let Latency = 8;
1563 let NumMicroOps = 2;
1564 let ResourceCycles = [1,1];
1565 }
1566 def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm,
1567 VPBLENDDYrmi)>;
1568 def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1569 "VBLENDMPS(Z|Z256)rm(b?)",
1570 "VBROADCASTF32X2Z256m(b?)",
1571 "VBROADCASTF32X2Zm(b?)",
1572 "VBROADCASTF32X4Z256rm(b?)",
1573 "VBROADCASTF32X4rm(b?)",
1574 "VBROADCASTF32X8rm(b?)",
1575 "VBROADCASTF64X2Z128rm(b?)",
1576 "VBROADCASTF64X2rm(b?)",
1577 "VBROADCASTF64X4rm(b?)",
1578 "VBROADCASTI32X2Z256m(b?)",
1579 "VBROADCASTI32X2Zm(b?)",
1580 "VBROADCASTI32X4Z256rm(b?)",
1581 "VBROADCASTI32X4rm(b?)",
1582 "VBROADCASTI32X8rm(b?)",
1583 "VBROADCASTI64X2Z128rm(b?)",
1584 "VBROADCASTI64X2rm(b?)",
1585 "VBROADCASTI64X4rm(b?)",
1586 "VBROADCASTSD(Z|Z256)m(b?)",
1587 "VBROADCASTSS(Z|Z256)m(b?)",
1588 "VINSERTF32x4(Z|Z256)rm(b?)",
1589 "VINSERTF32x8Zrm(b?)",
1590 "VINSERTF64x2(Z|Z256)rm(b?)",
1591 "VINSERTF64x4Zrm(b?)",
1592 "VINSERTI32x4(Z|Z256)rm(b?)",
1593 "VINSERTI32x8Zrm(b?)",
1594 "VINSERTI64x2(Z|Z256)rm(b?)",
1595 "VINSERTI64x4Zrm(b?)",
1596 "VMOVAPD(Z|Z256)rm(b?)",
1597 "VMOVAPS(Z|Z256)rm(b?)",
1598 "VMOVDDUP(Z|Z256)rm(b?)",
1599 "VMOVDQA32(Z|Z256)rm(b?)",
1600 "VMOVDQA64(Z|Z256)rm(b?)",
1601 "VMOVDQU16(Z|Z256)rm(b?)",
1602 "VMOVDQU32(Z|Z256)rm(b?)",
1603 "VMOVDQU64(Z|Z256)rm(b?)",
1604 "VMOVDQU8(Z|Z256)rm(b?)",
1605 "VMOVSHDUP(Z|Z256)rm(b?)",
1606 "VMOVSLDUP(Z|Z256)rm(b?)",
1607 "VMOVUPD(Z|Z256)rm(b?)",
1608 "VMOVUPS(Z|Z256)rm(b?)",
1609 "VPADD(B|D|Q|W)Yrm",
1610 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1611 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1612 "VPBROADCASTD(Z|Z256)m(b?)",
1613 "VPBROADCASTQ(Z|Z256)m(b?)",
1614 "VPSUB(B|D|Q|W)Yrm",
1615 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1616 "VPTERNLOGD(Z|Z256)rm(b?)i",
1617 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1619 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1620 let Latency = 8;
1621 let NumMicroOps = 4;
1622 let ResourceCycles = [1,2,1];
1623 }
1624 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1626 def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> {
1627 let Latency = 8;
1628 let NumMicroOps = 5;
1629 let ResourceCycles = [1,1,3];
1630 }
1631 def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>;
1633 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1634 let Latency = 8;
1635 let NumMicroOps = 5;
1636 let ResourceCycles = [1,1,1,2];
1637 }
1638 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
1639 "RCR(8|16|32|64)m(1|i)")>;
1641 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1642 let Latency = 8;
1643 let NumMicroOps = 6;
1644 let ResourceCycles = [1,1,1,3];
1645 }
1646 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1647 "SAR(8|16|32|64)mCL",
1648 "SHL(8|16|32|64)mCL",
1649 "SHR(8|16|32|64)mCL")>;
1651 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1652 let Latency = 8;
1653 let NumMicroOps = 6;
1654 let ResourceCycles = [1,1,1,2,1];
1655 }
1656 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1658 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1659 let Latency = 8;
1660 let NumMicroOps = 8;
1661 let ResourceCycles = [1,2,1,2,2];
1662 }
1663 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1664 VPSCATTERQDZ256mr,
1665 VSCATTERQPSZ128mr,
1666 VSCATTERQPSZ256mr)>;
1668 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1669 let Latency = 8;
1670 let NumMicroOps = 12;
1671 let ResourceCycles = [1,4,1,4,2];
1672 }
1673 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1674 VSCATTERDPSZ128mr)>;
1676 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1677 let Latency = 8;
1678 let NumMicroOps = 20;
1679 let ResourceCycles = [1,8,1,8,2];
1680 }
1681 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1682 VSCATTERDPSZ256mr)>;
1684 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1685 let Latency = 8;
1686 let NumMicroOps = 36;
1687 let ResourceCycles = [1,16,1,16,2];
1688 }
1689 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1691 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1692 let Latency = 9;
1693 let NumMicroOps = 2;
1694 let ResourceCycles = [1,1];
1695 }
1696 def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1698 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1699 let Latency = 9;
1700 let NumMicroOps = 2;
1701 let ResourceCycles = [1,1];
1702 }
1703 def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm,
1704 VPMOVSXDQYrm,
1705 VPMOVSXWDYrm,
1706 VPMOVZXWDYrm)>;
1707 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i",
1708 "VCMP(PD|PS)Z128rm(b?)i",
1709 "VCMP(SD|SS)Zrm",
1710 "VFPCLASSSSZrm(b?)",
1711 "VPCMPBZ128rmi(b?)",
1712 "VPCMPDZ128rmi(b?)",
1713 "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1714 "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1715 "(V?)PCMPGTQrm",
1716 "VPCMPQZ128rmi(b?)",
1717 "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1718 "VPCMPWZ128rmi(b?)",
1719 "VPERMI2D128rm(b?)",
1720 "VPERMI2PD128rm(b?)",
1721 "VPERMI2PS128rm(b?)",
1722 "VPERMI2Q128rm(b?)",
1723 "VPERMT2D128rm(b?)",
1724 "VPERMT2PD128rm(b?)",
1725 "VPERMT2PS128rm(b?)",
1726 "VPERMT2Q128rm(b?)",
1727 "VPMAXSQZ128rm(b?)",
1728 "VPMAXUQZ128rm(b?)",
1729 "VPMINSQZ128rm(b?)",
1730 "VPMINUQZ128rm(b?)",
1731 "VPMOVSXBDZ128rm(b?)",
1732 "VPMOVSXBQZ128rm(b?)",
1733 "VPMOVSXBWZ128rm(b?)",
1734 "VPMOVSXDQZ128rm(b?)",
1735 "VPMOVSXWDZ128rm(b?)",
1736 "VPMOVSXWQZ128rm(b?)",
1737 "VPMOVZXBDZ128rm(b?)",
1738 "VPMOVZXBQZ128rm(b?)",
1739 "VPMOVZXBWZ128rm(b?)",
1740 "VPMOVZXDQZ128rm(b?)",
1741 "VPMOVZXWDZ128rm(b?)",
1742 "VPMOVZXWQZ128rm(b?)",
1743 "VPTESTMBZ128rm(b?)",
1744 "VPTESTMDZ128rm(b?)",
1745 "VPTESTMQZ128rm(b?)",
1746 "VPTESTMWZ128rm(b?)",
1747 "VPTESTNMBZ128rm(b?)",
1748 "VPTESTNMDZ128rm(b?)",
1749 "VPTESTNMQZ128rm(b?)",
1750 "VPTESTNMWZ128rm(b?)")>;
1752 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1753 let Latency = 9;
1754 let NumMicroOps = 2;
1755 let ResourceCycles = [1,1];
1756 }
1757 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1758 "(V?)CVTPS2PDrm")>;
1760 def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> {
1761 let Latency = 9;
1762 let NumMicroOps = 3;
1763 let ResourceCycles = [1,1,1];
1764 }
1765 def: InstRW<[SKXWriteResGroup142], (instrs IMUL64m, MUL64m, MULX64rm)>;
1767 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1768 let Latency = 9;
1769 let NumMicroOps = 4;
1770 let ResourceCycles = [2,1,1];
1771 }
1772 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1773 "(V?)PHSUBSWrm")>;
1775 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1776 let Latency = 9;
1777 let NumMicroOps = 5;
1778 let ResourceCycles = [1,2,1,1];
1779 }
1780 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1781 "LSL(16|32|64)rm")>;
1783 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1784 let Latency = 10;
1785 let NumMicroOps = 2;
1786 let ResourceCycles = [1,1];
1787 }
1788 def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>;
1789 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1790 "ILD_F(16|32|64)m",
1791 "VALIGND(Z|Z256)rm(b?)i",
1792 "VALIGNQ(Z|Z256)rm(b?)i",
1793 "VCMPPD(Z|Z256)rm(b?)i",
1794 "VCMPPS(Z|Z256)rm(b?)i",
1795 "VPCMPB(Z|Z256)rmi(b?)",
1796 "VPCMPD(Z|Z256)rmi(b?)",
1797 "VPCMPEQB(Z|Z256)rm(b?)",
1798 "VPCMPEQD(Z|Z256)rm(b?)",
1799 "VPCMPEQQ(Z|Z256)rm(b?)",
1800 "VPCMPEQW(Z|Z256)rm(b?)",
1801 "VPCMPGTB(Z|Z256)rm(b?)",
1802 "VPCMPGTD(Z|Z256)rm(b?)",
1803 "VPCMPGTQ(Z|Z256)rm(b?)",
1804 "VPCMPGTW(Z|Z256)rm(b?)",
1805 "VPCMPQ(Z|Z256)rmi(b?)",
1806 "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1807 "VPCMPU(B|D|Q|W)Zrmi(b?)",
1808 "VPCMPW(Z|Z256)rmi(b?)",
1809 "VPMAXSQ(Z|Z256)rm(b?)",
1810 "VPMAXUQ(Z|Z256)rm(b?)",
1811 "VPMINSQ(Z|Z256)rm(b?)",
1812 "VPMINUQ(Z|Z256)rm(b?)",
1813 "VPTESTM(B|D|Q|W)Z256rm(b?)",
1814 "VPTESTM(B|D|Q|W)Zrm(b?)",
1815 "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1816 "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1818 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1819 let Latency = 10;
1820 let NumMicroOps = 2;
1821 let ResourceCycles = [1,1];
1822 }
1823 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1824 "VCVTDQ2PSZ128rm(b?)",
1825 "(V?)CVTDQ2PSrm",
1826 "VCVTPD2QQZ128rm(b?)",
1827 "VCVTPD2UQQZ128rm(b?)",
1828 "VCVTPH2PSZ128rm(b?)",
1829 "VCVTPS2DQZ128rm(b?)",
1830 "(V?)CVTPS2DQrm",
1831 "VCVTPS2PDZ128rm(b?)",
1832 "VCVTPS2QQZ128rm(b?)",
1833 "VCVTPS2UDQZ128rm(b?)",
1834 "VCVTPS2UQQZ128rm(b?)",
1835 "VCVTQQ2PDZ128rm(b?)",
1836 "VCVTQQ2PSZ128rm(b?)",
1837 "VCVTSS2SDZrm",
1838 "(V?)CVTSS2SDrm",
1839 "VCVTTPD2QQZ128rm(b?)",
1840 "VCVTTPD2UQQZ128rm(b?)",
1841 "VCVTTPS2DQZ128rm(b?)",
1842 "(V?)CVTTPS2DQrm",
1843 "VCVTTPS2QQZ128rm(b?)",
1844 "VCVTTPS2UDQZ128rm(b?)",
1845 "VCVTTPS2UQQZ128rm(b?)",
1846 "VCVTUDQ2PDZ128rm(b?)",
1847 "VCVTUDQ2PSZ128rm(b?)",
1848 "VCVTUQQ2PDZ128rm(b?)",
1849 "VCVTUQQ2PSZ128rm(b?)")>;
1851 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1852 let Latency = 10;
1853 let NumMicroOps = 3;
1854 let ResourceCycles = [2,1];
1855 }
1856 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1857 "VEXPANDPSZ128rm(b?)",
1858 "VPEXPANDDZ128rm(b?)",
1859 "VPEXPANDQZ128rm(b?)")>;
1861 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1862 let Latency = 10;
1863 let NumMicroOps = 3;
1864 let ResourceCycles = [1,1,1];
1865 }
1866 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1868 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1869 let Latency = 10;
1870 let NumMicroOps = 4;
1871 let ResourceCycles = [2,1,1];
1872 }
1873 def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm,
1874 VPHSUBSWYrm)>;
1876 def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort0156]> {
1877 let Latency = 9;
1878 let NumMicroOps = 4;
1879 let ResourceCycles = [1,1,1,1];
1880 }
1881 def: InstRW<[SKXWriteResGroup156], (instrs IMUL32m, MUL32m, MULX32rm)>;
1883 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1884 let Latency = 10;
1885 let NumMicroOps = 8;
1886 let ResourceCycles = [1,1,1,1,1,3];
1887 }
1888 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1890 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1891 let Latency = 11;
1892 let NumMicroOps = 1;
1893 let ResourceCycles = [1,3];
1894 }
1895 def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1897 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1898 let Latency = 11;
1899 let NumMicroOps = 2;
1900 let ResourceCycles = [1,1];
1901 }
1902 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1904 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1905 let Latency = 11;
1906 let NumMicroOps = 2;
1907 let ResourceCycles = [1,1];
1908 }
1909 def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm,
1910 VCVTPS2PDYrm)>;
1911 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1912 "VCVTPH2PS(Z|Z256)rm(b?)",
1913 "VCVTPS2PD(Z|Z256)rm(b?)",
1914 "VCVTQQ2PD(Z|Z256)rm(b?)",
1915 "VCVTQQ2PSZ256rm(b?)",
1916 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1917 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1918 "VCVT(T?)PS2DQYrm",
1919 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1920 "VCVT(T?)PS2QQZ256rm(b?)",
1921 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1922 "VCVT(T?)PS2UQQZ256rm(b?)",
1923 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1924 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1925 "VCVTUQQ2PSZ256rm(b?)")>;
1927 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1928 let Latency = 11;
1929 let NumMicroOps = 3;
1930 let ResourceCycles = [2,1];
1931 }
1932 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1933 "VEXPANDPD(Z|Z256)rm(b?)",
1934 "VEXPANDPS(Z|Z256)rm(b?)",
1935 "VPEXPANDD(Z|Z256)rm(b?)",
1936 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1938 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1939 let Latency = 11;
1940 let NumMicroOps = 3;
1941 let ResourceCycles = [1,2];
1942 }
1943 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1945 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1946 let Latency = 11;
1947 let NumMicroOps = 3;
1948 let ResourceCycles = [1,1,1];
1949 }
1950 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
1952 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1953 let Latency = 11;
1954 let NumMicroOps = 3;
1955 let ResourceCycles = [1,1,1];
1956 }
1957 def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
1958 CVTPD2DQrm,
1959 CVTTPD2DQrm,
1960 MMX_CVTPD2PIirm,
1961 MMX_CVTTPD2PIirm)>;
1963 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1964 let Latency = 11;
1965 let NumMicroOps = 4;
1966 let ResourceCycles = [2,1,1];
1967 }
1968 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
1970 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1971 let Latency = 11;
1972 let NumMicroOps = 7;
1973 let ResourceCycles = [2,3,2];
1974 }
1975 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
1976 "RCR(16|32|64)rCL")>;
1978 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
1979 let Latency = 11;
1980 let NumMicroOps = 9;
1981 let ResourceCycles = [1,5,1,2];
1982 }
1983 def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>;
1985 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1986 let Latency = 11;
1987 let NumMicroOps = 11;
1988 let ResourceCycles = [2,9];
1989 }
1990 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
1992 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
1993 let Latency = 12;
1994 let NumMicroOps = 3;
1995 let ResourceCycles = [3];
1996 }
1997 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
1999 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
2000 let Latency = 12;
2001 let NumMicroOps = 3;
2002 let ResourceCycles = [3];
2003 }
2004 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
2006 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2007 let Latency = 12;
2008 let NumMicroOps = 3;
2009 let ResourceCycles = [2,1];
2010 }
2011 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
2013 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
2014 let Latency = 12;
2015 let NumMicroOps = 3;
2016 let ResourceCycles = [1,1,1];
2017 }
2018 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2019 "VCVT(T?)SS2USI64Zrm(b?)")>;
2021 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2022 let Latency = 12;
2023 let NumMicroOps = 3;
2024 let ResourceCycles = [1,1,1];
2025 }
2026 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
2027 "VCVT(T?)PS2UQQZrm(b?)")>;
2029 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
2030 let Latency = 12;
2031 let NumMicroOps = 4;
2032 let ResourceCycles = [1,1,1,1];
2033 }
2034 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2036 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2037 let Latency = 13;
2038 let NumMicroOps = 3;
2039 let ResourceCycles = [2,1];
2040 }
2041 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
2042 "VPERMWZ256rm(b?)",
2043 "VPERMWZrm(b?)")>;
2045 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2046 let Latency = 13;
2047 let NumMicroOps = 3;
2048 let ResourceCycles = [1,1,1];
2049 }
2050 def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>;
2052 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2053 let Latency = 13;
2054 let NumMicroOps = 4;
2055 let ResourceCycles = [2,1,1];
2056 }
2057 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2058 "VPERMT2W128rm(b?)")>;
2060 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2061 let Latency = 14;
2062 let NumMicroOps = 1;
2063 let ResourceCycles = [1,3];
2064 }
2065 def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2066 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2068 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2069 let Latency = 14;
2070 let NumMicroOps = 1;
2071 let ResourceCycles = [1,5];
2072 }
2073 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2075 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2076 let Latency = 14;
2077 let NumMicroOps = 3;
2078 let ResourceCycles = [1,1,1];
2079 }
2080 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2082 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2083 let Latency = 14;
2084 let NumMicroOps = 3;
2085 let ResourceCycles = [1,1,1];
2086 }
2087 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2088 "VCVTPD2PSZrm(b?)",
2089 "VCVTPD2UDQZrm(b?)",
2090 "VCVTQQ2PSZrm(b?)",
2091 "VCVTTPD2DQZrm(b?)",
2092 "VCVTTPD2UDQZrm(b?)",
2093 "VCVTUQQ2PSZrm(b?)")>;
2095 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2096 let Latency = 14;
2097 let NumMicroOps = 4;
2098 let ResourceCycles = [2,1,1];
2099 }
2100 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2101 "VPERMI2Wrm(b?)",
2102 "VPERMT2W256rm(b?)",
2103 "VPERMT2Wrm(b?)")>;
2105 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2106 let Latency = 14;
2107 let NumMicroOps = 10;
2108 let ResourceCycles = [2,4,1,3];
2109 }
2110 def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>;
2112 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2113 let Latency = 15;
2114 let NumMicroOps = 1;
2115 let ResourceCycles = [1];
2116 }
2117 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2119 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2120 let Latency = 15;
2121 let NumMicroOps = 8;
2122 let ResourceCycles = [1,2,2,1,2];
2123 }
2124 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2126 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2127 let Latency = 15;
2128 let NumMicroOps = 10;
2129 let ResourceCycles = [1,1,1,5,1,1];
2130 }
2131 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2133 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2134 let Latency = 16;
2135 let NumMicroOps = 14;
2136 let ResourceCycles = [1,1,1,4,2,5];
2137 }
2138 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2140 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> {
2141 let Latency = 16;
2142 let NumMicroOps = 16;
2143 let ResourceCycles = [16];
2144 }
2145 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2147 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2148 let Latency = 17;
2149 let NumMicroOps = 2;
2150 let ResourceCycles = [1,1,5];
2151 }
2152 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2154 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2155 let Latency = 17;
2156 let NumMicroOps = 15;
2157 let ResourceCycles = [2,1,2,4,2,4];
2158 }
2159 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2161 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2162 let Latency = 18;
2163 let NumMicroOps = 4;
2164 let ResourceCycles = [1,3];
2165 }
2166 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2168 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2169 let Latency = 18;
2170 let NumMicroOps = 8;
2171 let ResourceCycles = [1,1,1,5];
2172 }
2173 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2175 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2176 let Latency = 18;
2177 let NumMicroOps = 11;
2178 let ResourceCycles = [2,1,1,4,1,2];
2179 }
2180 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2182 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2183 let Latency = 19;
2184 let NumMicroOps = 2;
2185 let ResourceCycles = [1,1,4];
2186 }
2187 def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2189 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2190 let Latency = 19;
2191 let NumMicroOps = 4;
2192 let ResourceCycles = [1,3];
2193 }
2194 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2195 "VPMULLQZrm(b?)")>;
2197 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2198 let Latency = 20;
2199 let NumMicroOps = 0;
2200 }
2201 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2202 VGATHERQPSZrm,
2203 VPGATHERDDZ128rm)>;
2205 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2206 let Latency = 20;
2207 let NumMicroOps = 1;
2208 let ResourceCycles = [1];
2209 }
2210 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2212 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2213 let Latency = 20;
2214 let NumMicroOps = 2;
2215 let ResourceCycles = [1,1,4];
2216 }
2217 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2219 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2220 let Latency = 20;
2221 let NumMicroOps = 5;
2222 let ResourceCycles = [1,2,1,1];
2223 }
2224 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2225 VGATHERQPSZ256rm,
2226 VPGATHERQDZ128rm,
2227 VPGATHERQDZ256rm)>;
2229 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2230 let Latency = 20;
2231 let NumMicroOps = 8;
2232 let ResourceCycles = [1,1,1,1,1,1,2];
2233 }
2234 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2236 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2237 let Latency = 20;
2238 let NumMicroOps = 10;
2239 let ResourceCycles = [1,2,7];
2240 }
2241 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2243 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2244 let Latency = 21;
2245 let NumMicroOps = 2;
2246 let ResourceCycles = [1,1,8];
2247 }
2248 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2250 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2251 let Latency = 22;
2252 let NumMicroOps = 2;
2253 let ResourceCycles = [1,1];
2254 }
2255 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2257 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2258 let Latency = 22;
2259 let NumMicroOps = 5;
2260 let ResourceCycles = [1,2,1,1];
2261 }
2262 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2263 VGATHERQPDZ128rm,
2264 VPGATHERDQZ128rm,
2265 VPGATHERQQZ128rm)>;
2267 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2268 let Latency = 22;
2269 let NumMicroOps = 5;
2270 let ResourceCycles = [1,2,1,1];
2271 }
2272 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2273 VGATHERDPDrm,
2274 VGATHERQPDrm,
2275 VGATHERQPSrm,
2276 VPGATHERDDrm,
2277 VPGATHERDQrm,
2278 VPGATHERQDrm,
2279 VPGATHERQQrm,
2280 VPGATHERDDrm,
2281 VPGATHERQDrm,
2282 VPGATHERDQrm,
2283 VPGATHERQQrm,
2284 VGATHERDPSrm,
2285 VGATHERQPSrm,
2286 VGATHERDPDrm,
2287 VGATHERQPDrm)>;
2289 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2290 let Latency = 25;
2291 let NumMicroOps = 5;
2292 let ResourceCycles = [1,2,1,1];
2293 }
2294 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2295 VGATHERQPDYrm,
2296 VGATHERQPSYrm,
2297 VPGATHERDDYrm,
2298 VPGATHERDQYrm,
2299 VPGATHERQDYrm,
2300 VPGATHERQQYrm,
2301 VPGATHERDDYrm,
2302 VPGATHERQDYrm,
2303 VPGATHERDQYrm,
2304 VPGATHERQQYrm,
2305 VGATHERDPSYrm,
2306 VGATHERQPSYrm,
2307 VGATHERDPDYrm)>;
2309 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2310 let Latency = 22;
2311 let NumMicroOps = 14;
2312 let ResourceCycles = [5,5,4];
2313 }
2314 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2315 "VPCONFLICTQZ256rr")>;
2317 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2318 let Latency = 23;
2319 let NumMicroOps = 19;
2320 let ResourceCycles = [2,1,4,1,1,4,6];
2321 }
2322 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2324 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2325 let Latency = 25;
2326 let NumMicroOps = 3;
2327 let ResourceCycles = [1,1,1];
2328 }
2329 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2331 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2332 let Latency = 25;
2333 let NumMicroOps = 5;
2334 let ResourceCycles = [1,2,1,1];
2335 }
2336 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2337 VGATHERQPDZ256rm,
2338 VPGATHERDQZ256rm,
2339 VPGATHERQDZrm,
2340 VPGATHERQQZ256rm)>;
2342 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2343 let Latency = 26;
2344 let NumMicroOps = 5;
2345 let ResourceCycles = [1,2,1,1];
2346 }
2347 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2348 VGATHERQPDZrm,
2349 VPGATHERDQZrm,
2350 VPGATHERQQZrm)>;
2352 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2353 let Latency = 27;
2354 let NumMicroOps = 2;
2355 let ResourceCycles = [1,1];
2356 }
2357 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2359 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2360 let Latency = 27;
2361 let NumMicroOps = 5;
2362 let ResourceCycles = [1,2,1,1];
2363 }
2364 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2365 VPGATHERDDZ256rm)>;
2367 def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> {
2368 let Latency = 28;
2369 let NumMicroOps = 8;
2370 let ResourceCycles = [2,4,1,1];
2371 }
2372 def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>;
2374 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2375 let Latency = 29;
2376 let NumMicroOps = 15;
2377 let ResourceCycles = [5,5,1,4];
2378 }
2379 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2381 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2382 let Latency = 30;
2383 let NumMicroOps = 3;
2384 let ResourceCycles = [1,1,1];
2385 }
2386 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2388 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2389 let Latency = 30;
2390 let NumMicroOps = 5;
2391 let ResourceCycles = [1,2,1,1];
2392 }
2393 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2394 VPGATHERDDZrm)>;
2396 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2397 let Latency = 35;
2398 let NumMicroOps = 23;
2399 let ResourceCycles = [1,5,3,4,10];
2400 }
2401 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2402 "IN(8|16|32)rr")>;
2404 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2405 let Latency = 35;
2406 let NumMicroOps = 23;
2407 let ResourceCycles = [1,5,2,1,4,10];
2408 }
2409 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2410 "OUT(8|16|32)rr")>;
2412 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2413 let Latency = 37;
2414 let NumMicroOps = 21;
2415 let ResourceCycles = [9,7,5];
2416 }
2417 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2418 "VPCONFLICTQZrr")>;
2420 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2421 let Latency = 37;
2422 let NumMicroOps = 31;
2423 let ResourceCycles = [1,8,1,21];
2424 }
2425 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2427 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2428 let Latency = 40;
2429 let NumMicroOps = 18;
2430 let ResourceCycles = [1,1,2,3,1,1,1,8];
2431 }
2432 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2434 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2435 let Latency = 41;
2436 let NumMicroOps = 39;
2437 let ResourceCycles = [1,10,1,1,26];
2438 }
2439 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2441 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2442 let Latency = 42;
2443 let NumMicroOps = 22;
2444 let ResourceCycles = [2,20];
2445 }
2446 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2448 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2449 let Latency = 42;
2450 let NumMicroOps = 40;
2451 let ResourceCycles = [1,11,1,1,26];
2452 }
2453 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2454 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2456 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2457 let Latency = 44;
2458 let NumMicroOps = 22;
2459 let ResourceCycles = [9,7,1,5];
2460 }
2461 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2462 "VPCONFLICTQZrm(b?)")>;
2464 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2465 let Latency = 62;
2466 let NumMicroOps = 64;
2467 let ResourceCycles = [2,8,5,10,39];
2468 }
2469 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2471 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2472 let Latency = 63;
2473 let NumMicroOps = 88;
2474 let ResourceCycles = [4,4,31,1,2,1,45];
2475 }
2476 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2478 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2479 let Latency = 63;
2480 let NumMicroOps = 90;
2481 let ResourceCycles = [4,2,33,1,2,1,47];
2482 }
2483 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2485 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2486 let Latency = 67;
2487 let NumMicroOps = 35;
2488 let ResourceCycles = [17,11,7];
2489 }
2490 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2492 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2493 let Latency = 74;
2494 let NumMicroOps = 36;
2495 let ResourceCycles = [17,11,1,7];
2496 }
2497 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2499 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2500 let Latency = 75;
2501 let NumMicroOps = 15;
2502 let ResourceCycles = [6,3,6];
2503 }
2504 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2506 def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2507 let Latency = 76;
2508 let NumMicroOps = 32;
2509 let ResourceCycles = [7,2,8,3,1,11];
2510 }
2511 def: InstRW<[SKXWriteResGroup264], (instregex "DIV(16|32|64)r")>;
2513 def SKXWriteResGroup265 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2514 let Latency = 102;
2515 let NumMicroOps = 66;
2516 let ResourceCycles = [4,2,4,8,14,34];
2517 }
2518 def: InstRW<[SKXWriteResGroup265], (instregex "IDIV(16|32|64)r")>;
2520 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2521 let Latency = 106;
2522 let NumMicroOps = 100;
2523 let ResourceCycles = [9,1,11,16,1,11,21,30];
2524 }
2525 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2527 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2528 let Latency = 140;
2529 let NumMicroOps = 4;
2530 let ResourceCycles = [1,3];
2531 }
2532 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2534 def: InstRW<[WriteZero], (instrs CLC)>;
2536 } // SchedModel