lib/Target/X86/X86Subtarget.h

   1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  16
  17 #include "X86FrameLowering.h"
  18 #include "X86ISelLowering.h"
  19 #include "X86InstrInfo.h"
  20 #include "X86SelectionDAGInfo.h"
  21 #include "llvm/ADT/StringRef.h"
  22 #include "llvm/ADT/Triple.h"
  23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  24 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  25 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  26 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  27 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  28 #include "llvm/IR/CallingConv.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include <climits>
  31 #include <memory>
  32
  33 #define GET_SUBTARGETINFO_HEADER
  34 #include "X86GenSubtargetInfo.inc"
  35
  36 namespace llvm {
  37
  38 class GlobalValue;
  39
  40 /// The X86 backend supports a number of different styles of PIC.
  41 ///
  42 namespace PICStyles {
  43
  44 enum Style {
  45   StubPIC,          // Used on i386-darwin in pic mode.
  46   GOT,              // Used on 32 bit elf on when in pic mode.
  47   RIPRel,           // Used on X86-64 when in pic mode.
  48   None              // Set when not in pic mode.
  49 };
  50
  51 } // end namespace PICStyles
  52
  53 class X86Subtarget final : public X86GenSubtargetInfo {
  54 public:
  55   enum X86ProcFamilyEnum {
  56     Others,
  57     IntelAtom,
  58     IntelSLM,
  59     IntelGLM,
  60     IntelGLP,
  61     IntelTRM,
  62     IntelHaswell,
  63     IntelBroadwell,
  64     IntelSkylake,
  65     IntelKNL,
  66     IntelSKX,
  67     IntelCannonlake,
  68     IntelIcelakeClient,
  69     IntelIcelakeServer,
  70   };
  71
  72 protected:
  73   enum X86SSEEnum {
  74     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
  75   };
  76
  77   enum X863DNowEnum {
  78     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
  79   };
  80
  81   /// X86 processor family: Intel Atom, and others
  82   X86ProcFamilyEnum X86ProcFamily = Others;
  83
  84   /// Which PIC style to use
  85   PICStyles::Style PICStyle;
  86
  87   const TargetMachine &TM;
  88
  89   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
  90   X86SSEEnum X86SSELevel = NoSSE;
  91
  92   /// MMX, 3DNow, 3DNow Athlon, or none supported.
  93   X863DNowEnum X863DNowLevel = NoThreeDNow;
  94
  95   /// True if the processor supports X87 instructions.
  96   bool HasX87 = false;
  97
  98   /// True if this processor has NOPL instruction
  99   /// (generally pentium pro+).
 100   bool HasNOPL = false;
 101
 102   /// True if this processor has conditional move instructions
 103   /// (generally pentium pro+).
 104   bool HasCMov = false;
 105
 106   /// True if the processor supports X86-64 instructions.
 107   bool HasX86_64 = false;
 108
 109   /// True if the processor supports POPCNT.
 110   bool HasPOPCNT = false;
 111
 112   /// True if the processor supports SSE4A instructions.
 113   bool HasSSE4A = false;
 114
 115   /// Target has AES instructions
 116   bool HasAES = false;
 117   bool HasVAES = false;
 118
 119   /// Target has FXSAVE/FXRESTOR instructions
 120   bool HasFXSR = false;
 121
 122   /// Target has XSAVE instructions
 123   bool HasXSAVE = false;
 124
 125   /// Target has XSAVEOPT instructions
 126   bool HasXSAVEOPT = false;
 127
 128   /// Target has XSAVEC instructions
 129   bool HasXSAVEC = false;
 130
 131   /// Target has XSAVES instructions
 132   bool HasXSAVES = false;
 133
 134   /// Target has carry-less multiplication
 135   bool HasPCLMUL = false;
 136   bool HasVPCLMULQDQ = false;
 137
 138   /// Target has Galois Field Arithmetic instructions
 139   bool HasGFNI = false;
 140
 141   /// Target has 3-operand fused multiply-add
 142   bool HasFMA = false;
 143
 144   /// Target has 4-operand fused multiply-add
 145   bool HasFMA4 = false;
 146
 147   /// Target has XOP instructions
 148   bool HasXOP = false;
 149
 150   /// Target has TBM instructions.
 151   bool HasTBM = false;
 152
 153   /// Target has LWP instructions
 154   bool HasLWP = false;
 155
 156   /// True if the processor has the MOVBE instruction.
 157   bool HasMOVBE = false;
 158
 159   /// True if the processor has the RDRAND instruction.
 160   bool HasRDRAND = false;
 161
 162   /// Processor has 16-bit floating point conversion instructions.
 163   bool HasF16C = false;
 164
 165   /// Processor has FS/GS base insturctions.
 166   bool HasFSGSBase = false;
 167
 168   /// Processor has LZCNT instruction.
 169   bool HasLZCNT = false;
 170
 171   /// Processor has BMI1 instructions.
 172   bool HasBMI = false;
 173
 174   /// Processor has BMI2 instructions.
 175   bool HasBMI2 = false;
 176
 177   /// Processor has VBMI instructions.
 178   bool HasVBMI = false;
 179
 180   /// Processor has VBMI2 instructions.
 181   bool HasVBMI2 = false;
 182
 183   /// Processor has Integer Fused Multiply Add
 184   bool HasIFMA = false;
 185
 186   /// Processor has RTM instructions.
 187   bool HasRTM = false;
 188
 189   /// Processor has ADX instructions.
 190   bool HasADX = false;
 191
 192   /// Processor has SHA instructions.
 193   bool HasSHA = false;
 194
 195   /// Processor has PRFCHW instructions.
 196   bool HasPRFCHW = false;
 197
 198   /// Processor has RDSEED instructions.
 199   bool HasRDSEED = false;
 200
 201   /// Processor has LAHF/SAHF instructions.
 202   bool HasLAHFSAHF = false;
 203
 204   /// Processor has MONITORX/MWAITX instructions.
 205   bool HasMWAITX = false;
 206
 207   /// Processor has Cache Line Zero instruction
 208   bool HasCLZERO = false;
 209
 210   /// Processor has Cache Line Demote instruction
 211   bool HasCLDEMOTE = false;
 212
 213   /// Processor has MOVDIRI instruction (direct store integer).
 214   bool HasMOVDIRI = false;
 215
 216   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
 217   bool HasMOVDIR64B = false;
 218
 219   /// Processor has ptwrite instruction.
 220   bool HasPTWRITE = false;
 221
 222   /// Processor has Prefetch with intent to Write instruction
 223   bool HasPREFETCHWT1 = false;
 224
 225   /// True if SHLD instructions are slow.
 226   bool IsSHLDSlow = false;
 227
 228   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
 229   //  PMULUDQ.
 230   bool IsPMULLDSlow = false;
 231
 232   /// True if unaligned memory accesses of 16-bytes are slow.
 233   bool IsUAMem16Slow = false;
 234
 235   /// True if unaligned memory accesses of 32-bytes are slow.
 236   bool IsUAMem32Slow = false;
 237
 238   /// True if SSE operations can have unaligned memory operands.
 239   /// This may require setting a configuration bit in the processor.
 240   bool HasSSEUnalignedMem = false;
 241
 242   /// True if this processor has the CMPXCHG16B instruction;
 243   /// this is true for most x86-64 chips, but not the first AMD chips.
 244   bool HasCmpxchg16b = false;
 245
 246   /// True if the LEA instruction should be used for adjusting
 247   /// the stack pointer. This is an optimization for Intel Atom processors.
 248   bool UseLeaForSP = false;
 249
 250   /// True if POPCNT instruction has a false dependency on the destination register.
 251   bool HasPOPCNTFalseDeps = false;
 252
 253   /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
 254   bool HasLZCNTFalseDeps = false;
 255
 256   /// True if its preferable to combine to a single shuffle using a variable
 257   /// mask over multiple fixed shuffles.
 258   bool HasFastVariableShuffle = false;
 259
 260   /// True if there is no performance penalty to writing only the lower parts
 261   /// of a YMM or ZMM register without clearing the upper part.
 262   bool HasFastPartialYMMorZMMWrite = false;
 263
 264   /// True if there is no performance penalty for writing NOPs with up to
 265   /// 11 bytes.
 266   bool HasFast11ByteNOP = false;
 267
 268   /// True if there is no performance penalty for writing NOPs with up to
 269   /// 15 bytes.
 270   bool HasFast15ByteNOP = false;
 271
 272   /// True if gather is reasonably fast. This is true for Skylake client and
 273   /// all AVX-512 CPUs.
 274   bool HasFastGather = false;
 275
 276   /// True if hardware SQRTSS instruction is at least as fast (latency) as
 277   /// RSQRTSS followed by a Newton-Raphson iteration.
 278   bool HasFastScalarFSQRT = false;
 279
 280   /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
 281   /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
 282   bool HasFastVectorFSQRT = false;
 283
 284   /// True if 8-bit divisions are significantly faster than
 285   /// 32-bit divisions and should be used when possible.
 286   bool HasSlowDivide32 = false;
 287
 288   /// True if 32-bit divides are significantly faster than
 289   /// 64-bit divisions and should be used when possible.
 290   bool HasSlowDivide64 = false;
 291
 292   /// True if LZCNT instruction is fast.
 293   bool HasFastLZCNT = false;
 294
 295   /// True if SHLD based rotate is fast.
 296   bool HasFastSHLDRotate = false;
 297
 298   /// True if the processor supports macrofusion.
 299   bool HasMacroFusion = false;
 300
 301   /// True if the processor has enhanced REP MOVSB/STOSB.
 302   bool HasERMSB = false;
 303
 304   /// True if the short functions should be padded to prevent
 305   /// a stall when returning too early.
 306   bool PadShortFunctions = false;
 307
 308   /// True if two memory operand instructions should use a temporary register
 309   /// instead.
 310   bool SlowTwoMemOps = false;
 311
 312   /// True if the LEA instruction inputs have to be ready at address generation
 313   /// (AG) time.
 314   bool LEAUsesAG = false;
 315
 316   /// True if the LEA instruction with certain arguments is slow
 317   bool SlowLEA = false;
 318
 319   /// True if the LEA instruction has all three source operands: base, index,
 320   /// and offset or if the LEA instruction uses base and index registers where
 321   /// the base is EBP, RBP,or R13
 322   bool Slow3OpsLEA = false;
 323
 324   /// True if INC and DEC instructions are slow when writing to flags
 325   bool SlowIncDec = false;
 326
 327   /// Processor has AVX-512 PreFetch Instructions
 328   bool HasPFI = false;
 329
 330   /// Processor has AVX-512 Exponential and Reciprocal Instructions
 331   bool HasERI = false;
 332
 333   /// Processor has AVX-512 Conflict Detection Instructions
 334   bool HasCDI = false;
 335
 336   /// Processor has AVX-512 population count Instructions
 337   bool HasVPOPCNTDQ = false;
 338
 339   /// Processor has AVX-512 Doubleword and Quadword instructions
 340   bool HasDQI = false;
 341
 342   /// Processor has AVX-512 Byte and Word instructions
 343   bool HasBWI = false;
 344
 345   /// Processor has AVX-512 Vector Length eXtenstions
 346   bool HasVLX = false;
 347
 348   /// Processor has PKU extenstions
 349   bool HasPKU = false;
 350
 351   /// Processor has AVX-512 Vector Neural Network Instructions
 352   bool HasVNNI = false;
 353
 354   /// Processor has AVX-512 Bit Algorithms instructions
 355   bool HasBITALG = false;
 356
 357   /// Processor supports MPX - Memory Protection Extensions
 358   bool HasMPX = false;
 359
 360   /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
 361   /// using Shadow Stack
 362   bool HasSHSTK = false;
 363
 364   /// Processor supports Invalidate Process-Context Identifier
 365   bool HasINVPCID = false;
 366
 367   /// Processor has Software Guard Extensions
 368   bool HasSGX = false;
 369
 370   /// Processor supports Flush Cache Line instruction
 371   bool HasCLFLUSHOPT = false;
 372
 373   /// Processor supports Cache Line Write Back instruction
 374   bool HasCLWB = false;
 375
 376   /// Processor supports Write Back No Invalidate instruction
 377   bool HasWBNOINVD = false;
 378
 379   /// Processor support RDPID instruction
 380   bool HasRDPID = false;
 381
 382   /// Processor supports WaitPKG instructions
 383   bool HasWAITPKG = false;
 384
 385   /// Processor supports PCONFIG instruction
 386   bool HasPCONFIG = false;
 387
 388   /// Use a retpoline thunk rather than indirect calls to block speculative
 389   /// execution.
 390   bool UseRetpolineIndirectCalls = false;
 391
 392   /// Use a retpoline thunk or remove any indirect branch to block speculative
 393   /// execution.
 394   bool UseRetpolineIndirectBranches = false;
 395
 396   /// Deprecated flag, query `UseRetpolineIndirectCalls` and
 397   /// `UseRetpolineIndirectBranches` instead.
 398   bool DeprecatedUseRetpoline = false;
 399
 400   /// When using a retpoline thunk, call an externally provided thunk rather
 401   /// than emitting one inside the compiler.
 402   bool UseRetpolineExternalThunk = false;
 403
 404   /// Use software floating point for code generation.
 405   bool UseSoftFloat = false;
 406
 407   /// The minimum alignment known to hold of the stack frame on
 408   /// entry to the function and which must be maintained by every function.
 409   unsigned stackAlignment = 4;
 410
 411   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
 412   ///
 413   // FIXME: this is a known good value for Yonah. How about others?
 414   unsigned MaxInlineSizeThreshold = 128;
 415
 416   /// Indicates target prefers 256 bit instructions.
 417   bool Prefer256Bit = false;
 418
 419   /// What processor and OS we're targeting.
 420   Triple TargetTriple;
 421
 422   /// GlobalISel related APIs.
 423   std::unique_ptr<CallLowering> CallLoweringInfo;
 424   std::unique_ptr<LegalizerInfo> Legalizer;
 425   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 426   std::unique_ptr<InstructionSelector> InstSelector;
 427
 428 private:
 429   /// Override the stack alignment.
 430   unsigned StackAlignOverride;
 431
 432   /// Preferred vector width from function attribute.
 433   unsigned PreferVectorWidthOverride;
 434
 435   /// Resolved preferred vector width from function attribute and subtarget
 436   /// features.
 437   unsigned PreferVectorWidth = UINT32_MAX;
 438
 439   /// Required vector width from function attribute.
 440   unsigned RequiredVectorWidth;
 441
 442   /// True if compiling for 64-bit, false for 16-bit or 32-bit.
 443   bool In64BitMode;
 444
 445   /// True if compiling for 32-bit, false for 16-bit or 64-bit.
 446   bool In32BitMode;
 447
 448   /// True if compiling for 16-bit, false for 32-bit or 64-bit.
 449   bool In16BitMode;
 450
 451   /// Contains the Overhead of gather\scatter instructions
 452   int GatherOverhead = 1024;
 453   int ScatterOverhead = 1024;
 454
 455   X86SelectionDAGInfo TSInfo;
 456   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
 457   // X86TargetLowering needs.
 458   X86InstrInfo InstrInfo;
 459   X86TargetLowering TLInfo;
 460   X86FrameLowering FrameLowering;
 461
 462 public:
 463   /// This constructor initializes the data members to match that
 464   /// of the specified triple.
 465   ///
 466   X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
 467                const X86TargetMachine &TM, unsigned StackAlignOverride,
 468                unsigned PreferVectorWidthOverride,
 469                unsigned RequiredVectorWidth);
 470
 471   const X86TargetLowering *getTargetLowering() const override {
 472     return &TLInfo;
 473   }
 474
 475   const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
 476
 477   const X86FrameLowering *getFrameLowering() const override {
 478     return &FrameLowering;
 479   }
 480
 481   const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
 482     return &TSInfo;
 483   }
 484
 485   const X86RegisterInfo *getRegisterInfo() const override {
 486     return &getInstrInfo()->getRegisterInfo();
 487   }
 488
 489   /// Returns the minimum alignment known to hold of the
 490   /// stack frame on entry to the function and which must be maintained by every
 491   /// function for this subtarget.
 492   unsigned getStackAlignment() const { return stackAlignment; }
 493
 494   /// Returns the maximum memset / memcpy size
 495   /// that still makes it profitable to inline the call.
 496   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
 497
 498   /// ParseSubtargetFeatures - Parses features string setting specified
 499   /// subtarget options.  Definition of function is auto generated by tblgen.
 500   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 501
 502   /// Methods used by Global ISel
 503   const CallLowering *getCallLowering() const override;
 504   const InstructionSelector *getInstructionSelector() const override;
 505   const LegalizerInfo *getLegalizerInfo() const override;
 506   const RegisterBankInfo *getRegBankInfo() const override;
 507
 508 private:
 509   /// Initialize the full set of dependencies so we can use an initializer
 510   /// list for X86Subtarget.
 511   X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 512   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 513
 514 public:
 515   /// Is this x86_64? (disregarding specific ABI / programming model)
 516   bool is64Bit() const {
 517     return In64BitMode;
 518   }
 519
 520   bool is32Bit() const {
 521     return In32BitMode;
 522   }
 523
 524   bool is16Bit() const {
 525     return In16BitMode;
 526   }
 527
 528   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
 529   bool isTarget64BitILP32() const {
 530     return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
 531                            TargetTriple.isOSNaCl());
 532   }
 533
 534   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
 535   bool isTarget64BitLP64() const {
 536     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
 537                            !TargetTriple.isOSNaCl());
 538   }
 539
 540   PICStyles::Style getPICStyle() const { return PICStyle; }
 541   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 542
 543   bool hasX87() const { return HasX87; }
 544   bool hasNOPL() const { return HasNOPL; }
 545   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
 546   // All 64-bit processors support cmov.
 547   bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
 548   bool hasSSE1() const { return X86SSELevel >= SSE1; }
 549   bool hasSSE2() const { return X86SSELevel >= SSE2; }
 550   bool hasSSE3() const { return X86SSELevel >= SSE3; }
 551   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
 552   bool hasSSE41() const { return X86SSELevel >= SSE41; }
 553   bool hasSSE42() const { return X86SSELevel >= SSE42; }
 554   bool hasAVX() const { return X86SSELevel >= AVX; }
 555   bool hasAVX2() const { return X86SSELevel >= AVX2; }
 556   bool hasAVX512() const { return X86SSELevel >= AVX512F; }
 557   bool hasInt256() const { return hasAVX2(); }
 558   bool hasSSE4A() const { return HasSSE4A; }
 559   bool hasMMX() const { return X863DNowLevel >= MMX; }
 560   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
 561   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
 562   bool hasPOPCNT() const { return HasPOPCNT; }
 563   bool hasAES() const { return HasAES; }
 564   bool hasVAES() const { return HasVAES; }
 565   bool hasFXSR() const { return HasFXSR; }
 566   bool hasXSAVE() const { return HasXSAVE; }
 567   bool hasXSAVEOPT() const { return HasXSAVEOPT; }
 568   bool hasXSAVEC() const { return HasXSAVEC; }
 569   bool hasXSAVES() const { return HasXSAVES; }
 570   bool hasPCLMUL() const { return HasPCLMUL; }
 571   bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
 572   bool hasGFNI() const { return HasGFNI; }
 573   // Prefer FMA4 to FMA - its better for commutation/memory folding and
 574   // has equal or better performance on all supported targets.
 575   bool hasFMA() const { return HasFMA; }
 576   bool hasFMA4() const { return HasFMA4; }
 577   bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
 578   bool hasXOP() const { return HasXOP; }
 579   bool hasTBM() const { return HasTBM; }
 580   bool hasLWP() const { return HasLWP; }
 581   bool hasMOVBE() const { return HasMOVBE; }
 582   bool hasRDRAND() const { return HasRDRAND; }
 583   bool hasF16C() const { return HasF16C; }
 584   bool hasFSGSBase() const { return HasFSGSBase; }
 585   bool hasLZCNT() const { return HasLZCNT; }
 586   bool hasBMI() const { return HasBMI; }
 587   bool hasBMI2() const { return HasBMI2; }
 588   bool hasVBMI() const { return HasVBMI; }
 589   bool hasVBMI2() const { return HasVBMI2; }
 590   bool hasIFMA() const { return HasIFMA; }
 591   bool hasRTM() const { return HasRTM; }
 592   bool hasADX() const { return HasADX; }
 593   bool hasSHA() const { return HasSHA; }
 594   bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
 595   bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
 596   bool hasSSEPrefetch() const {
 597     // We implicitly enable these when we have a write prefix supporting cache
 598     // level OR if we have prfchw, but don't already have a read prefetch from
 599     // 3dnow.
 600     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
 601   }
 602   bool hasRDSEED() const { return HasRDSEED; }
 603   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
 604   bool hasMWAITX() const { return HasMWAITX; }
 605   bool hasCLZERO() const { return HasCLZERO; }
 606   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
 607   bool hasMOVDIRI() const { return HasMOVDIRI; }
 608   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
 609   bool hasPTWRITE() const { return HasPTWRITE; }
 610   bool isSHLDSlow() const { return IsSHLDSlow; }
 611   bool isPMULLDSlow() const { return IsPMULLDSlow; }
 612   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
 613   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
 614   int getGatherOverhead() const { return GatherOverhead; }
 615   int getScatterOverhead() const { return ScatterOverhead; }
 616   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
 617   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
 618   bool useLeaForSP() const { return UseLeaForSP; }
 619   bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
 620   bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
 621   bool hasFastVariableShuffle() const {
 622     return HasFastVariableShuffle;
 623   }
 624   bool hasFastPartialYMMorZMMWrite() const {
 625     return HasFastPartialYMMorZMMWrite;
 626   }
 627   bool hasFastGather() const { return HasFastGather; }
 628   bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
 629   bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
 630   bool hasFastLZCNT() const { return HasFastLZCNT; }
 631   bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
 632   bool hasMacroFusion() const { return HasMacroFusion; }
 633   bool hasERMSB() const { return HasERMSB; }
 634   bool hasSlowDivide32() const { return HasSlowDivide32; }
 635   bool hasSlowDivide64() const { return HasSlowDivide64; }
 636   bool padShortFunctions() const { return PadShortFunctions; }
 637   bool slowTwoMemOps() const { return SlowTwoMemOps; }
 638   bool LEAusesAG() const { return LEAUsesAG; }
 639   bool slowLEA() const { return SlowLEA; }
 640   bool slow3OpsLEA() const { return Slow3OpsLEA; }
 641   bool slowIncDec() const { return SlowIncDec; }
 642   bool hasCDI() const { return HasCDI; }
 643   bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
 644   bool hasPFI() const { return HasPFI; }
 645   bool hasERI() const { return HasERI; }
 646   bool hasDQI() const { return HasDQI; }
 647   bool hasBWI() const { return HasBWI; }
 648   bool hasVLX() const { return HasVLX; }
 649   bool hasPKU() const { return HasPKU; }
 650   bool hasVNNI() const { return HasVNNI; }
 651   bool hasBITALG() const { return HasBITALG; }
 652   bool hasMPX() const { return HasMPX; }
 653   bool hasSHSTK() const { return HasSHSTK; }
 654   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
 655   bool hasCLWB() const { return HasCLWB; }
 656   bool hasWBNOINVD() const { return HasWBNOINVD; }
 657   bool hasRDPID() const { return HasRDPID; }
 658   bool hasWAITPKG() const { return HasWAITPKG; }
 659   bool hasPCONFIG() const { return HasPCONFIG; }
 660   bool hasSGX() const { return HasSGX; }
 661   bool hasINVPCID() const { return HasINVPCID; }
 662   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
 663   bool useRetpolineIndirectBranches() const {
 664     return UseRetpolineIndirectBranches;
 665   }
 666   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 667
 668   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
 669   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
 670
 671   // Helper functions to determine when we should allow widening to 512-bit
 672   // during codegen.
 673   // TODO: Currently we're always allowing widening on CPUs without VLX,
 674   // because for many cases we don't have a better option.
 675   bool canExtendTo512DQ() const {
 676     return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
 677   }
 678   bool canExtendTo512BW() const  {
 679     return hasBWI() && canExtendTo512DQ();
 680   }
 681
 682   // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
 683   // disable them in the legalizer.
 684   bool useAVX512Regs() const {
 685     return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
 686   }
 687
 688   bool useBWIRegs() const {
 689     return hasBWI() && useAVX512Regs();
 690   }
 691
 692   bool isXRaySupported() const override { return is64Bit(); }
 693
 694   X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
 695
 696   /// TODO: to be removed later and replaced with suitable properties
 697   bool isAtom() const { return X86ProcFamily == IntelAtom; }
 698   bool isSLM() const { return X86ProcFamily == IntelSLM; }
 699   bool isGLM() const {
 700     return X86ProcFamily == IntelGLM ||
 701            X86ProcFamily == IntelGLP ||
 702            X86ProcFamily == IntelTRM;
 703   }
 704   bool useSoftFloat() const { return UseSoftFloat; }
 705
 706   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
 707   /// no-sse2). There isn't any reason to disable it if the target processor
 708   /// supports it.
 709   bool hasMFence() const { return hasSSE2() || is64Bit(); }
 710
 711   const Triple &getTargetTriple() const { return TargetTriple; }
 712
 713   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 714   bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
 715   bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
 716   bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
 717   bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
 718
 719   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 720   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 721   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 722
 723   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 724   bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
 725   bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
 726   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 727   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 728   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
 729   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
 730   bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
 731   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 732
 733   bool isTargetWindowsMSVC() const {
 734     return TargetTriple.isWindowsMSVCEnvironment();
 735   }
 736
 737   bool isTargetKnownWindowsMSVC() const {
 738     return TargetTriple.isKnownWindowsMSVCEnvironment();
 739   }
 740
 741   bool isTargetWindowsCoreCLR() const {
 742     return TargetTriple.isWindowsCoreCLREnvironment();
 743   }
 744
 745   bool isTargetWindowsCygwin() const {
 746     return TargetTriple.isWindowsCygwinEnvironment();
 747   }
 748
 749   bool isTargetWindowsGNU() const {
 750     return TargetTriple.isWindowsGNUEnvironment();
 751   }
 752
 753   bool isTargetWindowsItanium() const {
 754     return TargetTriple.isWindowsItaniumEnvironment();
 755   }
 756
 757   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
 758
 759   bool isOSWindows() const { return TargetTriple.isOSWindows(); }
 760
 761   bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
 762
 763   bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
 764
 765   bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
 766   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
 767
 768   bool isPICStyleStubPIC() const {
 769     return PICStyle == PICStyles::StubPIC;
 770   }
 771
 772   bool isPositionIndependent() const { return TM.isPositionIndependent(); }
 773
 774   bool isCallingConvWin64(CallingConv::ID CC) const {
 775     switch (CC) {
 776     // On Win64, all these conventions just use the default convention.
 777     case CallingConv::C:
 778     case CallingConv::Fast:
 779     case CallingConv::Swift:
 780     case CallingConv::X86_FastCall:
 781     case CallingConv::X86_StdCall:
 782     case CallingConv::X86_ThisCall:
 783     case CallingConv::X86_VectorCall:
 784     case CallingConv::Intel_OCL_BI:
 785       return isTargetWin64();
 786     // This convention allows using the Win64 convention on other targets.
 787     case CallingConv::Win64:
 788       return true;
 789     // This convention allows using the SysV convention on Windows targets.
 790     case CallingConv::X86_64_SysV:
 791       return false;
 792     // Otherwise, who knows what this is.
 793     default:
 794       return false;
 795     }
 796   }
 797
 798   /// Classify a global variable reference for the current subtarget according
 799   /// to how we should reference it in a non-pcrel context.
 800   unsigned char classifyLocalReference(const GlobalValue *GV) const;
 801
 802   unsigned char classifyGlobalReference(const GlobalValue *GV,
 803                                         const Module &M) const;
 804   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
 805
 806   /// Classify a global function reference for the current subtarget.
 807   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
 808                                                 const Module &M) const;
 809   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
 810
 811   /// Classify a blockaddress reference for the current subtarget according to
 812   /// how we should reference it in a non-pcrel context.
 813   unsigned char classifyBlockAddressReference() const;
 814
 815   /// Return true if the subtarget allows calls to immediate address.
 816   bool isLegalToCallImmediateAddr() const;
 817
 818   /// If we are using retpolines, we need to expand indirectbr to avoid it
 819   /// lowering to an actual indirect jump.
 820   bool enableIndirectBrExpand() const override {
 821     return useRetpolineIndirectBranches();
 822   }
 823
 824   /// Enable the MachineScheduler pass for all X86 subtargets.
 825   bool enableMachineScheduler() const override { return true; }
 826
 827   // TODO: Update the regression tests and return true.
 828   bool supportPrintSchedInfo() const override { return false; }
 829
 830   bool enableEarlyIfConversion() const override;
 831
 832   AntiDepBreakMode getAntiDepBreakMode() const override {
 833     return TargetSubtargetInfo::ANTIDEP_CRITICAL;
 834   }
 835
 836   bool enableAdvancedRASplitCost() const override { return true; }
 837 };
 838
 839 } // end namespace llvm
 840
 841 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H