lib/Target/PowerPC/PPCRegisterInfo.cpp

   1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the PowerPC implementation of the TargetRegisterInfo
  10 // class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "PPCRegisterInfo.h"
  15 #include "PPCFrameLowering.h"
  16 #include "PPCInstrBuilder.h"
  17 #include "PPCMachineFunctionInfo.h"
  18 #include "PPCSubtarget.h"
  19 #include "PPCTargetMachine.h"
  20 #include "llvm/ADT/BitVector.h"
  21 #include "llvm/ADT/STLExtras.h"
  22 #include "llvm/ADT/Statistic.h"
  23 #include "llvm/CodeGen/MachineFrameInfo.h"
  24 #include "llvm/CodeGen/MachineFunction.h"
  25 #include "llvm/CodeGen/MachineInstrBuilder.h"
  26 #include "llvm/CodeGen/MachineModuleInfo.h"
  27 #include "llvm/CodeGen/MachineRegisterInfo.h"
  28 #include "llvm/CodeGen/RegisterScavenging.h"
  29 #include "llvm/CodeGen/TargetFrameLowering.h"
  30 #include "llvm/CodeGen/TargetInstrInfo.h"
  31 #include "llvm/IR/CallingConv.h"
  32 #include "llvm/IR/Constants.h"
  33 #include "llvm/IR/Function.h"
  34 #include "llvm/IR/Type.h"
  35 #include "llvm/Support/CommandLine.h"
  36 #include "llvm/Support/Debug.h"
  37 #include "llvm/Support/ErrorHandling.h"
  38 #include "llvm/Support/MathExtras.h"
  39 #include "llvm/Support/raw_ostream.h"
  40 #include "llvm/Target/TargetMachine.h"
  41 #include "llvm/Target/TargetOptions.h"
  42 #include <cstdlib>
  43
  44 using namespace llvm;
  45
  46 #define DEBUG_TYPE "reginfo"
  47
  48 #define GET_REGINFO_TARGET_DESC
  49 #include "PPCGenRegisterInfo.inc"
  50
  51 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
  52 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
  53
  54 static cl::opt<bool>
  55 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
  56          cl::desc("Enable use of a base pointer for complex stack frames"));
  57
  58 static cl::opt<bool>
  59 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
  60          cl::desc("Force the use of a base pointer in every function"));
  61
  62 static cl::opt<bool>
  63 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
  64          cl::desc("Enable spills from gpr to vsr rather than stack"));
  65
  66 static cl::opt<bool>
  67 StackPtrConst("ppc-stack-ptr-caller-preserved",
  68                 cl::desc("Consider R1 caller preserved so stack saves of "
  69                          "caller preserved registers can be LICM candidates"),
  70                 cl::init(true), cl::Hidden);
  71
  72 static cl::opt<unsigned>
  73 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
  74                   cl::desc("Maximum search distance for definition of CR bit "
  75                            "spill on ppc"),
  76                   cl::Hidden, cl::init(100));
  77
  78 static unsigned offsetMinAlignForOpcode(unsigned OpC);
  79
  80 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
  81   : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
  82                        TM.isPPC64() ? 0 : 1,
  83                        TM.isPPC64() ? 0 : 1),
  84     TM(TM) {
  85   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
  86   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
  87   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
  88   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
  89   ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
  90   ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
  91   ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
  92   ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
  93   ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
  94
  95   // 64-bit
  96   ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
  97   ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
  98   ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
  99   ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
 100   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
 101
 102   // VSX
 103   ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
 104   ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
 105   ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
 106   ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
 107   ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
 108   ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
 109   ImmToIdxMap[PPC::LXV] = PPC::LXVX;
 110   ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
 111   ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
 112   ImmToIdxMap[PPC::STXV] = PPC::STXVX;
 113   ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
 114   ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
 115
 116   // SPE
 117   ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
 118   ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
 119   ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
 120   ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
 121 }
 122
 123 /// getPointerRegClass - Return the register class to use to hold pointers.
 124 /// This is used for addressing modes.
 125 const TargetRegisterClass *
 126 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
 127                                                                        const {
 128   // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
 129   // when it checks for ZERO folding.
 130   if (Kind == 1) {
 131     if (TM.isPPC64())
 132       return &PPC::G8RC_NOX0RegClass;
 133     return &PPC::GPRC_NOR0RegClass;
 134   }
 135
 136   if (TM.isPPC64())
 137     return &PPC::G8RCRegClass;
 138   return &PPC::GPRCRegClass;
 139 }
 140
 141 const MCPhysReg*
 142 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 143   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
 144   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
 145     if (Subtarget.hasVSX())
 146       return CSR_64_AllRegs_VSX_SaveList;
 147     if (Subtarget.hasAltivec())
 148       return CSR_64_AllRegs_Altivec_SaveList;
 149     return CSR_64_AllRegs_SaveList;
 150   }
 151
 152   if (Subtarget.isDarwinABI())
 153     return TM.isPPC64()
 154                ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
 155                                          : CSR_Darwin64_SaveList)
 156                : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
 157                                          : CSR_Darwin32_SaveList);
 158
 159   if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
 160     return CSR_SRV464_TLS_PE_SaveList;
 161
 162   if (Subtarget.hasSPE())
 163     return CSR_SVR432_SPE_SaveList;
 164
 165   // On PPC64, we might need to save r2 (but only if it is not reserved).
 166   bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
 167
 168   if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
 169     return TM.isPPC64()
 170                ? (Subtarget.hasAltivec()
 171                       ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
 172                                 : CSR_SVR64_ColdCC_Altivec_SaveList)
 173                       : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
 174                                 : CSR_SVR64_ColdCC_SaveList))
 175                : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList
 176                                          : CSR_SVR32_ColdCC_SaveList);
 177   }
 178
 179   return TM.isPPC64()
 180              ? (Subtarget.hasAltivec()
 181                     ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
 182                               : CSR_SVR464_Altivec_SaveList)
 183                     : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
 184              : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
 185                                        : CSR_SVR432_SaveList);
 186 }
 187
 188 const MCPhysReg *
 189 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
 190   assert(MF && "Invalid MachineFunction pointer.");
 191   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
 192   if (Subtarget.isDarwinABI())
 193     return nullptr;
 194   if (!TM.isPPC64())
 195     return nullptr;
 196   if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS)
 197     return nullptr;
 198   if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
 199     return nullptr;
 200
 201   // On PPC64, we might need to save r2 (but only if it is not reserved).
 202   bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
 203   if (Subtarget.hasAltivec())
 204     return SaveR2
 205       ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
 206       : CSR_SVR464_Altivec_ViaCopy_SaveList;
 207   else
 208     return SaveR2
 209       ? CSR_SVR464_R2_ViaCopy_SaveList
 210       : CSR_SVR464_ViaCopy_SaveList;
 211 }
 212
 213 const uint32_t *
 214 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
 215                                       CallingConv::ID CC) const {
 216   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 217   if (CC == CallingConv::AnyReg) {
 218     if (Subtarget.hasVSX())
 219       return CSR_64_AllRegs_VSX_RegMask;
 220     if (Subtarget.hasAltivec())
 221       return CSR_64_AllRegs_Altivec_RegMask;
 222     return CSR_64_AllRegs_RegMask;
 223   }
 224
 225   if (Subtarget.isDarwinABI())
 226     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
 227                                                   : CSR_Darwin64_RegMask)
 228                         : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
 229                                                   : CSR_Darwin32_RegMask);
 230   if (Subtarget.isAIXABI()) {
 231     assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
 232     return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask;
 233   }
 234
 235   if (CC == CallingConv::Cold) {
 236     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
 237                                                   : CSR_SVR64_ColdCC_RegMask)
 238                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
 239                                                   : CSR_SVR32_ColdCC_RegMask);
 240   }
 241
 242   return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
 243                                                 : CSR_SVR464_RegMask)
 244                       : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
 245                                                 : CSR_SVR432_RegMask);
 246 }
 247
 248 const uint32_t*
 249 PPCRegisterInfo::getNoPreservedMask() const {
 250   return CSR_NoRegs_RegMask;
 251 }
 252
 253 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
 254   for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
 255     Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
 256 }
 257
 258 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 259   BitVector Reserved(getNumRegs());
 260   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 261   const PPCFrameLowering *TFI = getFrameLowering(MF);
 262
 263   // The ZERO register is not really a register, but the representation of r0
 264   // when used in instructions that treat r0 as the constant 0.
 265   markSuperRegs(Reserved, PPC::ZERO);
 266
 267   // The FP register is also not really a register, but is the representation
 268   // of the frame pointer register used by ISD::FRAMEADDR.
 269   markSuperRegs(Reserved, PPC::FP);
 270
 271   // The BP register is also not really a register, but is the representation
 272   // of the base pointer register used by setjmp.
 273   markSuperRegs(Reserved, PPC::BP);
 274
 275   // The counter registers must be reserved so that counter-based loops can
 276   // be correctly formed (and the mtctr instructions are not DCE'd).
 277   markSuperRegs(Reserved, PPC::CTR);
 278   markSuperRegs(Reserved, PPC::CTR8);
 279
 280   markSuperRegs(Reserved, PPC::R1);
 281   markSuperRegs(Reserved, PPC::LR);
 282   markSuperRegs(Reserved, PPC::LR8);
 283   markSuperRegs(Reserved, PPC::RM);
 284
 285   if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
 286     markSuperRegs(Reserved, PPC::VRSAVE);
 287
 288   // The SVR4 ABI reserves r2 and r13
 289   if (Subtarget.isSVR4ABI()) {
 290     // We only reserve r2 if we need to use the TOC pointer. If we have no
 291     // explicit uses of the TOC pointer (meaning we're a leaf function with
 292     // no constant-pool loads, etc.) and we have no potential uses inside an
 293     // inline asm block, then we can treat r2 has an ordinary callee-saved
 294     // register.
 295     const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
 296     if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
 297       markSuperRegs(Reserved, PPC::R2);  // System-reserved register
 298     markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
 299   }
 300
 301   // Always reserve r2 on AIX for now.
 302   // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
 303   if (Subtarget.isAIXABI())
 304     markSuperRegs(Reserved, PPC::R2);  // System-reserved register
 305
 306   // On PPC64, r13 is the thread pointer. Never allocate this register.
 307   if (TM.isPPC64())
 308     markSuperRegs(Reserved, PPC::R13);
 309
 310   if (TFI->needsFP(MF))
 311     markSuperRegs(Reserved, PPC::R31);
 312
 313   bool IsPositionIndependent = TM.isPositionIndependent();
 314   if (hasBasePointer(MF)) {
 315     if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
 316       markSuperRegs(Reserved, PPC::R29);
 317     else
 318       markSuperRegs(Reserved, PPC::R30);
 319   }
 320
 321   if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
 322     markSuperRegs(Reserved, PPC::R30);
 323
 324   // Reserve Altivec registers when Altivec is unavailable.
 325   if (!Subtarget.hasAltivec())
 326     for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
 327          IE = PPC::VRRCRegClass.end(); I != IE; ++I)
 328       markSuperRegs(Reserved, *I);
 329
 330   assert(checkAllSuperRegsMarked(Reserved));
 331   return Reserved;
 332 }
 333
 334 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
 335   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 336   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
 337   const MachineFrameInfo &MFI = MF.getFrameInfo();
 338   const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
 339
 340   // If the callee saved info is invalid we have to default to true for safety.
 341   if (!MFI.isCalleeSavedInfoValid())
 342     return true;
 343
 344   // We will require the use of X-Forms because the frame is larger than what
 345   // can be represented in signed 16 bits that fit in the immediate of a D-Form.
 346   // If we need an X-Form then we need a register to store the address offset.
 347   unsigned FrameSize = MFI.getStackSize();
 348   // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
 349   if (FrameSize & ~0x7FFF)
 350     return true;
 351
 352   // The callee saved info is valid so it can be traversed.
 353   // Checking for registers that need saving that do not have load or store
 354   // forms where the address offset is an immediate.
 355   for (unsigned i = 0; i < Info.size(); i++) {
 356     int FrIdx = Info[i].getFrameIdx();
 357     unsigned Reg = Info[i].getReg();
 358
 359     unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(Reg);
 360     if (!MFI.isFixedObjectIndex(FrIdx)) {
 361       // This is not a fixed object. If it requires alignment then we may still
 362       // need to use the XForm.
 363       if (offsetMinAlignForOpcode(Opcode) > 1)
 364         return true;
 365     }
 366
 367     // This is eiher:
 368     // 1) A fixed frame index object which we know are aligned so
 369     // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
 370     // need to consider the alignement here.
 371     // 2) A not fixed object but in that case we now know that the min required
 372     // alignment is no more than 1 based on the previous check.
 373     if (InstrInfo->isXFormMemOp(Opcode))
 374       return true;
 375   }
 376   return false;
 377 }
 378
 379 bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
 380                                                const MachineFunction &MF) const {
 381   assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
 382   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 383   const MachineFrameInfo &MFI = MF.getFrameInfo();
 384   if (!TM.isPPC64())
 385     return false;
 386
 387   if (!Subtarget.isSVR4ABI())
 388     return false;
 389   if (PhysReg == PPC::X2)
 390     // X2 is guaranteed to be preserved within a function if it is reserved.
 391     // The reason it's reserved is that it's the TOC pointer (and the function
 392     // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
 393     // with no TOC access), we can't claim that it is preserved.
 394     return (getReservedRegs(MF).test(PPC::X2));
 395   if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
 396       && !MFI.hasOpaqueSPAdjustment())
 397     // The value of the stack pointer does not change within a function after
 398     // the prologue and before the epilogue if there are no dynamic allocations
 399     // and no inline asm which clobbers X1.
 400     return true;
 401   return false;
 402 }
 403
 404 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
 405                                               MachineFunction &MF) const {
 406   const PPCFrameLowering *TFI = getFrameLowering(MF);
 407   const unsigned DefaultSafety = 1;
 408
 409   switch (RC->getID()) {
 410   default:
 411     return 0;
 412   case PPC::G8RC_NOX0RegClassID:
 413   case PPC::GPRC_NOR0RegClassID:
 414   case PPC::SPERCRegClassID:
 415   case PPC::SPE4RCRegClassID:
 416   case PPC::G8RCRegClassID:
 417   case PPC::GPRCRegClassID: {
 418     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
 419     return 32 - FP - DefaultSafety;
 420   }
 421   case PPC::F8RCRegClassID:
 422   case PPC::F4RCRegClassID:
 423   case PPC::QFRCRegClassID:
 424   case PPC::QSRCRegClassID:
 425   case PPC::QBRCRegClassID:
 426   case PPC::VRRCRegClassID:
 427   case PPC::VFRCRegClassID:
 428   case PPC::VSLRCRegClassID:
 429     return 32 - DefaultSafety;
 430   case PPC::VSRCRegClassID:
 431   case PPC::VSFRCRegClassID:
 432   case PPC::VSSRCRegClassID:
 433     return 64 - DefaultSafety;
 434   case PPC::CRRCRegClassID:
 435     return 8 - DefaultSafety;
 436   }
 437 }
 438
 439 const TargetRegisterClass *
 440 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
 441                                            const MachineFunction &MF) const {
 442   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 443   if (Subtarget.hasVSX()) {
 444     // With VSX, we can inflate various sub-register classes to the full VSX
 445     // register set.
 446
 447     // For Power9 we allow the user to enable GPR to vector spills.
 448     // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
 449     // support to spill GPRC.
 450     if (TM.isELFv2ABI()) {
 451       if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
 452           RC == &PPC::G8RCRegClass) {
 453         InflateGP8RC++;
 454         return &PPC::SPILLTOVSRRCRegClass;
 455       }
 456       if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
 457         InflateGPRC++;
 458     }
 459     if (RC == &PPC::F8RCRegClass)
 460       return &PPC::VSFRCRegClass;
 461     else if (RC == &PPC::VRRCRegClass)
 462       return &PPC::VSRCRegClass;
 463     else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
 464       return &PPC::VSSRCRegClass;
 465   }
 466
 467   return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
 468 }
 469
 470 //===----------------------------------------------------------------------===//
 471 // Stack Frame Processing methods
 472 //===----------------------------------------------------------------------===//
 473
 474 /// lowerDynamicAlloc - Generate the code for allocating an object in the
 475 /// current frame.  The sequence of code will be in the general form
 476 ///
 477 ///   addi   R0, SP, \#frameSize ; get the address of the previous frame
 478 ///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
 479 ///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
 480 ///
 481 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
 482   // Get the instruction.
 483   MachineInstr &MI = *II;
 484   // Get the instruction's basic block.
 485   MachineBasicBlock &MBB = *MI.getParent();
 486   // Get the basic block's function.
 487   MachineFunction &MF = *MBB.getParent();
 488   // Get the frame info.
 489   MachineFrameInfo &MFI = MF.getFrameInfo();
 490   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 491   // Get the instruction info.
 492   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 493   // Determine whether 64-bit pointers are used.
 494   bool LP64 = TM.isPPC64();
 495   DebugLoc dl = MI.getDebugLoc();
 496
 497   // Get the maximum call stack size.
 498   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
 499   // Get the total frame size.
 500   unsigned FrameSize = MFI.getStackSize();
 501
 502   // Get stack alignments.
 503   const PPCFrameLowering *TFI = getFrameLowering(MF);
 504   unsigned TargetAlign = TFI->getStackAlignment();
 505   unsigned MaxAlign = MFI.getMaxAlignment();
 506   assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
 507          "Maximum call-frame size not sufficiently aligned");
 508
 509   // Determine the previous frame's address.  If FrameSize can't be
 510   // represented as 16 bits or we need special alignment, then we load the
 511   // previous frame's address from 0(SP).  Why not do an addis of the hi?
 512   // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
 513   // Constructing the constant and adding would take 3 instructions.
 514   // Fortunately, a frame greater than 32K is rare.
 515   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
 516   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 517   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 518
 519   if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
 520     if (LP64)
 521       BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
 522         .addReg(PPC::X31)
 523         .addImm(FrameSize);
 524     else
 525       BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
 526         .addReg(PPC::R31)
 527         .addImm(FrameSize);
 528   } else if (LP64) {
 529     BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
 530       .addImm(0)
 531       .addReg(PPC::X1);
 532   } else {
 533     BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
 534       .addImm(0)
 535       .addReg(PPC::R1);
 536   }
 537
 538   bool KillNegSizeReg = MI.getOperand(1).isKill();
 539   unsigned NegSizeReg = MI.getOperand(1).getReg();
 540
 541   // Grow the stack and update the stack pointer link, then determine the
 542   // address of new allocated space.
 543   if (LP64) {
 544     if (MaxAlign > TargetAlign) {
 545       unsigned UnalNegSizeReg = NegSizeReg;
 546       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
 547
 548       // Unfortunately, there is no andi, only andi., and we can't insert that
 549       // here because we might clobber cr0 while it is live.
 550       BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
 551         .addImm(~(MaxAlign-1));
 552
 553       unsigned NegSizeReg1 = NegSizeReg;
 554       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
 555       BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
 556         .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
 557         .addReg(NegSizeReg1, RegState::Kill);
 558       KillNegSizeReg = true;
 559     }
 560
 561     BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
 562       .addReg(Reg, RegState::Kill)
 563       .addReg(PPC::X1)
 564       .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
 565     BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
 566       .addReg(PPC::X1)
 567       .addImm(maxCallFrameSize);
 568   } else {
 569     if (MaxAlign > TargetAlign) {
 570       unsigned UnalNegSizeReg = NegSizeReg;
 571       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
 572
 573       // Unfortunately, there is no andi, only andi., and we can't insert that
 574       // here because we might clobber cr0 while it is live.
 575       BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
 576         .addImm(~(MaxAlign-1));
 577
 578       unsigned NegSizeReg1 = NegSizeReg;
 579       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
 580       BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
 581         .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
 582         .addReg(NegSizeReg1, RegState::Kill);
 583       KillNegSizeReg = true;
 584     }
 585
 586     BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
 587       .addReg(Reg, RegState::Kill)
 588       .addReg(PPC::R1)
 589       .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
 590     BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
 591       .addReg(PPC::R1)
 592       .addImm(maxCallFrameSize);
 593   }
 594
 595   // Discard the DYNALLOC instruction.
 596   MBB.erase(II);
 597 }
 598
 599 void PPCRegisterInfo::lowerDynamicAreaOffset(
 600     MachineBasicBlock::iterator II) const {
 601   // Get the instruction.
 602   MachineInstr &MI = *II;
 603   // Get the instruction's basic block.
 604   MachineBasicBlock &MBB = *MI.getParent();
 605   // Get the basic block's function.
 606   MachineFunction &MF = *MBB.getParent();
 607   // Get the frame info.
 608   MachineFrameInfo &MFI = MF.getFrameInfo();
 609   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 610   // Get the instruction info.
 611   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 612
 613   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
 614   bool is64Bit = TM.isPPC64();
 615   DebugLoc dl = MI.getDebugLoc();
 616   BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
 617           MI.getOperand(0).getReg())
 618       .addImm(maxCallFrameSize);
 619   MBB.erase(II);
 620 }
 621
 622 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
 623 /// reserving a whole register (R0), we scrounge for one here. This generates
 624 /// code like this:
 625 ///
 626 ///   mfcr rA                  ; Move the conditional register into GPR rA.
 627 ///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
 628 ///   stw rA, FI               ; Store rA to the frame.
 629 ///
 630 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
 631                                       unsigned FrameIndex) const {
 632   // Get the instruction.
 633   MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
 634   // Get the instruction's basic block.
 635   MachineBasicBlock &MBB = *MI.getParent();
 636   MachineFunction &MF = *MBB.getParent();
 637   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 638   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 639   DebugLoc dl = MI.getDebugLoc();
 640
 641   bool LP64 = TM.isPPC64();
 642   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
 643   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 644
 645   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 646   unsigned SrcReg = MI.getOperand(0).getReg();
 647
 648   // We need to store the CR in the low 4-bits of the saved value. First, issue
 649   // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
 650   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
 651       .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
 652
 653   // If the saved register wasn't CR0, shift the bits left so that they are in
 654   // CR0's slot.
 655   if (SrcReg != PPC::CR0) {
 656     unsigned Reg1 = Reg;
 657     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 658
 659     // rlwinm rA, rA, ShiftBits, 0, 31.
 660     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
 661       .addReg(Reg1, RegState::Kill)
 662       .addImm(getEncodingValue(SrcReg) * 4)
 663       .addImm(0)
 664       .addImm(31);
 665   }
 666
 667   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
 668                     .addReg(Reg, RegState::Kill),
 669                     FrameIndex);
 670
 671   // Discard the pseudo instruction.
 672   MBB.erase(II);
 673 }
 674
 675 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
 676                                       unsigned FrameIndex) const {
 677   // Get the instruction.
 678   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
 679   // Get the instruction's basic block.
 680   MachineBasicBlock &MBB = *MI.getParent();
 681   MachineFunction &MF = *MBB.getParent();
 682   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 683   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 684   DebugLoc dl = MI.getDebugLoc();
 685
 686   bool LP64 = TM.isPPC64();
 687   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
 688   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 689
 690   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 691   unsigned DestReg = MI.getOperand(0).getReg();
 692   assert(MI.definesRegister(DestReg) &&
 693     "RESTORE_CR does not define its destination");
 694
 695   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
 696                               Reg), FrameIndex);
 697
 698   // If the reloaded register isn't CR0, shift the bits right so that they are
 699   // in the right CR's slot.
 700   if (DestReg != PPC::CR0) {
 701     unsigned Reg1 = Reg;
 702     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 703
 704     unsigned ShiftBits = getEncodingValue(DestReg)*4;
 705     // rlwinm r11, r11, 32-ShiftBits, 0, 31.
 706     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
 707              .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
 708              .addImm(31);
 709   }
 710
 711   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
 712              .addReg(Reg, RegState::Kill);
 713
 714   // Discard the pseudo instruction.
 715   MBB.erase(II);
 716 }
 717
 718 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
 719                                          unsigned FrameIndex) const {
 720   // Get the instruction.
 721   MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
 722   // Get the instruction's basic block.
 723   MachineBasicBlock &MBB = *MI.getParent();
 724   MachineFunction &MF = *MBB.getParent();
 725   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 726   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 727   const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
 728   DebugLoc dl = MI.getDebugLoc();
 729
 730   bool LP64 = TM.isPPC64();
 731   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
 732   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 733
 734   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 735   unsigned SrcReg = MI.getOperand(0).getReg();
 736
 737   // Search up the BB to find the definition of the CR bit.
 738   MachineBasicBlock::reverse_iterator Ins;
 739   unsigned CRBitSpillDistance = 0;
 740   for (Ins = MI; Ins != MBB.rend(); Ins++) {
 741     // Definition found.
 742     if (Ins->modifiesRegister(SrcReg, TRI))
 743       break;
 744     // Unable to find CR bit definition within maximum search distance.
 745     if (CRBitSpillDistance == MaxCRBitSpillDist) {
 746       Ins = MI;
 747       break;
 748     }
 749     // Skip debug instructions when counting CR bit spill distance.
 750     if (!Ins->isDebugInstr())
 751       CRBitSpillDistance++;
 752   }
 753
 754   // Unable to find the definition of the CR bit in the MBB.
 755   if (Ins == MBB.rend())
 756     Ins = MI;
 757
 758   // There is no need to extract the CR bit if its value is already known.
 759   switch (Ins->getOpcode()) {
 760   case PPC::CRUNSET:
 761     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
 762       .addImm(0);
 763     break;
 764   case PPC::CRSET:
 765     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
 766       .addImm(-32768);
 767     break;
 768   default:
 769     // We need to move the CR field that contains the CR bit we are spilling.
 770     // The super register may not be explicitly defined (i.e. it can be defined
 771     // by a CR-logical that only defines the subreg) so we state that the CR
 772     // field is undef. Also, in order to preserve the kill flag on the CR bit,
 773     // we add it as an implicit use.
 774     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
 775       .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
 776       .addReg(SrcReg,
 777               RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
 778
 779     // If the saved register wasn't CR0LT, shift the bits left so that the bit
 780     // to store is the first one. Mask all but that bit.
 781     unsigned Reg1 = Reg;
 782     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 783
 784     // rlwinm rA, rA, ShiftBits, 0, 0.
 785     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
 786       .addReg(Reg1, RegState::Kill)
 787       .addImm(getEncodingValue(SrcReg))
 788       .addImm(0).addImm(0);
 789   }
 790   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
 791                     .addReg(Reg, RegState::Kill),
 792                     FrameIndex);
 793
 794   // Discard the pseudo instruction.
 795   MBB.erase(II);
 796 }
 797
 798 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
 799                                       unsigned FrameIndex) const {
 800   // Get the instruction.
 801   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
 802   // Get the instruction's basic block.
 803   MachineBasicBlock &MBB = *MI.getParent();
 804   MachineFunction &MF = *MBB.getParent();
 805   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 806   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 807   DebugLoc dl = MI.getDebugLoc();
 808
 809   bool LP64 = TM.isPPC64();
 810   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
 811   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 812
 813   unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 814   unsigned DestReg = MI.getOperand(0).getReg();
 815   assert(MI.definesRegister(DestReg) &&
 816     "RESTORE_CRBIT does not define its destination");
 817
 818   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
 819                               Reg), FrameIndex);
 820
 821   BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
 822
 823   unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
 824   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
 825           .addReg(getCRFromCRBit(DestReg));
 826
 827   unsigned ShiftBits = getEncodingValue(DestReg);
 828   // rlwimi r11, r10, 32-ShiftBits, ..., ...
 829   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
 830       .addReg(RegO, RegState::Kill)
 831       .addReg(Reg, RegState::Kill)
 832       .addImm(ShiftBits ? 32 - ShiftBits : 0)
 833       .addImm(ShiftBits)
 834       .addImm(ShiftBits);
 835
 836   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
 837           getCRFromCRBit(DestReg))
 838       .addReg(RegO, RegState::Kill)
 839       // Make sure we have a use dependency all the way through this
 840       // sequence of instructions. We can't have the other bits in the CR
 841       // modified in between the mfocrf and the mtocrf.
 842       .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
 843
 844   // Discard the pseudo instruction.
 845   MBB.erase(II);
 846 }
 847
 848 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
 849                                           unsigned FrameIndex) const {
 850   // Get the instruction.
 851   MachineInstr &MI = *II;       // ; SPILL_VRSAVE <SrcReg>, <offset>
 852   // Get the instruction's basic block.
 853   MachineBasicBlock &MBB = *MI.getParent();
 854   MachineFunction &MF = *MBB.getParent();
 855   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 856   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 857   DebugLoc dl = MI.getDebugLoc();
 858
 859   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 860   unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
 861   unsigned SrcReg = MI.getOperand(0).getReg();
 862
 863   BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
 864       .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
 865
 866   addFrameReference(
 867       BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
 868       FrameIndex);
 869
 870   // Discard the pseudo instruction.
 871   MBB.erase(II);
 872 }
 873
 874 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
 875                                          unsigned FrameIndex) const {
 876   // Get the instruction.
 877   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_VRSAVE <offset>
 878   // Get the instruction's basic block.
 879   MachineBasicBlock &MBB = *MI.getParent();
 880   MachineFunction &MF = *MBB.getParent();
 881   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 882   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 883   DebugLoc dl = MI.getDebugLoc();
 884
 885   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 886   unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
 887   unsigned DestReg = MI.getOperand(0).getReg();
 888   assert(MI.definesRegister(DestReg) &&
 889     "RESTORE_VRSAVE does not define its destination");
 890
 891   addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
 892                               Reg), FrameIndex);
 893
 894   BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
 895              .addReg(Reg, RegState::Kill);
 896
 897   // Discard the pseudo instruction.
 898   MBB.erase(II);
 899 }
 900
 901 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
 902                                            unsigned Reg, int &FrameIdx) const {
 903   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 904   // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
 905   // ABI, return true to prevent allocating an additional frame slot.
 906   // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
 907   // is arbitrary and will be subsequently ignored.  For 32-bit, we have
 908   // previously created the stack slot if needed, so return its FrameIdx.
 909   if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
 910     if (TM.isPPC64())
 911       FrameIdx = 0;
 912     else {
 913       const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
 914       FrameIdx = FI->getCRSpillFrameIndex();
 915     }
 916     return true;
 917   }
 918   return false;
 919 }
 920
 921 // If the offset must be a multiple of some value, return what that value is.
 922 static unsigned offsetMinAlignForOpcode(unsigned OpC) {
 923   switch (OpC) {
 924   default:
 925     return 1;
 926   case PPC::LWA:
 927   case PPC::LWA_32:
 928   case PPC::LD:
 929   case PPC::LDU:
 930   case PPC::STD:
 931   case PPC::STDU:
 932   case PPC::DFLOADf32:
 933   case PPC::DFLOADf64:
 934   case PPC::DFSTOREf32:
 935   case PPC::DFSTOREf64:
 936   case PPC::LXSD:
 937   case PPC::LXSSP:
 938   case PPC::STXSD:
 939   case PPC::STXSSP:
 940     return 4;
 941   case PPC::LXV:
 942   case PPC::STXV:
 943     return 16;
 944   }
 945 }
 946
 947 // If the offset must be a multiple of some value, return what that value is.
 948 static unsigned offsetMinAlign(const MachineInstr &MI) {
 949   unsigned OpC = MI.getOpcode();
 950   return offsetMinAlignForOpcode(OpC);
 951 }
 952
 953 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
 954 static unsigned getOffsetONFromFION(const MachineInstr &MI,
 955                                     unsigned FIOperandNum) {
 956   // Take into account whether it's an add or mem instruction
 957   unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
 958   if (MI.isInlineAsm())
 959     OffsetOperandNo = FIOperandNum - 1;
 960   else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
 961            MI.getOpcode() == TargetOpcode::PATCHPOINT)
 962     OffsetOperandNo = FIOperandNum + 1;
 963
 964   return OffsetOperandNo;
 965 }
 966
 967 void
 968 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 969                                      int SPAdj, unsigned FIOperandNum,
 970                                      RegScavenger *RS) const {
 971   assert(SPAdj == 0 && "Unexpected");
 972
 973   // Get the instruction.
 974   MachineInstr &MI = *II;
 975   // Get the instruction's basic block.
 976   MachineBasicBlock &MBB = *MI.getParent();
 977   // Get the basic block's function.
 978   MachineFunction &MF = *MBB.getParent();
 979   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
 980   // Get the instruction info.
 981   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
 982   // Get the frame info.
 983   MachineFrameInfo &MFI = MF.getFrameInfo();
 984   DebugLoc dl = MI.getDebugLoc();
 985
 986   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
 987
 988   // Get the frame index.
 989   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 990
 991   // Get the frame pointer save index.  Users of this index are primarily
 992   // DYNALLOC instructions.
 993   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
 994   int FPSI = FI->getFramePointerSaveIndex();
 995   // Get the instruction opcode.
 996   unsigned OpC = MI.getOpcode();
 997
 998   if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
 999     lowerDynamicAreaOffset(II);
1000     return;
1001   }
1002
1003   // Special case for dynamic alloca.
1004   if (FPSI && FrameIndex == FPSI &&
1005       (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
1006     lowerDynamicAlloc(II);
1007     return;
1008   }
1009
1010   // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1011   if (OpC == PPC::SPILL_CR) {
1012     lowerCRSpilling(II, FrameIndex);
1013     return;
1014   } else if (OpC == PPC::RESTORE_CR) {
1015     lowerCRRestore(II, FrameIndex);
1016     return;
1017   } else if (OpC == PPC::SPILL_CRBIT) {
1018     lowerCRBitSpilling(II, FrameIndex);
1019     return;
1020   } else if (OpC == PPC::RESTORE_CRBIT) {
1021     lowerCRBitRestore(II, FrameIndex);
1022     return;
1023   } else if (OpC == PPC::SPILL_VRSAVE) {
1024     lowerVRSAVESpilling(II, FrameIndex);
1025     return;
1026   } else if (OpC == PPC::RESTORE_VRSAVE) {
1027     lowerVRSAVERestore(II, FrameIndex);
1028     return;
1029   }
1030
1031   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1032   MI.getOperand(FIOperandNum).ChangeToRegister(
1033     FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1034
1035   // If the instruction is not present in ImmToIdxMap, then it has no immediate
1036   // form (and must be r+r).
1037   bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1038                    OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
1039
1040   // Now add the frame object offset to the offset from r1.
1041   int Offset = MFI.getObjectOffset(FrameIndex);
1042   Offset += MI.getOperand(OffsetOperandNo).getImm();
1043
1044   // If we're not using a Frame Pointer that has been set to the value of the
1045   // SP before having the stack size subtracted from it, then add the stack size
1046   // to Offset to get the correct offset.
1047   // Naked functions have stack size 0, although getStackSize may not reflect
1048   // that because we didn't call all the pieces that compute it for naked
1049   // functions.
1050   if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1051     if (!(hasBasePointer(MF) && FrameIndex < 0))
1052       Offset += MFI.getStackSize();
1053   }
1054
1055   // If we can, encode the offset directly into the instruction.  If this is a
1056   // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
1057   // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1058   // clear can be encoded.  This is extremely uncommon, because normally you
1059   // only "std" to a stack slot that is at least 4-byte aligned, but it can
1060   // happen in invalid code.
1061   assert(OpC != PPC::DBG_VALUE &&
1062          "This should be handled in a target-independent way");
1063   if (!noImmForm && ((isInt<16>(Offset) &&
1064                       ((Offset % offsetMinAlign(MI)) == 0)) ||
1065                      OpC == TargetOpcode::STACKMAP ||
1066                      OpC == TargetOpcode::PATCHPOINT)) {
1067     MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1068     return;
1069   }
1070
1071   // The offset doesn't fit into a single register, scavenge one to build the
1072   // offset in.
1073
1074   bool is64Bit = TM.isPPC64();
1075   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1076   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1077   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1078   unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1079            SReg = MF.getRegInfo().createVirtualRegister(RC);
1080
1081   // Insert a set of rA with the full offset value before the ld, st, or add
1082   if (isInt<16>(Offset))
1083     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1084       .addImm(Offset);
1085   else {
1086     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1087       .addImm(Offset >> 16);
1088     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1089       .addReg(SRegHi, RegState::Kill)
1090       .addImm(Offset);
1091   }
1092
1093   // Convert into indexed form of the instruction:
1094   //
1095   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1096   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1097   unsigned OperandBase;
1098
1099   if (noImmForm)
1100     OperandBase = 1;
1101   else if (OpC != TargetOpcode::INLINEASM &&
1102            OpC != TargetOpcode::INLINEASM_BR) {
1103     assert(ImmToIdxMap.count(OpC) &&
1104            "No indexed form of load or store available!");
1105     unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1106     MI.setDesc(TII.get(NewOpcode));
1107     OperandBase = 1;
1108   } else {
1109     OperandBase = OffsetOperandNo;
1110   }
1111
1112   unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
1113   MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1114   MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1115 }
1116
1117 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1118   const PPCFrameLowering *TFI = getFrameLowering(MF);
1119
1120   if (!TM.isPPC64())
1121     return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1122   else
1123     return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1124 }
1125
1126 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1127   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1128   if (!hasBasePointer(MF))
1129     return getFrameRegister(MF);
1130
1131   if (TM.isPPC64())
1132     return PPC::X30;
1133
1134   if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1135     return PPC::R29;
1136
1137   return PPC::R30;
1138 }
1139
1140 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1141   if (!EnableBasePointer)
1142     return false;
1143   if (AlwaysBasePointer)
1144     return true;
1145
1146   // If we need to realign the stack, then the stack pointer can no longer
1147   // serve as an offset into the caller's stack space. As a result, we need a
1148   // base pointer.
1149   return needsStackRealignment(MF);
1150 }
1151
1152 /// Returns true if the instruction's frame index
1153 /// reference would be better served by a base register other than FP
1154 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1155 /// references it should create new base registers for.
1156 bool PPCRegisterInfo::
1157 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1158   assert(Offset < 0 && "Local offset must be negative");
1159
1160   // It's the load/store FI references that cause issues, as it can be difficult
1161   // to materialize the offset if it won't fit in the literal field. Estimate
1162   // based on the size of the local frame and some conservative assumptions
1163   // about the rest of the stack frame (note, this is pre-regalloc, so
1164   // we don't know everything for certain yet) whether this offset is likely
1165   // to be out of range of the immediate. Return true if so.
1166
1167   // We only generate virtual base registers for loads and stores that have
1168   // an r+i form. Return false for everything else.
1169   unsigned OpC = MI->getOpcode();
1170   if (!ImmToIdxMap.count(OpC))
1171     return false;
1172
1173   // Don't generate a new virtual base register just to add zero to it.
1174   if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1175       MI->getOperand(2).getImm() == 0)
1176     return false;
1177
1178   MachineBasicBlock &MBB = *MI->getParent();
1179   MachineFunction &MF = *MBB.getParent();
1180   const PPCFrameLowering *TFI = getFrameLowering(MF);
1181   unsigned StackEst = TFI->determineFrameLayout(MF, true);
1182
1183   // If we likely don't need a stack frame, then we probably don't need a
1184   // virtual base register either.
1185   if (!StackEst)
1186     return false;
1187
1188   // Estimate an offset from the stack pointer.
1189   // The incoming offset is relating to the SP at the start of the function,
1190   // but when we access the local it'll be relative to the SP after local
1191   // allocation, so adjust our SP-relative offset by that allocation size.
1192   Offset += StackEst;
1193
1194   // The frame pointer will point to the end of the stack, so estimate the
1195   // offset as the difference between the object offset and the FP location.
1196   return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1197 }
1198
1199 /// Insert defining instruction(s) for BaseReg to
1200 /// be a pointer to FrameIdx at the beginning of the basic block.
1201 void PPCRegisterInfo::
1202 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1203                              unsigned BaseReg, int FrameIdx,
1204                              int64_t Offset) const {
1205   unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1206
1207   MachineBasicBlock::iterator Ins = MBB->begin();
1208   DebugLoc DL;                  // Defaults to "unknown"
1209   if (Ins != MBB->end())
1210     DL = Ins->getDebugLoc();
1211
1212   const MachineFunction &MF = *MBB->getParent();
1213   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1214   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1215   const MCInstrDesc &MCID = TII.get(ADDriOpc);
1216   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1217   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1218
1219   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1220     .addFrameIndex(FrameIdx).addImm(Offset);
1221 }
1222
1223 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1224                                         int64_t Offset) const {
1225   unsigned FIOperandNum = 0;
1226   while (!MI.getOperand(FIOperandNum).isFI()) {
1227     ++FIOperandNum;
1228     assert(FIOperandNum < MI.getNumOperands() &&
1229            "Instr doesn't have FrameIndex operand!");
1230   }
1231
1232   MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1233   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1234   Offset += MI.getOperand(OffsetOperandNo).getImm();
1235   MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1236
1237   MachineBasicBlock &MBB = *MI.getParent();
1238   MachineFunction &MF = *MBB.getParent();
1239   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1240   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1241   const MCInstrDesc &MCID = MI.getDesc();
1242   MachineRegisterInfo &MRI = MF.getRegInfo();
1243   MRI.constrainRegClass(BaseReg,
1244                         TII.getRegClass(MCID, FIOperandNum, this, MF));
1245 }
1246
1247 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1248                                          unsigned BaseReg,
1249                                          int64_t Offset) const {
1250   unsigned FIOperandNum = 0;
1251   while (!MI->getOperand(FIOperandNum).isFI()) {
1252     ++FIOperandNum;
1253     assert(FIOperandNum < MI->getNumOperands() &&
1254            "Instr doesn't have FrameIndex operand!");
1255   }
1256
1257   unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1258   Offset += MI->getOperand(OffsetOperandNo).getImm();
1259
1260   return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1261          MI->getOpcode() == TargetOpcode::STACKMAP ||
1262          MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1263          (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1264 }